1 The Acorn Electron ULA
2 ======================
3
4 Principal Design and Feature Constraints
5 ----------------------------------------
6
7 The features of the ULA are limited by the amount of time and resources that
8 can be allocated to each activity necessary to support such features given the
9 fundamental obligations of the unit. Maintaining a screen display based on the
10 contents of RAM itself requires the ULA to have exclusive access to such
11 hardware resources for a significant period of time. Whilst other elements of
12 the ULA can in principle run in parallel with this activity, they cannot also
13 access the RAM. Consequently, other features that might use the RAM must
14 accept a reduced allocation of that resource in comparison to a hypothetical
15 architecture where concurrent RAM access is possible.
16
17 Thus, the principal constraint for many features is bandwidth. The duration of
18 access to hardware resources is one aspect of this; the rate at which such
19 resources can be accessed is another. For example, the RAM is not fast enough
20 to support access more frequently than one byte per 2MHz cycle, and for screen
21 modes involving 80 bytes of screen data per scanline, there are no free cycles
22 for anything other than the production of pixel output during the active
23 scanline periods.
24
25 Timing
26 ------
27
28 According to 15.3.2 in the Advanced User Guide, there are 312 scanlines, 256
29 of which are used to generate pixel data. At 50Hz, this means that 128 cycles
30 are spent on each scanline (2000000 cycles / 50 = 40000 cycles; 40000 cycles /
31 312 ~= 128 cycles). This is consistent with the observation that each scanline
32 requires at most 80 bytes of data, and that the ULA is apparently busy for 40
33 out of 64 microseconds in each scanline.
34
35 Access to RAM involves accessing four 64Kb dynamic RAM devices (IC4 to IC7,
36 each providing two bits of each byte) using two cycles within the 500ns period
37 of the 2MHz clock to complete each access operation. Since the CPU and ULA
38 have to take turns in accessing the RAM in MODE 4, 5 and 6, the CPU must
39 effectively run at 1MHz (since every other 500ns period involves the ULA
40 accessing RAM). The CPU is driven by an external clock (IC8) whose 16MHz
41 frequency is divided by the ULA (IC1) depending on the screen mode in use.
42
43 Each 16MHz cycle is approximately 62.5ns. To access the memory, the following
44 patterns corresponding to 16MHz cycles are required:
45
46 Time (ns): 0-------------- 500------------ ...
47 2 MHz cycle: 0 1 ...
48 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
49 ~RAS: 0 1 0 1 ...
50 ~CAS: 0 1 0 1 0 1 0 1 ...
51 A B C A B C ...
52 F S F S ...
53 a b c a b c ...
54
55 Here, "A" and "B" respectively indicate the row and first column addresses
56 being latched into the RAM (on a negative edge for ~RAS and ~CAS
57 respectively), and "C" indicates the second column address being latched into
58 the RAM. Presumably, the first and second half-bytes can be read at "F" and
59 "S" respectively, and the row and column addresses must be made available at
60 "a" and "b" (and "c") respectively at the latest.
61
62 The TM4164EC4-15 has a row address access time of 150ns (maximum) and a column
63 address access time of 90ns (maximum), which appears to mean that
64 approximately two 16MHz cycles after the row address is latched, and one and a
65 half cycles after the column address is latched, the data becomes available.
66
67 Note that the Service Manual refers to the negative edge of RAS and CAS, but
68 the datasheet for the similar TM4164EC4 product shows latching on the negative
69 edge of ~RAS and ~CAS. It is possible that the Service Manual also intended to
70 communicate the latter behaviour. In the TM4164EC4 datasheet, it appears that
71 "page mode" provides the appropriate behaviour for that particular product.
72
73 See: Acorn Electron Advanced User Guide
74 See: Acorn Electron Service Manual
75 http://acorn.chriswhy.co.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf
76 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
77
78 Video Timing
79 ------------
80
81 According to 8.7 in the Service Manual, and the PAL Wikipedia page,
82 approximately 4.7µs is used for the sync pulse, 5.7µs for the "back porch"
83 (including the "colour burst"), and 1.65µs for the "front porch", totalling
84 12.05µs and thus leaving 51.95µs for the active video signal for each
85 scanline. As the Service Manual suggests in the oscilloscope traces, the
86 display information is transmitted more or less centred within the active
87 video period since the ULA will only be providing pixel data for 40µs in each
88 scanline.
89
90 Each 62.5ns cycle happens to correspond to 64µs divided by 1024, meaning that
91 each scanline can be divided into 1024 cycles, although only 640 at most are
92 actively used to provide pixel data. Pixel data production should only occur
93 within a certain period on each scanline, approximately 262 cycles after the
94 start of hsync:
95
96 active video period = 51.95µs
97 pixel data period = 40µs
98 total silent period = 51.95µs - 40µs = 11.95µs
99 silent periods (before and after) = 11.95µs / 2 = 5.975µs
100 hsync and back porch period = 4.7µs + 5.7µs = 10.4µs
101 time before pixel data period = 10.4µs + 5.975µs = 16.375µs
102 pixel data period start cycle = 16.375µs / 62.5ns = 262
103
104 By choosing a number divisible by 8, the RAM access mechanism can be
105 synchronised with the pixel production. Thus, 264 is a more appropriate start
106 cycle.
107
108 The "vertical blanking period", meaning the period before picture information
109 in each field is 25 lines out of 312 (strictly 312.5) and thus lasts for
110 1.6ms. Of this, 2.5 lines occur before the vsync (field sync) which also lasts
111 for 2.5 lines. Thus, the first visible scanline on the first field of a frame
112 occurs half way through the 23rd scanline period measured from the start of
113 vsync:
114
115 10 20 23
116 Line in frame: 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8
117 Line from 1: 0 22 3
118 Line on screen: .:::::VVVVV::::: 12233445566
119 |_________________________________________________|
120 25 line vertical blanking period
121
122 In the second field of a frame, the first visible scanline coincides with the
123 24th scanline period measured from the start of line 313 in the frame:
124
125 310 336
126 Line in frame: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
127 Line from 313: 0 23
128 Line on screen: 88:::::VVVVV:::: 11223344
129 288 | |
130 |_________________________________________________|
131 25 line vertical blanking period
132
133 In order to consider only full lines, we might consider the start of each
134 frame to occur 23 lines after the start of vsync.
135
136 Again, it is likely that pixel data production should only occur on scanlines
137 within a certain period on each frame. The "625/50" document indicates that
138 only a certain region is "safe" to use, suggesting a vertically centred region
139 with approximately 15 blank lines above and below the picture. Thus, the start
140 of the picture could be chosen as 38 lines after the start of vsync.
141
142 See: http://en.wikipedia.org/wiki/PAL
143 See: http://en.wikipedia.org/wiki/Analog_television#Structure_of_a_video_signal
144 See: The 625/50 PAL Video Signal and TV Compatible Graphics Modes
145 http://lipas.uwasa.fi/~f76998/video/modes/
146 See: PAL TV timing and voltages
147 http://www.retroleum.co.uk/electronics-articles/pal-tv-timing-and-voltages/
148 See: Line Standards
149 http://www.pembers.freeserve.co.uk/World-TV-Standards/Line-Standards.html
150
151 RAM Integrated Circuits
152 -----------------------
153
154 Unicorn Electronics appears to offer 4164 RAM chips (as well as 6502 series
155 CPUs such as the 6502, 6502A, 6502B and 65C02). These 4164 devices are
156 available in 100ns (4164-100), 120ns (4164-120) and 150ns (4164-150) variants,
157 have 16 pins and address 65536 bits through a 1-bit wide channel.
158
159 The documentation for the Electron mentions 4164-15 RAM chips for IC4-7, and
160 the Samsung-produced KM41464 series is apparently equivalent to the Texas
161 Instruments 4164 chips presumably used in the Electron.
162
163 The TM4164EC4 series combines 4 64K x 1b units into a single package and
164 appears similar to the TM4164EA4 featured on the Electron's circuit diagram
165 (in the Advanced User Guide but not the Service Manual), and it also has 22
166 pins providing 3 additional inputs and 3 additional outputs over the 16 pins
167 of the individual 4164-15 modules, presumably allowing concurrent access to
168 the packaged memory units.
169
170 As far as currently available replacements are concerned, the NTE4164 is a
171 potential candidate: according to the Vetco Electronics entry, it is
172 supposedly a replacement for the TMS4164-15 amongst many other parts. Similar
173 parts include the NTE2164 and the NTE6664, both of which appear to have
174 largely the same performance and connection characteristics. Meanwhile, the
175 NTE21256 appears to be a 16-pin replacement with four times the capacity that
176 maintains the single data input and output pins. Using the NTE21256 as a
177 replacement for all ICs combined would be difficult because of the single bit
178 output.
179
180 Another device equivalent to the 4164-15 appears to be available under the
181 code 41662 from Jameco Electronics as the Siemens HYB 4164-2. The Jameco Web
182 site lists data sheets for other devices on the same page, but these are
183 different and actually appear to be provided under the 41574 product code (but
184 are listed under 41464-10) and appear to be replacements for the TM4164EC4:
185 the Samsung KM41464A-15 and NEC µPD41464 employ 18 pins, eliminating 4 pins by
186 employing 4 pins for both input and output.
187
188 Pins I/O pins Row access Column access
189 ---- -------- ---------- -------------
190 TM4164EC4 22 4 + 4 150ns (15) 90ns (15)
191 KM41464AP 18 4 150ns (15) 75ns (15)
192 NTE21256 16 1 + 1 150ns 75ns
193 HYB 4164-2 16 1 + 1 150ns 100ns
194 µPD41464 18 4 120ns (12) 60ns (12)
195
196 See: TM4164EC4 65,536 by 4-Bit Dynamic RAM Module
197 http://www.datasheetarchive.com/dl/Datasheets-112/DSAP0051030.pdf
198 See: Dynamic RAMS
199 http://www.unicornelectronics.com/IC/DYNAMIC.html
200 See: KM4164B 64K x 1 Bit Dynamic RAM with Page Mode
201 http://images.ihscontent.net/vipimages/VipMasterIC/IC/SAMS/SAMSD020/SAMSD020-45.pdf
202 See: NTE2164 Integrated Circuit 65,536 X 1 Bit Dynamic Random Access Memory
203 http://www.vetco.net/catalog/product_info.php?products_id=2806
204 See: NTE4164 - IC-NMOS 64K DRAM 150NS
205 http://www.vetco.net/catalog/product_info.php?products_id=3680
206 See: NTE21256 - IC-256K DRAM 150NS
207 http://www.vetco.net/catalog/product_info.php?products_id=2799
208 See: NTE21256 262,144-Bit Dynamic Random Access Memory (DRAM)
209 http://www.nteinc.com/specs/21000to21999/pdf/nte21256.pdf
210 See: NTE6664 - IC-MOS 64K DRAM 150NS
211 http://www.vetco.net/catalog/product_info.php?products_id=5213
212 See: NTE6664 Integrated Circuit 64K-Bit Dynamic RAM
213 http://www.nteinc.com/specs/6600to6699/pdf/nte6664.pdf
214 See: 4164-150: MAJOR BRANDS
215 http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41662_-1
216 See: HYB 4164-1, HYB 4164-2, HYB 4164-3 65,536-Bit Dynamic Random Access Memory (RAM)
217 http://www.jameco.com/Jameco/Products/ProdDS/41662SIEMENS.pdf
218 See: KM41464A NMOS DRAM 64K x 4 Bit Dynamic RAM with Page Mode
219 http://www.jameco.com/Jameco/Products/ProdDS/41662SAM.pdf
220 See: NEC µ41464 65,536 x 4-Bit Dynamic NMOS RAM
221 http://www.jameco.com/Jameco/Products/ProdDS/41662NEC.pdf
222 See: 41464-10: MAJOR BRANDS
223 http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41574_-1
224
225 Interrupts
226 ----------
227
228 The ULA generates IRQs (maskable interrupts) according to certain conditions
229 and these conditions are controlled by location &FE00:
230
231 * Vertical sync (bottom of displayed screen)
232 * 50MHz real time clock
233 * Transmit data empty
234 * Receive data full
235 * High tone detect
236
237 The ULA is also used to clear interrupt conditions through location &FE05. Of
238 particular significance is bit 7, which must be set if an NMI (non-maskable
239 interrupt) has occurred and has thus suspended ULA access to memory, restoring
240 the normal function of the ULA.
241
242 ROM Paging
243 ----------
244
245 Accessing different ROMs involves bits 0 to 3 of &FE05. Some special ROM
246 mappings exist:
247
248 8 keyboard
249 9 keyboard (duplicate)
250 10 BASIC ROM
251 11 BASIC ROM (duplicate)
252
253 Paging in a ROM involves the following procedure:
254
255 1. Assert ROM page enable (bit 3) together with a ROM number n in bits 0 to
256 2, corresponding to ROM number 8+n, such that one of ROMs 12 to 15 is
257 selected.
258 2. Where a ROM numbered from 0 to 7 is to be selected, set bit 3 to zero
259 whilst writing the desired ROM number n in bits 0 to 2.
260
261 Shadow/Expanded Memory
262 ----------------------
263
264 The Electron exposes all sixteen address lines and all eight data lines
265 through the expansion bus. Using such lines, it is possible to provide
266 additional memory - typically sideways ROM and RAM - on expansion cards and
267 through cartridges, although the official cartridge specification provides
268 fewer address lines and only seeks to provide access to memory in 16K units.
269
270 Various modifications and upgrades were developed to offer "turbo"
271 capabilities to the Electron, permitting the CPU to access a separate 8K of
272 RAM at 2MHz, presumably preventing access to the low 8K of RAM accessible via
273 the ULA through additional logic. However, an enhanced ULA might support
274 independent CPU access to memory over the expansion bus by allowing itself to
275 be discharged from providing access to memory, potentially for a range of
276 addresses, and for the CPU to communicate with external memory uninterrupted.
277
278 Hardware Scrolling
279 ------------------
280
281 On the standard ULA, &FE02 and &FE03 map to a 9 significant bits address with
282 the least significant 5 bits being zero, thus limiting the scrolling
283 resolution to 64 bytes. An enhanced ULA could support a resolution of 2 bytes
284 using the same layout of these addresses.
285
286 |--&FE02--------------| |--&FE03--------------|
287 XX XX 14 13 12 11 10 09 08 07 06 XX XX XX XX XX
288
289 XX 14 13 12 11 10 09 08 07 06 05 04 03 02 01 XX
290
291 Arguably, a resolution of 8 bytes is more useful, since the mapping of screen
292 memory to pixel locations is character oriented. A change in 8 bytes would
293 permit a horizontal scrolling resolution of 2 pixels in MODE 2, 4 pixels in
294 MODE 1 and 5, and 8 pixels in MODE 0, 3 and 6. This resolution is actually
295 observed on the BBC Micro (see 18.11.2 in the BBC Microcomputer Advanced User
296 Guide).
297
298 One argument for a 2 byte resolution is smooth vertical scrolling. A pitfall
299 of changing the screen address by 2 bytes is the change in the number of lines
300 from the initial and final character rows that need reading by the ULA, which
301 would need to maintain this state information (although this is a relatively
302 trivial change). Another pitfall is the complication that might be introduced
303 to software writing bitmaps of character height to the screen.
304
305 Enhancement: Region Blanking
306 ----------------------------
307
308 The problem of permitting character-oriented blitting in programs whilst
309 scrolling the screen by sub-character amounts could be mitigated by permitting
310 a region of the display to be blank, such as the final lines of the display.
311 Consider the following vertical scrolling by 2 bytes that would cause an
312 initial character row of 6 lines and a final character row of 2 lines:
313
314 6 lines - initial, partial character row
315 248 lines - 31 complete rows
316 2 lines - final, partial character row
317
318 If a routine were in use that wrote 8 line bitmaps to the partial character
319 row now split in two, it would be advisable to hide one of the regions in
320 order to prevent content appearing in the wrong place on screen (such as
321 content meant to appear at the top "leaking" onto the bottom). Blanking 6
322 lines would be sufficient, as can be seen from the following cases.
323
324 Scrolling up by 2 lines:
325
326 6 lines - initial, partial character row
327 240 lines - 30 complete rows
328 4 lines - part of 1 complete row
329 -----------------------------------------------------------------
330 4 lines - part of 1 complete row (hidden to maintain 250 lines)
331 2 lines - final, partial character row (hidden)
332
333 Scrolling down by 2 lines:
334
335 2 lines - initial, partial character row
336 248 lines - 31 complete rows
337 ----------------------------------------------------------
338 6 lines - final, partial character row (hidden)
339
340 Thus, in this case, region blanking would impose a 250 line display with the
341 bottom 6 lines blank.
342
343 See the description of the display suspend enhancement for a more efficient
344 way of blanking lines whilst allowing the CPU to perform useful work during
345 the blanking period.
346
347 Enhancement: Screen Height Adjustment
348 -------------------------------------
349
350 The height of the screen could be configurable in order to reduce screen
351 memory consumption. This is not quite done in MODE 3 and 6 since the start of
352 the screen appears to be rounded down to the nearest page, but by reducing the
353 height by amounts more than a page, savings would be possible. For example:
354
355 Screen width Depth Height Bytes per line Saving in bytes Start address
356 ------------ ----- ------ -------------- --------------- -------------
357 640 1 252 80 320 &3140 -> &3100
358 640 1 248 80 640 &3280 -> &3200
359 320 1 240 40 640 &5A80 -> &5A00
360 320 2 240 80 1280 &3500
361
362 Screen Mode Selection
363 ---------------------
364
365 Bits 3, 4 and 5 of address &FE*7 control the selected screen mode. For a wider
366 range of modes, the other bits of &FE*7 (related to sound, cassette
367 input/output and the Caps Lock LED) would need to be reassigned and bit 0
368 potentially being made available for use.
369
370 Enhancement: Palette Definition
371 -------------------------------
372
373 Since all memory accesses go via the ULA, an enhanced ULA could employ more
374 specific addresses than &FE*X to perform enhanced functions. For example, the
375 palette control is done using &FE*8-F and merely involves selecting predefined
376 colours, whereas an enhanced ULA could support the redefinition of all 16
377 colours using specific ranges such as &FE18-F (colours 0 to 7) and &FE28-F
378 (colours 8 to 15), where a single byte might provide 8 bits per pixel colour
379 specifications similar to those used on the Archimedes.
380
381 The principal limitation here is actually the hardware: the Electron has only
382 a single output line for each of the red, green and blue channels, and if
383 those outputs are strictly digital and can only be set to a "high" and "low"
384 value, then only the existing eight colours are possible. If a modern ULA were
385 able to output analogue values, it would still need to be assessed whether the
386 circuitry could successfully handle and propagate such values. Various sources
387 indicate that only "TTL levels" are supported by the RGB output circuit, and
388 since there are 74LS08 AND logic gates involved in the RGB component outputs
389 from the ULA, it is likely that the ULA is expected to provide only "high" or
390 "low" values.
391
392 Short of adding extra outputs from the ULA (either additional red, green and
393 blue outputs or a combined intensity output, the former employed on the
394 Amstrad CPC series), another approach might involve some kind of modulation
395 where an output value might be encoded in multiple pulses at a higher
396 frequency than the pixel frequency. However, this would demand additional
397 circuitry outside the ULA, and component RGB monitors would probably not be
398 able to take advantage of this feature; only UHF and composite video devices
399 (the latter with the composite video colour support enabled on the Electron's
400 circuit board) would potentially benefit.
401
402 Flashing Colours
403 ----------------
404
405 According to the Advanced User Guide, "The cursor and flashing colours are
406 entirely generated in software: This means that all of the logical to physical
407 colour map must be changed to cause colours to flash." This appears to suggest
408 that the palette registers must be updated upon the flash counter - read and
409 written by OSBYTE &C1 (193) - reaching zero and that some way of changing the
410 colour pairs to be any combination of colours might be possible, instead of
411 having colour complements as pairs.
412
413 It is conceivable that the interrupt code responsible does the simple thing
414 and merely inverts the current values for any logical colours (LC) for which
415 the associated physical colour (as supplied as the second parameter to the VDU
416 19 call) has the top bit of its four bit value set. These top bits are not
417 recorded in the palette registers but are presumably recorded separately and
418 used to build bitmaps as follows:
419
420 LC 2 colour 4 colour 16 colour 4-bit value for inversion
421 -- -------- -------- --------- -------------------------
422 0 00010001 00010001 00010001 1, 1, 1
423 1 01000100 00100010 00010001 4, 2, 1
424 2 01000100 00100010 4, 2
425 3 10001000 00100010 8, 2
426 4 00010001 1
427 5 00010001 1
428 6 00100010 2
429 7 00100010 2
430 8 01000100 4
431 9 01000100 4
432 10 10001000 8
433 11 10001000 8
434 12 01000100 4
435 13 01000100 4
436 14 10001000 8
437 15 10001000 8
438
439 Inversion value calculation:
440
441 2 colour formula: 1 << (colour * 2)
442 4 colour formula: 1 << colour
443 16 colour formula: 1 << ((colour & 2) + ((colour & 8) * 2))
444
445 For example, where logical colour 0 has been mapped to a physical colour in
446 the range 8 to 15, a bitmap of 00010001 would be chosen as its contribution to
447 the inversion operation. (The lower three bits of the physical colour would be
448 used to set the underlying colour information affected by the inversion
449 operation.)
450
451 An operation in the interrupt code would then combine the bitmaps for all
452 logical colours in 2 and 4 colour modes, with the 16 colour bitmaps being
453 combined for groups of logical colours as follows:
454
455 Logical colours
456 ---------------
457 0, 2, 8, 10
458 4, 6, 12, 14
459 5, 7, 13, 15
460 1, 3, 9, 11
461
462 These combined bitmaps would be EORed with the existing palette register
463 values in order to perform the value inversion necessary to produce the
464 flashing effect.
465
466 Thus, in the VDU 19 operation, the appropriate inversion value would be
467 calculated for the logical colour, and this value would then be combined with
468 other inversion values in a dedicated memory location corresponding to the
469 colour's group as indicated above. Meanwhile, the palette channel values would
470 be derived from the lower three bits of the specified physical colour and
471 combined with other palette data in dedicated memory locations corresponding
472 to the palette registers.
473
474 Enhancement: Palette Definition Lists
475 -------------------------------------
476
477 It can be useful to redefine the palette in order to change the colours
478 available for a particular region of the screen, particularly in modes where
479 the choice of colours is constrained, and if an increased colour depth were
480 available, palette redefinition would be useful to give the illusion of more
481 than 16 colours in MODE 2. Traditionally, palette redefinition has been done
482 by using interrupt-driven timers, but a more efficient approach would involve
483 presenting lists of palette definitions to the ULA so that it can change the
484 palette at a particular display line.
485
486 One might define a palette redefinition list in a region of memory and then
487 communicate its contents to the ULA by writing the address and length of the
488 list, along with the display line at which the palette is to be changed, to
489 ULA registers such that the ULA buffers the list and performs the redefinition
490 at the appropriate time. Throughput/bandwidth considerations might impose
491 restrictions on the practical length of such a list, however.
492
493 Enhancement: Palette-Free Modes
494 -------------------------------
495
496 Palette-free modes might be defined where bit values directly correspond to
497 the red, green and blue channels, although this would mostly make sense only
498 for modes with depths greater than the standard 4 bits per pixel, and such
499 modes would require more memory than MODE 2 if they were to have an acceptable
500 resolution.
501
502 Enhancement: Display Suspend
503 ----------------------------
504
505 Especially when writing to the screen memory, it could be beneficial to be
506 able to suspend the ULA's access to the memory, instead producing blank values
507 for all screen pixels until a program is ready to reveal the screen. This is
508 different from palette blanking since with a blank palette, the ULA is still
509 reading screen memory and translating its contents into pixel values that end
510 up being blank.
511
512 This function is reminiscent of a capability of the ZX81, albeit necessary on
513 that hardware to reduce the load on the system CPU which was responsible for
514 producing the video output. By allowing display suspend on the Electron, the
515 performance benefit would be derived from giving the CPU full access to the
516 memory bandwidth.
517
518 Enhancement: Memory Filling
519 ---------------------------
520
521 A capability that could be given to an enhanced ULA is that of permitting the
522 ULA to write to screen memory as well being able to read from it. Although
523 such a capability would probably not be useful in conjunction with the
524 existing read operations when producing a screen display, and insufficient
525 bandwidth would exist to do so in high-bandwidth screen modes anyway, the
526 capability could be offered during a display suspend period (as described
527 above), permitting a more efficient mechanism to rapidly fill memory with a
528 predetermined value.
529
530 This capability could also support block filling, where the limits of the
531 filled memory would be defined by the position and size of a screen area,
532 although this would demand the provision of additional registers in the ULA to
533 retain the details of such areas and additional logic to control the fill
534 operation.
535
536 Enhancement: Region Filling
537 ---------------------------
538
539 An alternative to memory writing might involve indicating regions using
540 additional registers or memory where the ULA fills regions of the screen with
541 content instead of reading from memory. Unlike hardware sprites which should
542 realistically provide varied content, region filling could employ single
543 colours or patterns, and one advantage of doing so would be that the ULA need
544 not access memory at all within a particular region.
545
546 Regions would be defined on a row-by-row basis. Instead of reading memory and
547 blitting a direct representation to the screen, the ULA would read region
548 definitions containing a start column, region width and colour details. There
549 might be a certain number of definitions allowed per row, or the ULA might
550 just traverse an ordered list of such definitions with each one indicating the
551 row, start column, region width and colour details.
552
553 One could even compress this information further by requiring only the row,
554 start column and colour details with each subsequent definition terminating
555 the effect of the previous one. However, one would also need to consider the
556 convenience of preparing such definitions and whether efficient access to
557 definitions for a particular row might be desirable. It might also be
558 desirable to avoid having to prepare definitions for "empty" areas of the
559 screen, effectively making the definition of the screen contents employ
560 run-length encoding and employ only colour plus length information.
561
562 One application of region filling is that of simple 2D and 3D shape rendering.
563 Although it is entirely possible to plot such shapes to the screen and have
564 the ULA blit the memory contents to the screen, such operations consume
565 bandwidth both in the initial plotting and in the final transfer to the
566 screen. Region filling would reduce such bandwidth usage substantially.
567
568 This way of representing screen images would make certain kinds of images
569 unfeasible to represent - consider alternating single pixel values which could
570 easily occur in some character bitmaps - even if an internal queue of regions
571 were to be supported such that the ULA could read ahead and buffer such
572 "bandwidth intensive" areas. Thus, the ULA might be better served providing
573 this feature for certain areas of the display only as some kind of special
574 graphics window.
575
576 Enhancement: Hardware Sprites
577 -----------------------------
578
579 An enhanced ULA might provide hardware sprites, but this would be done in an
580 way that is incompatible with the standard ULA, since no &FE*X locations are
581 available for allocation. To keep the facility simple, hardware sprites would
582 have a standard byte width and height.
583
584 The specification of sprites could involve the reservation of 16 locations
585 (for example, &FE20-F) specifying a fixed number of eight sprites, with each
586 location pair referring to the sprite data. By limiting the ULA to dealing
587 with a fixed number of sprites, the work required inside the ULA would be
588 reduced since it would avoid having to deal with arbitrary numbers of sprites.
589
590 The principal limitation on providing hardware sprites is that of having to
591 obtain sprite data, given that the ULA is usually required to retrieve screen
592 data, and given the lack of memory bandwidth available to retrieve sprite data
593 (particularly from multiple sprites supposedly at the same position) and
594 screen data simultaneously. Although the ULA could potentially read sprite
595 data and screen data in alternate memory accesses in screen modes where the
596 bandwidth is not already fully utilised, this would result in a degradation of
597 performance.
598
599 Enhancement: Additional Screen Mode Configurations
600 --------------------------------------------------
601
602 Alternative screen mode configurations could be supported. The ULA has to
603 produce 640 pixel values across the screen, with pixel doubling or quadrupling
604 employed to fill the screen width:
605
606 Screen width Columns Scaling Depth Bytes
607 ------------ ------- ------- ----- -----
608 640 80 x1 1 80
609 320 40 x2 1, 2 40, 80
610 160 20 x4 2, 4 40, 80
611
612 It must also use at most 80 byte-sized memory accesses to provide the
613 information for the display. Given that characters must occupy an 8x8 pixel
614 array, if a configuration featuring anything other than 20, 40 or 80 character
615 columns is to be supported, compromises must be made such as the introduction
616 of blank pixels either between characters (such as occurs between rows in MODE
617 3 and 6) or at the end of a scanline (such as occurs at the end of the frame
618 in MODE 3 and 6). Consider the following configuration:
619
620 Screen width Columns Scaling Depth Bytes Blank
621 ------------ ------- ------- ----- ------ -----
622 208 26 x3 1, 2 26, 52 16
623
624 Here, if the ULA can triple pixels, a 26 column mode with either 2 or 4
625 colours could be provided, with 16 blank pixel values (out of a total of 640)
626 generated either at the start or end (or split between the start and end) of
627 each scanline.
628
629 Enhancement: Character Attributes
630 ---------------------------------
631
632 The BBC Micro MODE 7 employs something resembling character attributes to
633 support teletext displays, but depends on circuitry providing a character
634 generator. The ZX Spectrum, on the other hand, provides character attributes
635 as a means of colouring bitmapped graphics. Although such a feature is very
636 limiting as the sole means of providing multicolour graphics, in situations
637 where the choice is between low resolution multicolour graphics or high
638 resolution monochrome graphics, character attributes provide a potentially
639 useful compromise.
640
641 For each byte read, the ULA must deliver 8 pixel values (out of a total of
642 640) to the video output, doing so by either emptying its pixel buffer on a
643 pixel per cycle basis, or by multiplying pixels and thus holding them for more
644 than one cycle. For example for a screen mode having 640 pixels in width:
645
646 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
647 Reads: B B
648 Pixels: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
649
650 And for a screen mode having 320 pixels in width:
651
652 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
653 Reads: B
654 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
655
656 However, in modes where less than 80 bytes are required to generate the pixel
657 values, an enhanced ULA might be able to read additional bytes between those
658 providing the bitmapped graphics data:
659
660 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
661 Reads: B A
662 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
663
664 These additional bytes could provide colour information for the bitmapped data
665 in the following character column (of 8 pixels). Since it would be desirable
666 to apply attribute data to the first column, the initial 8 cycles might be
667 configured to not produce pixel values.
668
669 For an entire character, attribute data need only be read for the first row of
670 pixels for a character. The subsequent rows would have attribute information
671 applied to them, although this would require the attribute data to be stored
672 in some kind of buffer. Thus, the following access pattern would be observed:
673
674 Cycle: A B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ...
675
676 A whole byte used for colour information for a whole character would result in
677 a choice of 256 colours, and this might be somewhat excessive. By only reading
678 attribute bytes at every other opportunity, a choice of 16 colours could be
679 applied individually to two characters.
680
681 Cycle: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
682 Reads: B A B -
683 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
684
685 Further reductions in attribute data access, offering 4 colours for every
686 character in a four character block, for example, might also be worth
687 considering.
688
689 Consider the following configurations for screen modes with a colour depth of
690 1 bit per pixel for bitmap information:
691
692 Screen width Columns Scaling Bytes (B) Bytes (A) Colours Screen start
693 ------------ ------- ------- --------- --------- ------- ------------
694 320 40 x2 40 40 256 &5300
695 320 40 x2 40 20 16 &5580 -> &5500
696 320 40 x2 40 10 4 &56C0 -> &5600
697 208 26 x3 26 26 256 &62C0 -> &6200
698 208 26 x3 26 13 16 &6460 -> &6400
699
700 Enhancement: MODE 7 Emulation using Character Attributes
701 --------------------------------------------------------
702
703 If the scheme of applying attributes to character regions were employed to
704 emulate MODE 7, in conjunction with the MODE 6 display technique, the
705 following configuration would be required:
706
707 Screen width Columns Rows Bytes (B) Bytes (A) Colours Screen start
708 ------------ ------- ---- --------- --------- ------- ------------
709 320 40 25 40 20 16 &5ECC -> &5E00
710 320 40 25 40 10 4 &5FC6 -> &5F00
711
712 Although this requires much more memory than MODE 7 (8500 bytes versus MODE
713 7's 1000 bytes), it does not need much more memory than MODE 6, and it would
714 at least make a limited 40-column multicolour mode available as a substitute
715 for MODE 7.
716
717 Enhancement: High Resolution Graphics and Mode Layouts
718 ------------------------------------------------------
719
720 Screen modes with different screen memory mappings, higher resolutions and
721 larger colour depths might be possible, but this would in most cases involve
722 the allocation of more screen memory, and the ULA would probably then be
723 obliged to page in such memory for the CPU to be able to sensibly access it
724 all. Merely changing the memory mappings in order to have Archimedes-style
725 row-oriented screen addresses (instead of character-oriented addresses) could
726 be done for the existing modes, but this might not be sufficiently beneficial,
727 especially since accessing regions of the screen would involve incrementing
728 pointers by amounts that are inconvenient on an 8-bit CPU.
729
730 Enhancement: Genlock Support
731 ----------------------------
732
733 The ULA generates a video signal in conjunction with circuitry producing the
734 output features necessary for the correct display of the screen image.
735 However, it appears that the ULA drives the video synchronisation mechanism
736 instead of reacting to an existing signal. Genlock support might be possible
737 if the ULA were made to be responsive to such external signals, resetting its
738 address generators upon receiving synchronisation events.
739
740 Enhancement: Improved Sound
741 ---------------------------
742
743 The standard ULA reserves &FE*6 for sound generation and cassette input/output
744 (with bits 1 and 2 of &FE*7 being used to select either sound generation or
745 cassette I/O), thus making it impossible to support multiple channels within
746 the given framework. The BBC Micro ULA employs &FE40-&FE4F for sound control,
747 and an enhanced ULA could adopt this interface.
748
749 The BBC Micro uses the SN76489 chip to produce sound, and the entire
750 functionality of this chip could be emulated for enhanced sound, with a subset
751 of the functionality exposed via the &FE*6 interface.
752
753 See: http://en.wikipedia.org/wiki/Texas_Instruments_SN76489
754
755 Enhancement: Waveform Upload
756 ----------------------------
757
758 As with a hardware sprite function, waveforms could be uploaded or referenced
759 using locations as registers referencing memory regions.
760
761 Enhancement: Sound Input/Output
762 -------------------------------
763
764 Since the ULA already controls audio input/output for cassette-based data, it
765 would have been interesting to entertain the idea of sampling and output of
766 sounds through the cassette interface. However, a significant amount of
767 circuitry is employed to process the input signal for use by the ULA and to
768 process the output signal for recording.
769
770 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw_03.htm#3.11
771
772 Enhancement: BBC ULA Compatibility
773 ----------------------------------
774
775 Although some new ULA functions could be defined in a way that is also
776 compatible with the BBC Micro, the BBC ULA is itself incompatible with the
777 Electron ULA: &FE00-7 is reserved for the video controller in the BBC memory
778 map, but controls various functions specific to the 6845 video controller;
779 &FE08-F is reserved for the serial controller. It therefore becomes possible
780 to disregard compatibility where compatibility is already disregarded for a
781 particular area of functionality.
782
783 &FE20-F maps to video ULA functionality on the BBC Micro which provides
784 control over the palette (using address &FE21, compared to &FE07-F on the
785 Electron) and other system-specific functions. Since the location usage is
786 generally incompatible, this region could be reused for other purposes.
787
788 Enhancement: Increased RAM, ULA and CPU Performance
789 ---------------------------------------------------
790
791 More modern implementations of the hardware might feature faster RAM coupled
792 with an increased ULA clock frequency in order to increase the bandwidth
793 available to the ULA and to the CPU in situations where the ULA is not needed
794 to perform work. A ULA employing a 32MHz clock would be able to complete the
795 retrieval of a byte from RAM in only 250ns and thus be able to enable the CPU
796 to access the RAM for the following 250ns even in display modes requiring the
797 retrieval of a byte for the display every 500ns. The CPU could, subject to
798 timing issues, run at 2MHz even in MODE 0, 1 and 2.
799
800 A scheme such as that described above would have a similar effect to the
801 scheme employed in the BBC Micro, although the latter made use of RAM with a
802 wider bandwidth in order to complete memory transfers within 250ns and thus
803 permit the CPU to run continuously at 2MHz.
804
805 Higher bandwidth could potentially be used to implement exotic features such
806 as RAM-resident hardware sprites or indeed any feature demanding RAM access
807 concurrent with the production of the display image.
808
809 ULA Pin Functions
810 -----------------
811
812 The functions of the ULA pins are described in the Electron Service Manual. Of
813 interest to video processing are the following:
814
815 CSYNC (low during horizontal or vertical synchronisation periods, high
816 otherwise)
817
818 HS (low during horizontal synchronisation periods, high otherwise)
819
820 RED, GREEN, BLUE (pixel colour outputs)
821
822 CLOCK IN (a 16MHz clock input, 4V peak to peak)
823
824 PHI OUT (a 1MHz, 2MHz and stopped clock signal for the CPU)
825
826 More general memory access pins:
827
828 RAM0...RAM3 (data lines to/from the RAM)
829
830 RA0...RA7 (address lines for sending both row and column addresses to the RAM)
831
832 RAS (row address strobe setting the row address on a negative edge - see the
833 timing notes)
834
835 CAS (column address strobe setting the column address on a negative edge -
836 see the timing notes)
837
838 WE (sets write enable with logic 0, read with logic 1)
839
840 ROM (select data access from ROM)
841
842 CPU-oriented memory access pins:
843
844 A0...A15 (CPU address lines)
845
846 PD0...PD7 (CPU data lines)
847
848 R/W (indicates CPU write with logic 0, CPU read with logic 1)
849
850 Interrupt-related pins:
851
852 NMI (CPU request for uninterrupted 1MHz access to memory)
853
854 IRQ (signal event to CPU)
855
856 POR (power-on reset, resetting the ULA on a positive edge and asserting the
857 CPU's RST pin)
858
859 RST (master reset for the CPU signalled on power-up and by the Break key)
860
861 Keyboard-related pins:
862
863 KBD0...KBD3 (keyboard inputs)
864
865 CAPS LOCK (control status LED)
866
867 Sound-related pins:
868
869 SOUND O/P (sound output using internal oscillator)
870
871 Cassette-related pins:
872
873 CAS IN (cassette circuit input, between 0.5V to 2V peak to peak)
874
875 CAS OUT (pseudo-sinusoidal output, 1.8V peak to peak)
876
877 CAS RC (detect high tone)
878
879 CAS MO (motor relay output)
880
881 ÷13 IN (~1200 baud clock input)
882
883 References
884 ----------
885
886 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw.htm
887
888 About this Document
889 -------------------
890
891 The most recent version of this document and accompanying distribution should
892 be available from the following location:
893
894 http://hgweb.boddie.org.uk/ULA
895
896 Copyright and licence information can be found in the docs directory of this
897 distribution - see docs/COPYING.txt for more information.