1 The Acorn Electron ULA
2 ======================
3
4 Principal Design and Feature Constraints
5 ----------------------------------------
6
7 The features of the ULA are limited in sophistication by the amount of time
8 and resources that can be allocated to each activity supporting the
9 fundamental features and obligations of the unit. Maintaining a screen display
10 based on the contents of RAM itself requires the ULA to have exclusive access
11 to various hardware resources for a significant period of time.
12
13 Whilst other elements of the ULA can in principle run in parallel with the
14 display refresh activity, they cannot also access the RAM at the same time.
15 Consequently, other features that might use the RAM must accept a reduced
16 allocation of that resource in comparison to a hypothetical architecture where
17 concurrent RAM access is possible at all times.
18
19 Thus, the principal constraint for many features is bandwidth. The duration of
20 access to hardware resources is one aspect of this; the rate at which such
21 resources can be accessed is another. For example, the RAM is not fast enough
22 to support access more frequently than one byte per 2MHz cycle, and for screen
23 modes involving 80 bytes of screen data per scanline, there are no free cycles
24 for anything other than the production of pixel output during the active
25 scanline periods.
26
27 Another constraint is imposed by the method of RAM access provided by the ULA.
28 The ULA is able to access RAM by fetching 4 bits at a time and thus managing
29 to transfer 8 bits within a single 2MHz cycle, this being sufficient to
30 provide display data for the most demanding screen modes. However, this
31 mechanism's timing requirements are beyond the capabilities of the CPU when
32 running at 2MHz.
33
34 Consequently, the CPU will only ever be able to access RAM via the ULA at
35 1MHz, even when the ULA is not accessing the RAM. Fortunately, when needing to
36 refresh the display, the ULA is still able to make use of the idle part of
37 each 1MHz cycle (or, rather, the idle 2MHz cycle unused by the CPU) to itself
38 access the RAM at a rate of 1 byte per 1MHz cycle (or 1 byte every other 2MHz
39 cycle), thus supporting the less demanding screen modes.
40
41 Timing
42 ------
43
44 According to 15.3.2 in the Advanced User Guide, there are 312 scanlines, 256
45 of which are used to generate pixel data. At 50Hz, this means that 128 cycles
46 are spent on each scanline (2000000 cycles / 50 = 40000 cycles; 40000 cycles /
47 312 ~= 128 cycles). This is consistent with the observation that each scanline
48 requires at most 80 bytes of data, and that the ULA is apparently busy for 40
49 out of 64 microseconds in each scanline.
50
51 (In fact, since the ULA is seeking to provide an image for an interlaced
52 625-line display, there are in fact two "fields" involved, one providing 312
53 scanlines and one providing 313 scanlines. See below for a description of the
54 video system.)
55
56 Access to RAM involves accessing four 64Kb dynamic RAM devices (IC4 to IC7,
57 each providing two bits of each byte) using two cycles within the 500ns period
58 of the 2MHz clock to complete each access operation. Since the CPU and ULA
59 have to take turns in accessing the RAM in MODE 4, 5 and 6, the CPU must
60 effectively run at 1MHz (since every other 500ns period involves the ULA
61 accessing RAM) during transfers of screen data.
62
63 The CPU is driven by an external clock (IC8) whose 16MHz frequency is divided
64 by the ULA (IC1) depending on the screen mode in use. Each 16MHz cycle is
65 approximately 62.5ns. To access the memory, the following patterns
66 corresponding to 16MHz cycles are required:
67
68 Time (ns): 0-------------- 500------------- ...
69 2 MHz cycle: 0 1 ...
70 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
71 /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ ...
72 ~RAS: /---\___________/---\___________ ...
73 ~CAS: /-----\___/-\___/-----\___/-\___ ...
74 Address events: A B C A B C ...
75 Data events: F S F S ...
76
77 ~RAS ops: 1 0 1 0 ...
78 ~CAS ops: 1 0 1 0 1 0 1 0 ...
79
80 Address ops: a b c a b c ...
81 Data ops: s f s f ...
82
83 ~WE: ......W ...
84 PHI OUT: \_______________/--------------- ...
85 CPU (RAM): L D ...
86 RnW: R ...
87
88 PHI OUT: \_______/-------\_______/------- ...
89 CPU (ROM): L D L D ...
90 RnW: R R ...
91
92 ~RAS must be high for 100ns, ~CAS must be high for 50ns.
93 ~RAS must be low for 150ns, ~CAS must be low for 90ns.
94 Data is available 150ns after ~RAS goes low, 90ns after ~CAS goes low.
95
96 Here, "A" and "B" respectively indicate the row and first column addresses
97 being latched into the RAM (on a negative edge for ~RAS and ~CAS
98 respectively), and "C" indicates the second column address being latched into
99 the RAM. Presumably, the first and second half-bytes can be read at "F" and
100 "S" respectively, and the row and column addresses must be made available at
101 "a" and "b" (and "c") respectively at the latest. Data can be read at "f" and
102 "s" for the first and second half-bytes respectively.
103
104 For the CPU, "L" indicates the point at which an address is taken from the CPU
105 address bus, on a negative edge of PHI OUT, with "D" being the point at which
106 data may either be read or be asserted for writing, on a positive edge of PHI
107 OUT. Here, PHI OUT is driven at 1MHz. Given that ~WE needs to be driven low
108 for writing or high for reading, and thus propagates RnW from the CPU, this
109 would need to be done before data would be retrieved and, according to the
110 TM4164EC4 datasheet, even as late as the column address is presented and ~CAS
111 brought low.
112
113 The TM4164EC4-15 has a row address access time of 150ns (maximum) and a column
114 address access time of 90ns (maximum), which appears to mean that ~RAS must be
115 held low for at least 150ns and that ~CAS must be held low for at least 90ns
116 before data becomes available. 150ns is 2.4 cycles (at 16MHz) and 90ns is 1.44
117 cycles. Thus, "A" to "F" is 2.5 cycles, "B" to "F" is 1.5 cycles, "C" to "S"
118 is 1.5 cycles.
119
120 Note that the Service Manual refers to the negative edge of RAS and CAS, but
121 the datasheet for the similar TM4164EC4 product shows latching on the negative
122 edge of ~RAS and ~CAS. It is possible that the Service Manual also intended to
123 communicate the latter behaviour. In the TM4164EC4 datasheet, it appears that
124 "page mode" provides the appropriate behaviour for that particular product.
125
126 The CPU, when accessing the RAM alone, apparently does not make use of the
127 vacated "slot" that the ULA would otherwise use (when interleaving accesses in
128 MODE 4, 5 and 6). It only employs a full 2MHz access frequency to memory when
129 accessing ROM (and potentially sideways RAM). The principal limitation is the
130 amount of time needed between issuing an address and receiving an entire byte
131 from the RAM, which is approximately 7 cycles (at 16MHz): much longer than the
132 4 cycles that would be required for 2MHz operation.
133
134 See: Acorn Electron Advanced User Guide
135 See: Acorn Electron Service Manual
136 http://chrisacorns.computinghistory.org.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf
137 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
138 See: http://stardot.org.uk/forums/viewtopic.php?p=120438#p120438
139 See: One of the Most Popular 65,536-Bit (64K) Dynamic RAMs The TMS 4164
140 http://smithsonianchips.si.edu/augarten/p64.htm
141
142 A Note on 8-Bit Wide RAM Access
143 -------------------------------
144
145 It is worth considering the timing when 8 bits of data can be obtained at once
146 from the RAM chips:
147
148 Time (ns): 0-------------- 500------------- ...
149 2 MHz cycle: 0 1 ...
150 8 MHz cycle: 0 1 2 3 0 1 2 3 ...
151 /-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_ ...
152 ~RAS: /---\___________/---\___________ ...
153 ~CAS: /-------\_______/-------\_______ ...
154 Address events: A B A B ...
155 Data events: E E ...
156
157 ~RAS ops: 1 0 1 0 ...
158 ~CAS ops: 1 0 1 0 ...
159
160 Address ops: a b a b ...
161 Data ops: f s f ...
162
163 ~WE: ........W ...
164 PHI OUT: \_______/-------\_______/------- ...
165 CPU: L D L D ...
166 RnW: R R ...
167
168 Here, "E" indicates the availability of an entire byte.
169
170 Since only one fetch is required per 2MHz cycle, instead of two fetches for
171 the 4-bit wide RAM arrangement, it seems likely that longer 8MHz cycles could
172 be used to coordinate the necessary signalling.
173
174 Another conceivable simplification from using an 8-bit wide RAM access channel
175 with a single access within each 2MHz cycle is the possibility of allowing the
176 CPU to signal directly to the RAM instead of having the ULA perform the access
177 signalling on the CPU's behalf. Note that it is this more leisurely signalling
178 that would allow the CPU to conduct accesses at 2MHz: the "compressed"
179 signalling being beyond the capabilities of the CPU.
180
181 Note that 16MHz cycles would still be needed for the pixel clock in MODE 0,
182 which needs to output eight pixels per 2MHz cycle, producing 640 monochrome
183 pixels per 80-byte line.
184
185 An obvious consideration with regard to 8-bit wide access is whether the ULA
186 could still conduct the "compressed" signalling for its own RAM accesses:
187
188 Time (ns): 0-------------- 500------------- ...
189 2 MHz cycle: 0 1 ...
190 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
191 /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ ...
192 ~RAS: /---\___________/---\___________ ...
193 ~CAS: /-----\___/-\___/-----\___/-\___ ...
194 Address events: A B C A B C ...
195 Data events: 1 2 1 2 ...
196
197 ~RAS ops: 1 0 1 0 ...
198 ~CAS ops: 1 0 1 0 1 0 1 0 ...
199
200 Address ops: a b c a b c ...
201 Data ops: s f s f ...
202
203 ~WE: ......W ...
204 PHI OUT: \_______/-------\_______/------- ...
205 CPU: L D L D ...
206 RnW: R R ...
207
208 Here, "1" and "2" in the data events correspond to whole byte accesses,
209 effectively upgrading the half-byte "F" and "S" events in the existing ULA
210 arrangement.
211
212 Although the provision of access for the CPU would adhere to the relevant
213 timing constraints, providing only one byte per 2MHz cycle, the ULA could
214 obtain two bytes per cycle. This would then free up bandwidth for the CPU in
215 screen modes where the ULA would normally be dominant (MODE 0 to 3), albeit at
216 the cost of extra buffering. Such buffering could also be done for modes where
217 the bandwidth is shared (MODE 4 to 6), consolidating pairs of ULA accesses into
218 single cycles and freeing up an extra cycle for CPU accesses.
219
220 A further consideration is whether the CPU and ULA could access the memory on
221 interleaved 4MHz cycles, thus replicating the arrangement used by the CPU and
222 Video ULA on the BBC Micro. One potential obstacle is that the apparent 4MHz
223 access rate employed by the ULA does not involve the complete process for
224 accessing the RAM: upon setting up the address and issuing the ~RAS signal,
225 the ULA is able to make a pair of column accesses on the same "row" of memory,
226 effectively achieving an average access rate of 4MHz.
227
228 However, if arbitrary pairs of column accesses were to be attempted, as would
229 be required by CPU and ULA interleaving, the ~RAS signal would need to be
230 re-issued with different addresses being set up. This would expand the time to
231 access a memory location to beyond the period of a 4MHz cycle, making it
232 impossible to employ interleaved accesses at such a rate.
233
234 CPU Clock Notes
235 ---------------
236
237 "The 6502 receives an external square-wave clock input signal on pin 37, which
238 is usually labeled PHI0. [...] This clock input is processed within the 6502
239 to form two clock outputs: PHI1 and PHI2 (pins 3 and 39, respectively). PHI2
240 is essentially a copy of PHI0; more specifically, PHI2 is PHI0 after it's been
241 through two inverters and a push-pull amplifier. The same network of
242 transistors within the 6502 which generates PHI2 is also tied to PHI1, and
243 generates PHI1 as the inverse of PHI0. The reason why PHI1 and PHI2 are made
244 available to external devices is so that they know when they can access the
245 CPU. When PHI1 is high, this means that external devices can read from the
246 address bus or data bus; when PHI2 is high, this means that external devices
247 can write to the data bus."
248
249 See: http://lateblt.livejournal.com/88105.html
250
251 "The 6502 has a synchronous memory bus where the master clock is divided into
252 two phases (Phase 1 and Phase 2). The address is always generated during Phase
253 1 and all memory accesses take place during Phase 2."
254
255 See: http://www.jmargolin.com/vgens/vgens.htm
256
257 Thus, the inverse of PHI OUT provides the "other phase" of the clock. "During
258 Phase 1" means when PHI0 - really PHI2 - is high and "during Phase 2" means
259 when PHI1 is high.
260
261 Bandwidth Figures
262 -----------------
263
264 Using an observation of 128 2MHz cycles per scanline, 256 active lines and 312
265 total lines, with 80 cycles occurring in the active periods of display
266 scanlines, the following bandwidth calculations can be performed:
267
268 Total theoretical maximum:
269 128 cycles * 312 lines
270 = 39936 bytes
271
272 MODE 0, 1, 2:
273 ULA: 80 cycles * 256 lines
274 = 20480 bytes
275 CPU: 48 cycles / 2 * 256 lines
276 + 128 cycles / 2 * (312 - 256) lines
277 = 9728 bytes
278
279 MODE 3:
280 ULA: 80 cycles * 24 rows * 8 lines
281 = 15360 bytes
282 CPU: 48 cycles / 2 * 24 rows * 8 lines
283 + 128 cycles / 2 * (312 - (24 rows * 8 lines))
284 = 12288 bytes
285
286 MODE 4, 5:
287 ULA: 40 cycles * 256 lines
288 = 10240 bytes
289 CPU: (40 cycles + 48 cycles / 2) * 256 lines
290 + 128 cycles / 2 * (312 - 256) lines
291 = 19968 bytes
292
293 MODE 6:
294 ULA: 40 cycles * 24 rows * 8 lines
295 = 7680 bytes
296 CPU: (40 cycles + 48 cycles / 2) * 24 rows * 8 lines
297 + 128 cycles / 2 * (312 - (24 rows * 8 lines))
298 = 19968 bytes
299
300 Here, the division of 2 for CPU accesses is performed to indicate that the CPU
301 only uses every other access opportunity even in uncontended periods. See the
302 2MHz RAM Access enhancement below for bandwidth calculations that consider
303 this limitation removed.
304
305 A summary of the bandwidth figures is as follows (with extra timing details
306 described below):
307
308 Standard ULA % Total Slowdown BBC-10s BBC-34s
309 MODE 0, 1, 2 9728 bytes 24% 4.11 43s 105s
310 MODE 3 12288 bytes 31% 3.25 34s
311 MODE 4, 5 19968 bytes 50% 2 20s
312 MODE 6 19968 bytes 50% 2 20s 50s
313
314 The review of the Electron in Practical Computing (October 1983) provides a
315 concise overview of the RAM access limitations and gives timing comparisons
316 between modes and BBC Micro performance. In the above, "BBC-10s" is the
317 measured or stated time given for a program taking 10 seconds on the BBC
318 Micro, whereas "BBC-34s" is the apparently measured time given for the
319 "Persian" program taking 34 seconds to complete on the BBC Micro, with a
320 "quick" mode presumably switching to MODE 6 using the ULA directly in order to
321 reduce display bandwidth usage while the program draws to the screen.
322 Evidently, the measured slowdown is slightly lower than the theoretical
323 slowdown, most likely due to the running time not being entirely dominated by
324 RAM access performance characteristics.
325
326 Video Timing
327 ------------
328
329 According to 8.7 in the Service Manual, and the PAL Wikipedia page,
330 approximately 4.7µs is used for the sync pulse, 5.7µs for the "back porch"
331 (including the "colour burst"), and 1.65µs for the "front porch", totalling
332 12.05µs and thus leaving 51.95µs for the active video signal for each
333 scanline. As the Service Manual suggests in the oscilloscope traces, the
334 display information is transmitted more or less centred within the active
335 video period since the ULA will only be providing pixel data for 40µs in each
336 scanline.
337
338 Each 62.5ns cycle happens to correspond to 64µs divided by 1024, meaning that
339 each scanline can be divided into 1024 cycles, although only 640 at most are
340 actively used to provide pixel data. Pixel data production should only occur
341 within a certain period on each scanline, approximately 262 cycles after the
342 start of hsync:
343
344 active video period = 51.95µs
345 pixel data period = 40µs
346 total silent period = 51.95µs - 40µs = 11.95µs
347 silent periods (before and after) = 11.95µs / 2 = 5.975µs
348 hsync and back porch period = 4.7µs + 5.7µs = 10.4µs
349 time before pixel data period = 10.4µs + 5.975µs = 16.375µs
350 pixel data period start cycle = 16.375µs / 62.5ns = 262
351
352 By choosing a number divisible by 8, the RAM access mechanism can be
353 synchronised with the pixel production. Thus, 256 is a more appropriate start
354 cycle, where the HS (horizontal sync) signal corresponding to the 4µs sync
355 pulse (or "normal sync" pulse as described by the "PAL TV timing and voltages"
356 document) occurs at cycle 0.
357
358 To summarise:
359
360 HS signal starts at cycle 0 on each horizontal scanline
361 HS signal ends approximately 4µs later at cycle 64
362 Pixel data starts approximately 12µs later at cycle 256
363
364 "Re: Electron Memory Contention" provides measurements that appear consistent
365 with these calculations.
366
367 The "vertical blanking period", meaning the period before picture information
368 in each field is 25 lines out of 312 (or 313) and thus lasts for 1.6ms. Of
369 this, 2.5 lines occur before the vsync (field sync) which also lasts for 2.5
370 lines. Thus, the first visible scanline on the first field of a frame occurs
371 half way through the 23rd scanline period measured from the start of vsync
372 (indicated by "V" in the diagrams below):
373
374 10 20 23
375 Line in frame: 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8
376 Line from 1: 0 22 3
377 Line on screen: .:::::VVVVV::::: 12233445566
378 |_________________________________________________|
379 25 line vertical blanking period
380
381 In the second field of a frame, the first visible scanline coincides with the
382 24th scanline period measured from the start of line 313 in the frame:
383
384 310 336
385 Line in frame: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
386 Line from 313: 0 23 4
387 Line on screen: 88:::::VVVVV:::: 11223344
388 288 | |
389 |_________________________________________________|
390 25 line vertical blanking period
391
392 In order to consider only full lines, we might consider the start of each
393 frame to occur 23 lines after the start of vsync.
394
395 Again, it is likely that pixel data production should only occur on scanlines
396 within a certain period on each frame. The "625/50" document indicates that
397 only a certain region is "safe" to use, suggesting a vertically centred region
398 with approximately 15 blank lines above and below the picture. However, the
399 "PAL TV timing and voltages" document suggests 28 blank lines above and below
400 the picture. This would centre the 256 lines within the 312 lines of each
401 field and thus provide a start of picture approximately 5.5 or 5 lines after
402 the end of the blanking period or 28 or 27.5 lines after the start of vsync.
403
404 To summarise:
405
406 CSYNC signal starts at cycle 0
407 CSYNC signal ends approximately 160µs (2.5 lines) later at cycle 2560
408 Start of line occurs approximately 1632µs (5.5 lines) later at cycle 28672
409
410 See: http://en.wikipedia.org/wiki/PAL
411 See: http://en.wikipedia.org/wiki/Analog_television#Structure_of_a_video_signal
412 See: The 625/50 PAL Video Signal and TV Compatible Graphics Modes
413 http://lipas.uwasa.fi/~f76998/video/modes/
414 See: PAL TV timing and voltages
415 http://www.retroleum.co.uk/electronics-articles/pal-tv-timing-and-voltages/
416 See: Line Standards
417 http://www.pembers.freeserve.co.uk/World-TV-Standards/Line-Standards.html
418 See: Horizontal Blanking Interval of 405-, 525-, 625- and 819-Line Standards
419 http://www.pembers.freeserve.co.uk/World-TV-Standards/HBI.pdf
420 See: Re: Electron Memory Contention
421 http://www.stardot.org.uk/forums/viewtopic.php?p=134109#p134109
422
423 RAM Integrated Circuits
424 -----------------------
425
426 Unicorn Electronics appears to offer 4164 RAM chips (as well as 6502 series
427 CPUs such as the 6502, 6502A, 6502B and 65C02). These 4164 devices are
428 available in 100ns (4164-100), 120ns (4164-120) and 150ns (4164-150) variants,
429 have 16 pins and address 65536 bits through a 1-bit wide channel. Similarly,
430 ByteDelight.com sell 4164 devices primarily for the ZX Spectrum.
431
432 The documentation for the Electron mentions 4164-15 RAM chips for IC4-7, and
433 the Samsung-produced KM41464 series is apparently equivalent to the Texas
434 Instruments 4164 chips presumably used in the Electron.
435
436 The TM4164EC4 series combines 4 64K x 1b units into a single package and
437 appears similar to the TM4164EA4 featured on the Electron's circuit diagram
438 (in the Advanced User Guide but not the Service Manual), and it also has 22
439 pins providing 3 additional inputs and 3 additional outputs over the 16 pins
440 of the individual 4164-15 modules, presumably allowing concurrent access to
441 the packaged memory units.
442
443 As far as currently available replacements are concerned, the NTE4164 is a
444 potential candidate: according to the Vetco Electronics entry, it is
445 supposedly a replacement for the TMS4164-15 amongst many other parts. Similar
446 parts include the NTE2164 and the NTE6664, both of which appear to have
447 largely the same performance and connection characteristics. Meanwhile, the
448 NTE21256 appears to be a 16-pin replacement with four times the capacity that
449 maintains the single data input and output pins. Using the NTE21256 as a
450 replacement for all ICs combined would be difficult because of the single bit
451 output.
452
453 Another device equivalent to the 4164-15 appears to be available under the
454 code 41662 from Jameco Electronics as the Siemens HYB 4164-2. The Jameco Web
455 site lists data sheets for other devices on the same page, but these are
456 different and actually appear to be provided under the 41574 product code (but
457 are listed under 41464-10) and appear to be replacements for the TM4164EC4:
458 the Samsung KM41464A-15 and NEC µPD41464 employ 18 pins, eliminating 4 pins by
459 employing 4 pins for both input and output.
460
461 Pins I/O pins Row access Column access
462 ---- -------- ---------- -------------
463 TM4164EC4 22 4 + 4 150ns (15) 90ns (15)
464 KM41464AP 18 4 150ns (15) 75ns (15)
465 NTE21256 16 1 + 1 150ns 75ns
466 HYB 4164-2 16 1 + 1 150ns 100ns
467 µPD41464 18 4 120ns (12) 60ns (12)
468
469 See: TM4164EC4 65,536 by 4-Bit Dynamic RAM Module
470 http://www.datasheetarchive.com/dl/Datasheets-112/DSAP0051030.pdf
471 See: Dynamic RAMS
472 http://www.unicornelectronics.com/IC/DYNAMIC.html
473 See: New old stock 8x 4164 chips
474 http://www.bytedelight.com/?product=8x-4164-chips-new-old-stock
475 See: KM4164B 64K x 1 Bit Dynamic RAM with Page Mode
476 http://images.ihscontent.net/vipimages/VipMasterIC/IC/SAMS/SAMSD020/SAMSD020-45.pdf
477 See: NTE2164 Integrated Circuit 65,536 X 1 Bit Dynamic Random Access Memory
478 http://www.vetco.net/catalog/product_info.php?products_id=2806
479 See: NTE4164 - IC-NMOS 64K DRAM 150NS
480 http://www.vetco.net/catalog/product_info.php?products_id=3680
481 See: NTE21256 - IC-256K DRAM 150NS
482 http://www.vetco.net/catalog/product_info.php?products_id=2799
483 See: NTE21256 262,144-Bit Dynamic Random Access Memory (DRAM)
484 http://www.nteinc.com/specs/21000to21999/pdf/nte21256.pdf
485 See: NTE6664 - IC-MOS 64K DRAM 150NS
486 http://www.vetco.net/catalog/product_info.php?products_id=5213
487 See: NTE6664 Integrated Circuit 64K-Bit Dynamic RAM
488 http://www.nteinc.com/specs/6600to6699/pdf/nte6664.pdf
489 See: 4164-150: MAJOR BRANDS
490 http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41662_-1
491 See: HYB 4164-1, HYB 4164-2, HYB 4164-3 65,536-Bit Dynamic Random Access Memory (RAM)
492 http://www.jameco.com/Jameco/Products/ProdDS/41662SIEMENS.pdf
493 See: KM41464A NMOS DRAM 64K x 4 Bit Dynamic RAM with Page Mode
494 http://www.jameco.com/Jameco/Products/ProdDS/41662SAM.pdf
495 See: NEC µ41464 65,536 x 4-Bit Dynamic NMOS RAM
496 http://www.jameco.com/Jameco/Products/ProdDS/41662NEC.pdf
497 See: 41464-10: MAJOR BRANDS
498 http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41574_-1
499
500 Interrupts
501 ----------
502
503 The ULA generates IRQs (maskable interrupts) according to certain conditions
504 and these conditions are controlled by location &FE00:
505
506 * Vertical sync (bottom of displayed screen)
507 * 50MHz real time clock
508 * Transmit data empty
509 * Receive data full
510 * High tone detect
511
512 The ULA is also used to clear interrupt conditions through location &FE05. Of
513 particular significance is bit 7, which must be set if an NMI (non-maskable
514 interrupt) has occurred and has thus suspended ULA access to memory, restoring
515 the normal function of the ULA.
516
517 ROM Paging
518 ----------
519
520 Accessing different ROMs involves bits 0 to 3 of &FE05. Some special ROM
521 mappings exist:
522
523 8 keyboard
524 9 keyboard (duplicate)
525 10 BASIC ROM
526 11 BASIC ROM (duplicate)
527
528 Paging in a ROM involves the following procedure:
529
530 1. Assert ROM page enable (bit 3) together with a ROM number n in bits 0 to
531 2, corresponding to ROM number 8+n, such that one of ROMs 12 to 15 is
532 selected.
533 2. Where a ROM numbered from 0 to 7 is to be selected, set bit 3 to zero
534 whilst writing the desired ROM number n in bits 0 to 2.
535
536 See: http://stardot.org.uk/forums/viewtopic.php?p=136686#p136686
537
538 Keyboard Access
539 ---------------
540
541 The keyboard pages appear to be accessed at 1MHz just like the RAM.
542
543 See: https://stardot.org.uk/forums/viewtopic.php?p=254155#p254155
544
545 Shadow/Expanded Memory
546 ----------------------
547
548 The Electron exposes all sixteen address lines and all eight data lines
549 through the expansion bus. Using such lines, it is possible to provide
550 additional memory - typically sideways ROM and RAM - on expansion cards and
551 through cartridges, although the official cartridge specification provides
552 fewer address lines and only seeks to provide access to memory in 16K units.
553
554 Various modifications and upgrades were developed to offer "turbo"
555 capabilities to the Electron, permitting the CPU to access a separate 8K of
556 RAM at 2MHz, presumably preventing access to the low 8K of RAM accessible via
557 the ULA through additional logic. However, an enhanced ULA might support
558 independent CPU access to memory over the expansion bus by allowing itself to
559 be discharged from providing access to memory, potentially for a range of
560 addresses, and for the CPU to communicate with external memory uninterrupted.
561
562 Sideways RAM/ROM and Upper Memory Access
563 ----------------------------------------
564
565 Although the ULA controls the CPU clock, effectively slowing or stopping the
566 CPU when the ULA needs to access screen memory, it is apparently able to allow
567 the CPU to access addresses of &8000 and above - the upper region of memory -
568 at 2MHz independently of any access to RAM that the ULA might be performing,
569 only blocking the CPU if it attempts to access addresses of &7FFF and below
570 during any ULA memory access - the lower region of memory - by stopping or
571 stalling its clock.
572
573 Thus, the ULA remains aware of the level of the A15 line, only inhibiting the
574 CPU clock if the line goes low, when the CPU is attempting to access the lower
575 region of memory.
576
577 Hardware Scrolling (and Enhancement)
578 ------------------------------------
579
580 On the standard ULA, &FE02 and &FE03 map to a 9 significant bits address with
581 the least significant 5 bits being zero, thus limiting the scrolling
582 resolution to 64 bytes. An enhanced ULA could support a resolution of 2 bytes
583 using the same layout of these addresses.
584
585 |--&FE02--------------| |--&FE03--------------|
586 XX XX 14 13 12 11 10 09 08 07 06 XX XX XX XX XX
587
588 XX 14 13 12 11 10 09 08 07 06 05 04 03 02 01 XX
589
590 Arguably, a resolution of 8 bytes is more useful, since the mapping of screen
591 memory to pixel locations is character oriented. A change in 8 bytes would
592 permit a horizontal scrolling resolution of 2 pixels in MODE 2, 4 pixels in
593 MODE 1 and 5, and 8 pixels in MODE 0, 3 and 6. This resolution is actually
594 observed on the BBC Micro (see 18.11.2 in the BBC Microcomputer Advanced User
595 Guide).
596
597 One argument for a 2 byte resolution is smooth vertical scrolling. A pitfall
598 of changing the screen address by 2 bytes is the change in the number of lines
599 from the initial and final character rows that need reading by the ULA, which
600 would need to maintain this state information (although this is a relatively
601 trivial change). Another pitfall is the complication that might be introduced
602 to software writing bitmaps of character height to the screen.
603
604 See: http://pastraiser.com/computers/acornelectron/acornelectron.html
605
606 Enhancement: Mode Layouts
607 -------------------------
608
609 Merely changing the screen memory mappings in order to have Archimedes-style
610 row-oriented screen addresses (instead of character-oriented addresses) could
611 be done for the existing modes, but this might not be sufficiently beneficial,
612 especially since accessing regions of the screen would involve incrementing
613 pointers by amounts that are inconvenient on an 8-bit CPU.
614
615 However, instead of using a Archimedes-style mapping, column-oriented screen
616 addresses could be more feasibly employed: incrementing the address would
617 reference the vertical screen location below the currently-referenced location
618 (just as occurs within characters using the existing ULA); instead of
619 returning to the top of the character row and referencing the next horizontal
620 location after eight bytes, the address would reference the next character row
621 and continue to reference locations downwards over the height of the screen
622 until reaching the bottom; at the bottom, the next location would be the next
623 horizontal location at the top of the screen.
624
625 In other words, the memory layout for the screen would resemble the following
626 (for MODE 2):
627
628 &3000 &3100 ... &7F00
629 &3001 &3101
630 ... ...
631 &3007
632 &3008
633 ...
634 ... ...
635 &30FF ... &7FFF
636
637 Since there are 256 pixel rows, each column of locations would be addressable
638 using the low byte of the address. Meanwhile, the high byte would be
639 incremented to address different columns. Thus, addressing screen locations
640 would become a lot more convenient and potentially much more efficient for
641 certain kinds of graphical output.
642
643 One potential complication with this simplified addressing scheme arises with
644 hardware scrolling. Vertical hardware scrolling by one pixel row (not supported
645 with the existing ULA) would be achieved by incrementing or decrementing the
646 screen start address; by one character row, it would involve adding or
647 subtracting 8. However, the ULA only supports multiples of 64 when changing the
648 screen start address. Thus, if such a scheme were to be adopted, three
649 additional bits would need to be supported in the screen start register (see
650 "Hardware Scrolling (and Enhancement)" for more details). However, horizontal
651 scrolling would be much improved even under the severe constraints of the
652 existing ULA: only adjustments of 256 to the screen start address would be
653 required to produce single-location scrolling of as few as two pixels in MODE 2
654 (four pixels in MODEs 1 and 5, eight pixels otherwise).
655
656 More disruptive is the effect of this alternative layout on software.
657 Presumably, compatibility with the BBC Micro was the primary goal of the
658 Electron's hardware design. With the character-oriented screen layout in
659 place, system software (and application software accessing the screen
660 directly) would be relying on this layout to run on the Electron with little
661 or no modification. Although it might have been possible to change the system
662 software to use this column-oriented layout instead, this would have incurred
663 a development cost and caused additional work porting things like games to the
664 Electron. Moreover, a separate branch of the software from that supporting the
665 BBC Micro and closer derivatives would then have needed maintaining.
666
667 The decision to use the character-oriented layout in the BBC Micro may have
668 been related to the choice of circuitry and to facilitate a convenient
669 hardware implementation, and by the time the Electron was planned, it was too
670 late to do anything about this somewhat unfortunate choice.
671
672 Pixel Layouts
673 -------------
674
675 The pixel layouts are as follows:
676
677 Modes Depth (bpp) Pixels (from bits)
678 ----- ----------- ------------------
679 0, 3, 4, 6 1 7 6 5 4 3 2 1 0
680 1, 5 2 73 62 51 40
681 2 4 7531 6420
682
683 Since the ULA reads a half-byte at a time, one might expect it to attempt to
684 produce pixels for every half-byte, as opposed to handling entire bytes.
685 However, the pixel layout is not conducive to producing pixels as soon as a
686 half-byte has been read for a given full-byte location: in 1bpp modes the
687 first four pixels can indeed be produced, but in 2bpp and 4bpp modes the pixel
688 data is spread across the entire byte in different ways.
689
690 An alternative arrangement might be as follows:
691
692 Modes Depth (bpp) Pixels (from bits)
693 ----- ----------- ------------------
694 0, 3, 4, 6 1 7 6 5 4 3 2 1 0
695 1, 5 2 76 54 32 10
696 2 4 7654 3210
697
698 Just as the mode layouts were presumably decided by compatibility with the BBC
699 Micro, the pixel layouts will have been maintained for similar reasons.
700 Unfortunately, this layout prevents any optimisation of the ULA for handling
701 half-byte pixel data generally.
702
703 Enhancement: The Missing MODE 4
704 -------------------------------
705
706 The Electron inherits its screen mode selection from the BBC Micro, where MODE
707 3 is a text version of MODE 0, and where MODE 6 is a text version of MODE 4.
708 Neither MODE 3 nor MODE 6 is a genuine character-based text mode like MODE 7,
709 however, and they are merely implemented by skipping two scanlines in every
710 ten after the eight required to produce a character line. Thus, such modes
711 provide a 24-row display.
712
713 In principle, nothing prevents this "text mode" effect being applied to other
714 modes. The 20-column modes are not well-suited to displaying text, which
715 leaves MODE 1 which, unlike MODEs 3 and 6, can display 4 colours rather than
716 2. Although the need for a non-monochrome 40-column text mode is addressed by
717 MODE 7 on the BBC Micro, the Electron lacks such a mode.
718
719 If the 4-colour, 24-row variant of MODE 1 were to be provided, logically it
720 would occupy MODE 4 instead of the current MODE 4:
721
722 Screen mode Size (kilobytes) Colours Rows Resolution
723 ----------- ---------------- ------- ---- ----------
724 0 20 2 32 640x256
725 1 20 4 32 320x256
726 2 20 16 32 160x256
727 3 16 2 24 640x256
728 4 (new) 16 4 24 320x256
729 4 (old) 10 2 32 320x256
730 5 10 4 32 160x256
731 6 8 2 24 320x256
732
733 Thus, for increasing mode numbers, the size of each mode would be the same or
734 less than the preceding mode.
735
736 Enhancement: Display Mode Property Control
737 ------------------------------------------
738
739 It is rather curious that the ULA supports the mode numbers directly in bits 3
740 to 5 of &FE07 since these would presumably need to be decoded in order to set
741 the fundamental properties of the display mode. These properties are as
742 follows:
743
744 * Screen data retrieval rate: number of fetches per pair of 2MHz cycles
745 * Pixel colour depth
746 * Text mode vertical spacing
747
748 From these, the following properties emerge:
749
750 Property Influences
751 -------- ----------
752 Character row size (bytes) Retrieval rate
753
754 Number of character rows Text mode setting
755
756 Display size (bytes) Retrieval rate (character row size)
757 Text mode setting (number of rows)
758
759 Pixel frequency Retrieval rate
760 Horizontal resolution (pixels) Colour depth
761
762 One can imagine a register bitfield arrangement as follows:
763
764 Field Values Formula
765 ----- ------ -------
766 Pixel depth 00: 1 bit per pixel log2(depth)
767 01: 2 bits per pixel
768 10: 4 bits per pixel
769
770 Retrieval rate 0: twice 2 - fetches per cycle pair
771 1: once
772
773 Text mode enable 0: disable/off text mode enabled
774 1: enable/on
775
776 This arrangement would require four bits. However, one bit in &FE07 is
777 seemingly inactive and might possibly be reallocated.
778
779 The resulting combination of properties would permit all of the existing modes
780 plus some additional ones, including the missing MODE 4 mentioned above. With
781 the bitfields above ordered from the most significant bits to the least
782 significant bits providing the low-level "mode" values, the following table
783 can be produced:
784
785 Screen mode Depth Rate Text Size (K) Colours Rows Resolution
786 ----------- ----- ---- ---- -------- ------- ---- ----------
787 0 (0000) 1 twice off 20 2 32 640x256 (MODE 0)
788 1 (0001) 1 twice on 16 2 24 640x256 (MODE 3)
789 2 (0010) 1 once off 10 2 32 320x256 (MODE 4)
790 3 (0011) 1 once on 8 2 24 320x256 (MODE 6)
791 4 (0100) 2 twice off 20 4 32 320x256 (MODE 1)
792 5 (0101) 2 twice on 16 4 24 320x256
793 6 (0110) 2 once off 10 4 32 160x256 (MODE 5)
794 7 (0111) 2 once on 8 4 24 160x256
795 8 (1000) 4 twice off 20 16 32 160x256 (MODE 2)
796 9 (1001) 4 twice on 16 16 24 160x256
797 10 (1010) 4 once off 10 16 32 80x256
798 11 (1011) 4 once on 8 16 24 80x256
799
800 The existing modes would be covered in a way that is incompatible with the
801 existing numbering, thus requiring a table in software, but additional text
802 modes would be provided for MODE 1, MODE 5 and MODE 2. An additional two lower
803 resolution modes would also be conceivable within this scheme, requiring the
804 stretching of 16MHz pixels by a factor of eight to yield 80 pixels per
805 scanline. The utility of such modes is questionable and such modes might not
806 be supported.
807
808 Enhancement: 2MHz RAM Access
809 ----------------------------
810
811 Given that the CPU and ULA both access RAM at 2MHz, but given that the CPU
812 when not competing with the ULA only accesses RAM every other 2MHz cycle (as
813 if the ULA still needed to access the RAM), one useful enhancement would be a
814 mechanism to let the CPU take over the ULA cycles outside the ULA's period of
815 activity comparable to the way the ULA takes over the CPU cycles in MODE 0 to
816 3.
817
818 Thus, the RAM access cycles would resemble the following in MODE 0 to 3:
819
820 Upon a transition from display cycles: UUUUCCCC (instead of UUUUC_C_)
821 On a non-display line: CCCCCCCC (instead of C_C_C_C_)
822
823 In MODE 4 to 6:
824
825 Upon a transition from display cycles: CUCUCCCC (instead of CUCUC_C_)
826 On a non-display line: CCCCCCCC (instead of C_C_C_C_)
827
828 This would improve CPU bandwidth as follows:
829
830 Standard ULA Enhanced ULA % Total Bandwidth Speedup
831 MODE 0, 1, 2 9728 bytes 19456 bytes 24% -> 49% 2
832 MODE 3 12288 bytes 24576 bytes 31% -> 62% 2
833 MODE 4, 5 19968 bytes 29696 bytes 50% -> 74% 1.5
834 MODE 6 19968 bytes 32256 bytes 50% -> 81% 1.6
835
836 (Here, the uncontended total 2MHz bandwidth for a display period would be
837 39936 bytes, being 128 cycles per line over 312 lines.)
838
839 With such an enhancement, MODE 0 to 3 experience a doubling of CPU bandwidth
840 because all access opportunities to RAM are doubled. Meanwhile, in the other
841 modes, some CPU accesses occur alongside ULA accesses and thus cannot be
842 doubled, but the CPU bandwidth increase is still significant.
843
844 Unfortunately, the mechanism for accessing the RAM is too slow to provide data
845 within the time constraints of 2MHz operation. There is no time remaining in a
846 2MHz cycle for the CPU to receive and process any retrieved data once the
847 necessary signalling has been performed.
848
849 The only way for the CPU to be able to access the RAM quickly enough would be
850 to do away with the double 4-bit access mechanism and to have a single 8-bit
851 channel to the memory. This would require twice as many 1-bit RAM chips or a
852 different kind of RAM chip, but it would also potentially simplify the ULA.
853
854 The section on 8-bit wide RAM access discusses the possibilities around
855 changing the memory architecture, also describing the possibility of ULA
856 accesses achieving two bytes per 2MHz cycle due to the doubling of the memory
857 channel, leaving every other access free for the CPU during the display period
858 in MODE 0 to 3...
859
860 Standard display period: UUUUUUUU
861 Modified display period: UCUCUCUC
862
863 ...and consolidating accesses in MODE 4 to 6:
864
865 Standard display period: UCUCUCUC
866 Modified display period: UCCCUCCC
867
868 Together with the enhancements for non-display periods, such an "Enhanced+ ULA"
869 would perform as follows:
870
871 Standard ULA Enhanced+ ULA % Total Bandwidth Speedup
872 MODE 0, 1, 2 9728 bytes 29696 bytes 24% -> 74% 3.1
873 MODE 3 12288 bytes 32256 bytes 31% -> 81% 2.6
874 MODE 4, 5 19968 bytes 34816 bytes 50% -> 87% 1.7
875 MODE 6 19968 bytes 36096 bytes 50% -> 90% 1.8
876
877 Of course, the principal enhancement would be the wider memory channel, with
878 more buffering in the ULA being its contribution to this arrangement.
879
880 Enhancement: Region Blanking
881 ----------------------------
882
883 The problem of permitting character-oriented blitting in programs whilst
884 scrolling the screen by sub-character amounts could be mitigated by permitting
885 a region of the display to be blank, such as the final lines of the display.
886 Consider the following vertical scrolling by 2 bytes that would cause an
887 initial character row of 6 lines and a final character row of 2 lines:
888
889 6 lines - initial, partial character row
890 248 lines - 31 complete rows
891 2 lines - final, partial character row
892
893 If a routine were in use that wrote 8 line bitmaps to the partial character
894 row now split in two, it would be advisable to hide one of the regions in
895 order to prevent content appearing in the wrong place on screen (such as
896 content meant to appear at the top "leaking" onto the bottom). Blanking 6
897 lines would be sufficient, as can be seen from the following cases.
898
899 Scrolling up by 2 lines:
900
901 6 lines - initial, partial character row
902 240 lines - 30 complete rows
903 4 lines - part of 1 complete row
904 -----------------------------------------------------------------
905 4 lines - part of 1 complete row (hidden to maintain 250 lines)
906 2 lines - final, partial character row (hidden)
907
908 Scrolling down by 2 lines:
909
910 2 lines - initial, partial character row
911 248 lines - 31 complete rows
912 ----------------------------------------------------------
913 6 lines - final, partial character row (hidden)
914
915 Thus, in this case, region blanking would impose a 250 line display with the
916 bottom 6 lines blank.
917
918 See the description of the display suspend enhancement for a more efficient
919 way of blanking lines than merely blanking the palette whilst allowing the CPU
920 to perform useful work during the blanking period.
921
922 To control the blanking or suspending of lines at the top and bottom of the
923 display, a memory location could be dedicated to the task: the upper 4 bits
924 could define a blanking region of up to 16 lines at the top of the screen,
925 whereas the lower 4 bits could define such a region at the bottom of the
926 screen. If more lines were required, two locations could be employed, allowing
927 the top and bottom regions to occupy the entire screen.
928
929 Enhancement: Screen Height Adjustment
930 -------------------------------------
931
932 The height of the screen could be configurable in order to reduce screen
933 memory consumption. This is not quite done in MODE 3 and 6 since the start of
934 the screen appears to be rounded down to the nearest page, but by reducing the
935 height by amounts more than a page, savings would be possible. For example:
936
937 Screen width Depth Height Bytes per line Saving in bytes Start address
938 ------------ ----- ------ -------------- --------------- -------------
939 640 1 252 80 320 &3140 -> &3100
940 640 1 248 80 640 &3280 -> &3200
941 320 1 240 40 640 &5A80 -> &5A00
942 320 2 240 80 1280 &3500
943
944 Screen Mode Selection
945 ---------------------
946
947 Bits 3, 4 and 5 of address &FE*7 control the selected screen mode. For a wider
948 range of modes, the other bits of &FE*7 (related to sound, cassette
949 input/output and the Caps Lock LED) would need to be reassigned and bit 0
950 potentially being made available for use.
951
952 Enhancement: Palette Definition
953 -------------------------------
954
955 Since all memory accesses go via the ULA, an enhanced ULA could employ more
956 specific addresses than &FE*X to perform enhanced functions. For example, the
957 palette control is done using &FE*8-F and merely involves selecting predefined
958 colours, whereas an enhanced ULA could support the redefinition of all 16
959 colours using specific ranges such as &FE18-F (colours 0 to 7) and &FE28-F
960 (colours 8 to 15), where a single byte might provide 8 bits per pixel colour
961 specifications similar to those used on the Archimedes.
962
963 The principal limitation here is actually the hardware: the Electron has only
964 a single output line for each of the red, green and blue channels, and if
965 those outputs are strictly digital and can only be set to a "high" and "low"
966 value, then only the existing eight colours are possible. If a modern ULA were
967 able to output analogue values (or values at well-defined points between the
968 high and low values, such as the half-on value supported by the Amstrad CPC
969 series), it would still need to be assessed whether the circuitry could
970 successfully handle and propagate such values. Various sources indicate that
971 only "TTL levels" are supported by the RGB output circuit, and since there are
972 74LS08 AND logic gates involved in the RGB component outputs from the ULA, it
973 is likely that the ULA is expected to provide only "high" or "low" values.
974
975 Short of adding extra outputs from the ULA (either additional red, green and
976 blue outputs or a combined intensity output), another approach might involve
977 some kind of modulation where an output value might be encoded in multiple
978 pulses at a higher frequency than the pixel frequency. However, this would
979 demand additional circuitry outside the ULA, and component RGB monitors would
980 probably not be able to take advantage of this feature; only UHF and composite
981 video devices (the latter with the composite video colour support enabled on
982 the Electron's circuit board) would potentially benefit.
983
984 Flashing Colours
985 ----------------
986
987 According to the Advanced User Guide, "The cursor and flashing colours are
988 entirely generated in software: This means that all of the logical to physical
989 colour map must be changed to cause colours to flash." This appears to suggest
990 that the palette registers must be updated upon the flash counter - read and
991 written by OSBYTE &C1 (193) - reaching zero and that some way of changing the
992 colour pairs to be any combination of colours might be possible, instead of
993 having colour complements as pairs.
994
995 It is conceivable that the interrupt code responsible does the simple thing
996 and merely inverts the current values for any logical colours (LC) for which
997 the associated physical colour (as supplied as the second parameter to the VDU
998 19 call) has the top bit of its four bit value set. These top bits are not
999 recorded in the palette registers but are presumably recorded separately and
1000 used to build bitmaps as follows:
1001
1002 LC 2 colour 4 colour 16 colour 4-bit value for inversion
1003 -- -------- -------- --------- -------------------------
1004 0 00010001 00010001 00010001 1, 1, 1
1005 1 01000100 00100010 00010001 4, 2, 1
1006 2 01000100 00100010 4, 2
1007 3 10001000 00100010 8, 2
1008 4 00010001 1
1009 5 00010001 1
1010 6 00100010 2
1011 7 00100010 2
1012 8 01000100 4
1013 9 01000100 4
1014 10 10001000 8
1015 11 10001000 8
1016 12 01000100 4
1017 13 01000100 4
1018 14 10001000 8
1019 15 10001000 8
1020
1021 Inversion value calculation:
1022
1023 2 colour formula: 1 << (colour * 2)
1024 4 colour formula: 1 << colour
1025 16 colour formula: 1 << ((colour & 2) + ((colour & 8) * 2))
1026
1027 For example, where logical colour 0 has been mapped to a physical colour in
1028 the range 8 to 15, a bitmap of 00010001 would be chosen as its contribution to
1029 the inversion operation. (The lower three bits of the physical colour would be
1030 used to set the underlying colour information affected by the inversion
1031 operation.)
1032
1033 An operation in the interrupt code would then combine the bitmaps for all
1034 logical colours in 2 and 4 colour modes, with the 16 colour bitmaps being
1035 combined for groups of logical colours as follows:
1036
1037 Logical colours
1038 ---------------
1039 0, 2, 8, 10
1040 4, 6, 12, 14
1041 5, 7, 13, 15
1042 1, 3, 9, 11
1043
1044 These combined bitmaps would be EORed with the existing palette register
1045 values in order to perform the value inversion necessary to produce the
1046 flashing effect.
1047
1048 Thus, in the VDU 19 operation, the appropriate inversion value would be
1049 calculated for the logical colour, and this value would then be combined with
1050 other inversion values in a dedicated memory location corresponding to the
1051 colour's group as indicated above. Meanwhile, the palette channel values would
1052 be derived from the lower three bits of the specified physical colour and
1053 combined with other palette data in dedicated memory locations corresponding
1054 to the palette registers.
1055
1056 Interestingly, although flashing colours on the BBC Micro are controlled by
1057 toggling bit 0 of the &FE20 control register location for the Video ULA, the
1058 actual colour inversion is done in hardware.
1059
1060 Enhancement: Palette Definition Lists
1061 -------------------------------------
1062
1063 It can be useful to redefine the palette in order to change the colours
1064 available for a particular region of the screen, particularly in modes where
1065 the choice of colours is constrained, and if an increased colour depth were
1066 available, palette redefinition would be useful to give the illusion of more
1067 than 16 colours in MODE 2. Traditionally, palette redefinition has been done
1068 by using interrupt-driven timers, but a more efficient approach would involve
1069 presenting lists of palette definitions to the ULA so that it can change the
1070 palette at a particular display line.
1071
1072 One might define a palette redefinition list in a region of memory and then
1073 communicate its contents to the ULA by writing the address and length of the
1074 list, along with the display line at which the palette is to be changed, to
1075 ULA registers such that the ULA buffers the list and performs the redefinition
1076 at the appropriate time. Throughput/bandwidth considerations might impose
1077 restrictions on the practical length of such a list, however.
1078
1079 A simple form of palette definition might be useful in text modes. Within the
1080 blank region between lines, the foreground palette could be changed to apply
1081 to the next line. Palette values could be read from a table in RAM, perhaps
1082 preceding the screen data, with 24 2-byte entries providing palette
1083 redefinition support in 2- and 4-colour modes.
1084
1085 Enhancement: Display Synchronisation Interrupts
1086 -----------------------------------------------
1087
1088 When completing each scanline of the display, the ULA could trigger an
1089 interrupt. Since this might impact system performance substantially, the
1090 feature would probably need to be configurable, and it might be sufficient to
1091 have an interrupt only after a certain number of display lines instead.
1092 Permitting the CPU to take action after eight lines would allow palette
1093 switching and other effects to occur on a character row basis.
1094
1095 The ULA provides an interrupt at the end of the display period, presumably so
1096 that software can schedule updates to the screen, avoid flickering or tearing,
1097 and so on. However, some applications might benefit from an interrupt at, or
1098 just before, the start of the display period so that palette modifications or
1099 similar effects could be scheduled.
1100
1101 Enhancement: Palette-Free Modes
1102 -------------------------------
1103
1104 Palette-free modes might be defined where bit values directly correspond to
1105 the red, green and blue channels, although this would mostly make sense only
1106 for modes with depths greater than the standard 4 bits per pixel, and such
1107 modes would require more memory than MODE 2 if they were to have an acceptable
1108 resolution.
1109
1110 Enhancement: Display Suspend
1111 ----------------------------
1112
1113 Especially when writing to the screen memory, it could be beneficial to be
1114 able to suspend the ULA's access to the memory, instead producing blank values
1115 for all screen pixels until a program is ready to reveal the screen. This is
1116 different from palette blanking since with a blank palette, the ULA is still
1117 reading screen memory and translating its contents into pixel values that end
1118 up being blank.
1119
1120 This function is reminiscent of a capability of the ZX81, albeit necessary on
1121 that hardware to reduce the load on the system CPU which was responsible for
1122 producing the video output. By allowing display suspend on the Electron, the
1123 performance benefit would be derived from giving the CPU full access to the
1124 memory bandwidth.
1125
1126 Note that since the CPU is only able to access RAM at 1MHz, there is no
1127 possibility to improve performance beyond that achieved in MODE 4, 5 or 6
1128 normally. However, if faster RAM access were to be made possible (see the
1129 discussion of 8-bit wide RAM access), the CPU could benefit from freeing up
1130 the ULA's access slots entirely.
1131
1132 The region blanking feature mentioned above could be implemented using this
1133 enhancement instead of employing palette blanking for the affected lines of
1134 the display.
1135
1136 Enhancement: Memory Filling
1137 ---------------------------
1138
1139 A capability that could be given to an enhanced ULA is that of permitting the
1140 ULA to write to screen memory as well being able to read from it. Although
1141 such a capability would probably not be useful in conjunction with the
1142 existing read operations when producing a screen display, and insufficient
1143 bandwidth would exist to do so in high-bandwidth screen modes anyway, the
1144 capability could be offered during a display suspend period (as described
1145 above), permitting a more efficient mechanism to rapidly fill memory with a
1146 predetermined value.
1147
1148 This capability could also support block filling, where the limits of the
1149 filled memory would be defined by the position and size of a screen area,
1150 although this would demand the provision of additional registers in the ULA to
1151 retain the details of such areas and additional logic to control the fill
1152 operation.
1153
1154 Enhancement: Region Filling
1155 ---------------------------
1156
1157 An alternative to memory writing might involve indicating regions using
1158 additional registers or memory where the ULA fills regions of the screen with
1159 content instead of reading from memory. Unlike hardware sprites which should
1160 realistically provide varied content, region filling could employ single
1161 colours or patterns, and one advantage of doing so would be that the ULA need
1162 not access memory at all within a particular region.
1163
1164 Regions would be defined on a row-by-row basis. Instead of reading memory and
1165 blitting a direct representation to the screen, the ULA would read region
1166 definitions containing a start column, region width and colour details. There
1167 might be a certain number of definitions allowed per row, or the ULA might
1168 just traverse an ordered list of such definitions with each one indicating the
1169 row, start column, region width and colour details.
1170
1171 One could even compress this information further by requiring only the row,
1172 start column and colour details with each subsequent definition terminating
1173 the effect of the previous one. However, one would also need to consider the
1174 convenience of preparing such definitions and whether efficient access to
1175 definitions for a particular row might be desirable. It might also be
1176 desirable to avoid having to prepare definitions for "empty" areas of the
1177 screen, effectively making the definition of the screen contents employ
1178 run-length encoding and employ only colour plus length information.
1179
1180 One application of region filling is that of simple 2D and 3D shape rendering.
1181 Although it is entirely possible to plot such shapes to the screen and have
1182 the ULA blit the memory contents to the screen, such operations consume
1183 bandwidth both in the initial plotting and in the final transfer to the
1184 screen. Region filling would reduce such bandwidth usage substantially.
1185
1186 This way of representing screen images would make certain kinds of images
1187 unfeasible to represent - consider alternating single pixel values which could
1188 easily occur in some character bitmaps - even if an internal queue of regions
1189 were to be supported such that the ULA could read ahead and buffer such
1190 "bandwidth intensive" areas. Thus, the ULA might be better served providing
1191 this feature for certain areas of the display only as some kind of special
1192 graphics window.
1193
1194 Enhancement: Hardware Sprites
1195 -----------------------------
1196
1197 An enhanced ULA might provide hardware sprites, but this would be done in an
1198 way that is incompatible with the standard ULA, since no &FE*X locations are
1199 available for allocation. To keep the facility simple, hardware sprites would
1200 have a standard byte width and height.
1201
1202 The specification of sprites could involve the reservation of 16 locations
1203 (for example, &FE20-F) specifying a fixed number of eight sprites, with each
1204 location pair referring to the sprite data. By limiting the ULA to dealing
1205 with a fixed number of sprites, the work required inside the ULA would be
1206 reduced since it would avoid having to deal with arbitrary numbers of sprites.
1207
1208 The principal limitation on providing hardware sprites is that of having to
1209 obtain sprite data, given that the ULA is usually required to retrieve screen
1210 data, and given the lack of memory bandwidth available to retrieve sprite data
1211 (particularly from multiple sprites supposedly at the same position) and
1212 screen data simultaneously. Although the ULA could potentially read sprite
1213 data and screen data in alternate memory accesses in screen modes where the
1214 bandwidth is not already fully utilised, this would result in a degradation of
1215 performance.
1216
1217 Enhancement: Additional Screen Mode Configurations
1218 --------------------------------------------------
1219
1220 Alternative screen mode configurations could be supported. The ULA has to
1221 produce 640 pixel values across the screen, with pixel doubling or quadrupling
1222 employed to fill the screen width:
1223
1224 Screen width Columns Scaling Depth Bytes
1225 ------------ ------- ------- ----- -----
1226 640 80 x1 1 80
1227 320 40 x2 1, 2 40, 80
1228 160 20 x4 2, 4 40, 80
1229
1230 It must also use at most 80 byte-sized memory accesses to provide the
1231 information for the display. Given that characters must occupy an 8x8 pixel
1232 array, if a configuration featuring anything other than 20, 40 or 80 character
1233 columns is to be supported, compromises must be made such as the introduction
1234 of blank pixels either between characters (such as occurs between rows in MODE
1235 3 and 6) or at the end of a scanline (such as occurs at the end of the frame
1236 in MODE 3 and 6). Consider the following configuration:
1237
1238 Screen width Columns Scaling Depth Bytes Blank
1239 ------------ ------- ------- ----- ------ -----
1240 208 26 x3 1, 2 26, 52 16
1241
1242 Here, if the ULA can triple pixels, a 26 column mode with either 2 or 4
1243 colours could be provided, with 16 blank pixel values (out of a total of 640)
1244 generated either at the start or end (or split between the start and end) of
1245 each scanline.
1246
1247 Enhancement: Character Attributes
1248 ---------------------------------
1249
1250 The BBC Micro MODE 7 employs something resembling character attributes to
1251 support teletext displays, but depends on circuitry providing a character
1252 generator. The ZX Spectrum, on the other hand, provides character attributes
1253 as a means of colouring bitmapped graphics. Although such a feature is very
1254 limiting as the sole means of providing multicolour graphics, in situations
1255 where the choice is between low resolution multicolour graphics or high
1256 resolution monochrome graphics, character attributes provide a potentially
1257 useful compromise.
1258
1259 For each byte read, the ULA must deliver 8 pixel values (out of a total of
1260 640) to the video output, doing so by either emptying its pixel buffer on a
1261 pixel per cycle basis, or by multiplying pixels and thus holding them for more
1262 than one cycle. For example for a screen mode having 640 pixels in width:
1263
1264 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1265 Reads: B B
1266 Pixels: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
1267
1268 And for a screen mode having 320 pixels in width:
1269
1270 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1271 Reads: B
1272 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
1273
1274 However, in modes where less than 80 bytes are required to generate the pixel
1275 values, an enhanced ULA might be able to read additional bytes between those
1276 providing the bitmapped graphics data:
1277
1278 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1279 Reads: B A
1280 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
1281
1282 These additional bytes could provide colour information for the bitmapped data
1283 in the following character column (of 8 pixels). Since it would be desirable
1284 to apply attribute data to the first column, the initial 8 cycles might be
1285 configured to not produce pixel values.
1286
1287 For an entire character, attribute data need only be read for the first row of
1288 pixels for a character. The subsequent rows would have attribute information
1289 applied to them, although this would require the attribute data to be stored
1290 in some kind of buffer. Thus, the following access pattern would be observed:
1291
1292 Reads: A B _ B _ B _ B _ B _ B _ B _ B ...
1293
1294 In modes 3 and 6, the blank display lines could be used to retrieve attribute
1295 data:
1296
1297 Reads (blank): A _ A _ A _ A _ A _ A _ A _ A _ ...
1298 Reads (active): B _ B _ B _ B _ B _ B _ B _ B _ ...
1299 Reads (active): B _ B _ B _ B _ B _ B _ B _ B _ ...
1300 ...
1301
1302 See below for a discussion of using this for character data as well.
1303
1304 A whole byte used for colour information for a whole character would result in
1305 a choice of 256 colours, and this might be somewhat excessive. By only reading
1306 attribute bytes at every other opportunity, a choice of 16 colours could be
1307 applied individually to two characters.
1308
1309 Cycle: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
1310 Reads: B A B -
1311 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
1312
1313 Further reductions in attribute data access, offering 4 colours for every
1314 character in a four character block, for example, might also be worth
1315 considering.
1316
1317 Consider the following configurations for screen modes with a colour depth of
1318 1 bit per pixel for bitmap information:
1319
1320 Screen width Columns Scaling Bytes (B) Bytes (A) Colours Screen start
1321 ------------ ------- ------- --------- --------- ------- ------------
1322 320 40 x2 40 40 256 &5300
1323 320 40 x2 40 20 16 &5580 -> &5500
1324 320 40 x2 40 10 4 &56C0 -> &5600
1325 208 26 x3 26 26 256 &62C0 -> &6200
1326 208 26 x3 26 13 16 &6460 -> &6400
1327
1328 Enhancement: Text-Only Modes using Character and Attribute Data
1329 ---------------------------------------------------------------
1330
1331 In modes 3 and 6, the blank display lines could be used to retrieve character
1332 and attribute data instead of trying to insert it between bitmap data accesses,
1333 but this data would then need to be retained:
1334
1335 Reads: A C A C A C A C A C A C A C A C ...
1336 Reads: B _ B _ B _ B _ B _ B _ B _ B _ ...
1337
1338 Only attribute (A) and character (C) reads would require screen memory
1339 storage. Bitmap data reads (B) would involve either accesses to memory to
1340 obtain character definition details or could, at the cost of special storage
1341 in the ULA, involve accesses within the ULA that would then free up the RAM.
1342 However, the CPU would not benefit from having any extra access slots due to
1343 the limitations of the RAM access mechanism.
1344
1345 A scheme without caching might be possible. The same line of memory addresses
1346 might be visited over and over again for eight display lines, with an index
1347 into the bitmap data being incremented from zero to seven. The access patterns
1348 would look like this:
1349
1350 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 0)
1351 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 1)
1352 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 2)
1353 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 3)
1354 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 4)
1355 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 5)
1356 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 6)
1357 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 7)
1358
1359 The bandwidth requirements would be the sum of the accesses to read the
1360 character values (repeatedly) and those to read the bitmap data to reproduce
1361 the characters on screen.
1362
1363 Enhancement: MODE 7 Emulation using Character Attributes
1364 --------------------------------------------------------
1365
1366 If the scheme of applying attributes to character regions were employed to
1367 emulate MODE 7, in conjunction with the MODE 6 display technique, the
1368 following configuration would be required:
1369
1370 Screen width Columns Rows Bytes (B) Bytes (A) Colours Screen start
1371 ------------ ------- ---- --------- --------- ------- ------------
1372 320 40 25 40 20 16 &5ECC -> &5E00
1373 320 40 25 40 10 4 &5FC6 -> &5F00
1374
1375 Although this requires much more memory than MODE 7 (8500 bytes versus MODE
1376 7's 1000 bytes), it does not need much more memory than MODE 6, and it would
1377 at least make a limited 40-column multicolour mode available as a substitute
1378 for MODE 7.
1379
1380 Using the text-only enhancement with caching of data or with repeated reads of
1381 the same character data line for eight display lines, the storage requirements
1382 would be diminished substantially:
1383
1384 Screen width Columns Rows Bytes (C) Bytes (A) Colours Screen start
1385 ------------ ------- ---- --------- --------- ------- ------------
1386 320 40 25 40 20 16 &7A94 -> &7A00
1387 320 40 25 40 10 4 &7B1E -> &7B00
1388 320 40 25 40 5 2 &7B9B -> &7B00
1389 320 40 25 40 0 (2) &7C18 -> &7C00
1390 640 80 25 80 40 16 &7448 -> &7400
1391 640 80 25 80 20 4 &763C -> &7600
1392 640 80 25 80 10 2 &7736 -> &7700
1393 640 80 25 80 0 (2) &7830 -> &7800
1394
1395 Note that the colours describe the locally defined attributes for each
1396 character. When no attribute information is provided, the colours are defined
1397 globally.
1398
1399 Enhancement: Character Generator Support and Vertical Scaling
1400 -------------------------------------------------------------
1401
1402 When generating a picture, the ULA traverses screen memory, obtaining 40 or 80
1403 bytes of pixel data for each scanline. It then proceeds to the next row of
1404 pixel data for each successive scanline, with the exception of the text modes
1405 where scanlines may be blank (for which the row address does not advance).
1406 This arrangement provides a conventional bitmapped graphics display.
1407
1408 However, the ULA could instead facilitate the use of character generators. The
1409 principles involved can be demonstrated by the Jafa Mode 7 Mark 2 Display Unit
1410 expansion for the Electron which feeds the pixel data from a MODE 4 screen to
1411 a SAA5050 character generator to create a MODE 7 display. The solution adopted
1412 involves the replication of 40 bytes of character data across as many pixel
1413 rows as is necessary for the character generator to receive the appropriate
1414 character data for all scanlines in any given character row. If only a single
1415 40-byte row of character data were to be present for the first scanline of a
1416 character row, the character generator would only produce the first scanline
1417 (or the uppermost pixels of the characters) correctly, with the rest of the
1418 character shapes being ill-defined.
1419
1420 Here, the ULA could facilitate the use of memory-efficient character mode
1421 representations (such as MODE 7) by holding the row address for a number of
1422 scanlines, thus providing the same row of screen data for those scanlines,
1423 then advancing to the next row. Visualised in terms of pixel data, it would be
1424 like providing a display with a very low vertical resolution. Indeed, being
1425 able to reduce the vertical resolution of a display mode by a factor of eight
1426 or ten would be equivalent to the above character generation technique in
1427 terms of the ULA's screen reading activities.
1428
1429 By combining this vertical scaling or scanline replication with a circuit
1430 switchable between bitmapped graphics output and character graphics output,
1431 MODE 7 support could be made available, potentially as a hardware option
1432 separate from the ULA.
1433
1434 Enhancement: Compressed Character Data
1435 --------------------------------------
1436
1437 Another observation about text-only modes is that they only need to store a
1438 restricted set of bitmapped data values. Encoding this set of values in a
1439 smaller unit of storage than a byte could possibly help to reduce the amount
1440 of storage and bandwidth required to reproduce the characters on the display.
1441
1442 Enhancement: High Resolution Graphics
1443 -------------------------------------
1444
1445 Screen modes with higher resolutions and larger colour depths might be
1446 possible, but this would in most cases involve the allocation of more screen
1447 memory, and the ULA would probably then be obliged to page in such memory for
1448 the CPU to be able to sensibly access it all.
1449
1450 Enhancement: Genlock Support
1451 ----------------------------
1452
1453 The ULA generates a video signal in conjunction with circuitry producing the
1454 output features necessary for the correct display of the screen image.
1455 However, it appears that the ULA drives the video synchronisation mechanism
1456 instead of reacting to an existing signal. Genlock support might be possible
1457 if the ULA were made to be responsive to such external signals, resetting its
1458 address generators upon receiving synchronisation events.
1459
1460 Enhancement: Improved Sound
1461 ---------------------------
1462
1463 The standard ULA reserves &FE*6 for sound generation and cassette input/output
1464 (with bits 1 and 2 of &FE*7 being used to select either sound generation or
1465 cassette I/O), thus making it impossible to support multiple channels within
1466 the given framework. The BBC Micro ULA employs &FE40-&FE4F for sound control,
1467 and an enhanced ULA could adopt this interface.
1468
1469 The BBC Micro uses the SN76489 chip to produce sound, and the entire
1470 functionality of this chip could be emulated for enhanced sound, with a subset
1471 of the functionality exposed via the &FE*6 interface.
1472
1473 See: http://en.wikipedia.org/wiki/Texas_Instruments_SN76489
1474 See: http://www.smspower.org/Development/SN76489
1475
1476 Enhancement: Waveform Upload
1477 ----------------------------
1478
1479 As with a hardware sprite function, waveforms could be uploaded or referenced
1480 using locations as registers referencing memory regions.
1481
1482 Enhancement: Sound Input/Output
1483 -------------------------------
1484
1485 Since the ULA already controls audio input/output for cassette-based data, it
1486 would have been interesting to entertain the idea of sampling and output of
1487 sounds through the cassette interface. However, a significant amount of
1488 circuitry is employed to process the input signal for use by the ULA and to
1489 process the output signal for recording.
1490
1491 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw_03.htm#3.11
1492
1493 Enhancement: BBC ULA Compatibility
1494 ----------------------------------
1495
1496 Although some new ULA functions could be defined in a way that is also
1497 compatible with the BBC Micro, the BBC ULA is itself incompatible with the
1498 Electron ULA: &FE00-7 is reserved for the video controller in the BBC memory
1499 map, but controls various functions specific to the 6845 video controller;
1500 &FE08-F is reserved for the serial controller. It therefore becomes possible
1501 to disregard compatibility where compatibility is already disregarded for a
1502 particular area of functionality.
1503
1504 &FE20-F maps to video ULA functionality on the BBC Micro which provides
1505 control over the palette (using address &FE21, compared to &FE07-F on the
1506 Electron) and other system-specific functions. Since the location usage is
1507 generally incompatible, this region could be reused for other purposes.
1508
1509 Enhancement: Increased RAM, ULA and CPU Performance
1510 ---------------------------------------------------
1511
1512 More modern implementations of the hardware might feature faster RAM coupled
1513 with an increased ULA clock frequency in order to increase the bandwidth
1514 available to the ULA and to the CPU in situations where the ULA is not needed
1515 to perform work. A ULA employing a 32MHz clock would be able to complete the
1516 retrieval of a byte from RAM in only 250ns and thus be able to enable the CPU
1517 to access the RAM for the following 250ns even in display modes requiring the
1518 retrieval of a byte for the display every 500ns. The CPU could, subject to
1519 timing issues, run at 2MHz even in MODE 0, 1 and 2.
1520
1521 A scheme such as that described above would have a similar effect to the
1522 scheme employed in the BBC Micro, although the latter made use of RAM with a
1523 wider bandwidth in order to complete memory transfers within 250ns and thus
1524 permit the CPU to run continuously at 2MHz.
1525
1526 Higher bandwidth could potentially be used to implement exotic features such
1527 as RAM-resident hardware sprites or indeed any feature demanding RAM access
1528 concurrent with the production of the display image.
1529
1530 Enhancement: Multiple CPU Stacks and Zero Pages
1531 -----------------------------------------------
1532
1533 The 6502 maintains a stack for subroutine calls and register storage in page
1534 &01. Although the stack register can be manipulated using the TSX and TXS
1535 instructions, thereby permitting the maintenance of multiple stack regions and
1536 thus the potential coexistence of multiple programs each using a separate
1537 region, only programs that make little use of the stack (perhaps avoiding
1538 deeply-nested subroutine invocations and significant register storage) would
1539 be able to coexist without overwriting each other's stacks.
1540
1541 One way that this issue could be alleviated would involve the provision of a
1542 facility to redirect accesses to page &01 to other areas of memory. The ULA
1543 would provide a register that defines a physical page for the use of the CPU's
1544 "logical" page &01, and upon any access to page &01 by the CPU, the ULA would
1545 change the asserted address lines to redirect the access to the appropriate
1546 physical region.
1547
1548 By providing an 8-bit register, mapping to the most significant byte (MSB) of
1549 a 16-bit address, the ULA could then replace any MSB equal to &01 with the
1550 register value before the access is made. Where multiple programs coexist,
1551 upon switching programs, the register would be updated to point the ULA to the
1552 appropriate stack location, thus providing a simple memory management unit
1553 (MMU) capability.
1554
1555 In a similar fashion, zero page accesses could also be redirected so that code
1556 could run from sideways RAM and have zero page operations redirected to "upper
1557 memory" - for example, to page &BE (with stack accesses redirected to page
1558 &BF, perhaps) - thereby permitting most CPU operations to occur without
1559 inadvertent accesses to "lower memory" (the RAM) which would risk stalling the
1560 CPU as it contends with the ULA for memory access.
1561
1562 Such facilities could also be provided by a separate circuit between the CPU
1563 and ULA in a fashion similar to that employed by a "turbo" board, but unlike
1564 such boards, no additional RAM would be provided: all memory accesses would
1565 occur as normal through the ULA, albeit redirected when configured
1566 appropriately.
1567
1568 ULA Pin Functions
1569 -----------------
1570
1571 The functions of the ULA pins are described in the Electron Service Manual. Of
1572 interest to video processing are the following:
1573
1574 CSYNC (low during horizontal or vertical synchronisation periods, high
1575 otherwise)
1576
1577 HS (low during horizontal synchronisation periods, high otherwise)
1578
1579 RED, GREEN, BLUE (pixel colour outputs)
1580
1581 CLOCK IN (a 16MHz clock input, 4V peak to peak)
1582
1583 PHI OUT (a 1MHz, 2MHz and stopped clock signal for the CPU)
1584
1585 More general memory access pins:
1586
1587 RAM0...RAM3 (data lines to/from the RAM)
1588
1589 RA0...RA7 (address lines for sending both row and column addresses to the RAM)
1590
1591 RAS (row address strobe setting the row address on a negative edge - see the
1592 timing notes)
1593
1594 CAS (column address strobe setting the column address on a negative edge -
1595 see the timing notes)
1596
1597 WE (sets write enable with logic 0, read with logic 1)
1598
1599 ROM (select data access from ROM)
1600
1601 CPU-oriented memory access pins:
1602
1603 A0...A15 (CPU address lines)
1604
1605 PD0...PD7 (CPU data lines)
1606
1607 R/W (indicates CPU write with logic 0, CPU read with logic 1)
1608
1609 Interrupt-related pins:
1610
1611 NMI (CPU request for uninterrupted 1MHz access to memory)
1612
1613 IRQ (signal event to CPU)
1614
1615 POR (power-on reset, resetting the ULA on a positive edge and asserting the
1616 CPU's RST pin)
1617
1618 RST (master reset for the CPU signalled on power-up and by the Break key)
1619
1620 Keyboard-related pins:
1621
1622 KBD0...KBD3 (keyboard inputs)
1623
1624 CAPS LOCK (control status LED)
1625
1626 Sound-related pins:
1627
1628 SOUND O/P (sound output using internal oscillator)
1629
1630 Cassette-related pins:
1631
1632 CAS IN (cassette circuit input, between 0.5V to 2V peak to peak)
1633
1634 CAS OUT (pseudo-sinusoidal output, 1.8V peak to peak)
1635
1636 CAS RC (detect high tone)
1637
1638 CAS MO (motor relay output)
1639
1640 ÷13 IN (~1200 baud clock input)
1641
1642 ULA Socket
1643 ----------
1644
1645 The socket used for the ULA is a 3M/TexTool 268-5400 68-pin socket.
1646
1647 References
1648 ----------
1649
1650 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw.htm
1651
1652 About this Document
1653 -------------------
1654
1655 The most recent version of this document and accompanying distribution should
1656 be available from the following location:
1657
1658 http://hgweb.boddie.org.uk/ULA
1659
1660 Copyright and licence information can be found in the docs directory of this
1661 distribution - see docs/COPYING.txt for more information.