1 The Acorn Electron ULA
2 ======================
3
4 Principal Design and Feature Constraints
5 ----------------------------------------
6
7 The features of the ULA are limited in sophistication by the amount of time
8 and resources that can be allocated to each activity supporting the
9 fundamental features and obligations of the unit. Maintaining a screen display
10 based on the contents of RAM itself requires the ULA to have exclusive access
11 to various hardware resources for a significant period of time.
12
13 Whilst other elements of the ULA can in principle run in parallel with the
14 display refresh activity, they cannot also access the RAM at the same time.
15 Consequently, other features that might use the RAM must accept a reduced
16 allocation of that resource in comparison to a hypothetical architecture where
17 concurrent RAM access is possible at all times.
18
19 Thus, the principal constraint for many features is bandwidth. The duration of
20 access to hardware resources is one aspect of this; the rate at which such
21 resources can be accessed is another. For example, the RAM is not fast enough
22 to support access more frequently than one byte per 2MHz cycle, and for screen
23 modes involving 80 bytes of screen data per scanline, there are no free cycles
24 for anything other than the production of pixel output during the active
25 scanline periods.
26
27 Another constraint is imposed by the method of RAM access provided by the ULA.
28 The ULA is able to access RAM by fetching 4 bits at a time and thus managing
29 to transfer 8 bits within a single 2MHz cycle, this being sufficient to
30 provide display data for the most demanding screen modes. However, this
31 mechanism's timing requirements are beyond the capabilities of the CPU when
32 running at 2MHz.
33
34 Consequently, the CPU will only ever be able to access RAM via the ULA at
35 1MHz, even when the ULA is not accessing the RAM. Fortunately, when needing to
36 refresh the display, the ULA is still able to make use of the idle part of
37 each 1MHz cycle (or, rather, the idle 2MHz cycle unused by the CPU) to itself
38 access the RAM at a rate of 1 byte per 1MHz cycle (or 1 byte every other 2MHz
39 cycle), thus supporting the less demanding screen modes.
40
41 Timing
42 ------
43
44 According to 15.3.2 in the Advanced User Guide, there are 312 scanlines, 256
45 of which are used to generate pixel data. At 50Hz, this means that 128 cycles
46 are spent on each scanline (2000000 cycles / 50 = 40000 cycles; 40000 cycles /
47 312 ~= 128 cycles). This is consistent with the observation that each scanline
48 requires at most 80 bytes of data, and that the ULA is apparently busy for 40
49 out of 64 microseconds in each scanline.
50
51 (In fact, since the ULA is seeking to provide an image for an interlaced
52 625-line display, there are in fact two "fields" involved, one providing 312
53 scanlines and one providing 313 scanlines. See below for a description of the
54 video system.)
55
56 Access to RAM involves accessing four 64Kb dynamic RAM devices (IC4 to IC7,
57 each providing two bits of each byte) using two cycles within the 500ns period
58 of the 2MHz clock to complete each access operation. Since the CPU and ULA
59 have to take turns in accessing the RAM in MODE 4, 5 and 6, the CPU must
60 effectively run at 1MHz (since every other 500ns period involves the ULA
61 accessing RAM) during transfers of screen data.
62
63 The CPU is driven by an external clock (IC8) whose 16MHz frequency is divided
64 by the ULA (IC1) depending on the screen mode in use. Each 16MHz cycle is
65 approximately 62.5ns. To access the memory, the following patterns
66 corresponding to 16MHz cycles are required:
67
68 Time (ns): 0-------------- 500------------- ...
69 2 MHz cycle: 0 1 ...
70 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
71 /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ ...
72 ~RAS: /---\___________/---\___________ ...
73 ~CAS: /-----\___/-\___/-----\___/-\___ ...
74 Address events: A B C A B C ...
75 Data events: F S F S ...
76
77 ~RAS ops: 1 0 1 0 ...
78 ~CAS ops: 1 0 1 0 1 0 1 0 ...
79
80 Address ops: a b c a b c ...
81 Data ops: s f s f ...
82
83 ~WE: ......W ...
84 PHI OUT: \_______________/--------------- ...
85 CPU (RAM): L D ...
86 RnW: R ...
87
88 PHI OUT: \_______/-------\_______/------- ...
89 CPU (ROM): L D L D ...
90 RnW: R R ...
91
92 ~RAS must be high for 100ns, ~CAS must be high for 50ns.
93 ~RAS must be low for 150ns, ~CAS must be low for 90ns.
94 Data is available 150ns after ~RAS goes low, 90ns after ~CAS goes low.
95
96 Here, "A" and "B" respectively indicate the row and first column addresses
97 being latched into the RAM (on a negative edge for ~RAS and ~CAS
98 respectively), and "C" indicates the second column address being latched into
99 the RAM. Presumably, the first and second half-bytes can be read at "F" and
100 "S" respectively, and the row and column addresses must be made available at
101 "a" and "b" (and "c") respectively at the latest. Data can be read at "f" and
102 "s" for the first and second half-bytes respectively.
103
104 For the CPU, "L" indicates the point at which an address is taken from the CPU
105 address bus, on a negative edge of PHI OUT, with "D" being the point at which
106 data may either be read or be asserted for writing, on a positive edge of PHI
107 OUT. Here, PHI OUT is driven at 1MHz. Given that ~WE needs to be driven low
108 for writing or high for reading, and thus propagates RnW from the CPU, this
109 would need to be done before data would be retrieved and, according to the
110 TM4164EC4 datasheet, even as late as the column address is presented and ~CAS
111 brought low.
112
113 The TM4164EC4-15 has a row address access time of 150ns (maximum) and a column
114 address access time of 90ns (maximum), which appears to mean that ~RAS must be
115 held low for at least 150ns and that ~CAS must be held low for at least 90ns
116 before data becomes available. 150ns is 2.4 cycles (at 16MHz) and 90ns is 1.44
117 cycles. Thus, "A" to "F" is 2.5 cycles, "B" to "F" is 1.5 cycles, "C" to "S"
118 is 1.5 cycles.
119
120 Note that the Service Manual refers to the negative edge of RAS and CAS, but
121 the datasheet for the similar TM4164EC4 product shows latching on the negative
122 edge of ~RAS and ~CAS. It is possible that the Service Manual also intended to
123 communicate the latter behaviour. In the TM4164EC4 datasheet, it appears that
124 "page mode" provides the appropriate behaviour for that particular product.
125
126 The CPU, when accessing the RAM alone, apparently does not make use of the
127 vacated "slot" that the ULA would otherwise use (when interleaving accesses in
128 MODE 4, 5 and 6). It only employs a full 2MHz access frequency to memory when
129 accessing ROM (and potentially sideways RAM). The principal limitation is the
130 amount of time needed between issuing an address and receiving an entire byte
131 from the RAM, which is approximately 7 cycles (at 16MHz): much longer than the
132 4 cycles that would be required for 2MHz operation.
133
134 See: Acorn Electron Advanced User Guide
135 See: Acorn Electron Service Manual
136 http://chrisacorns.computinghistory.org.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf
137 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
138 See: http://stardot.org.uk/forums/viewtopic.php?p=120438#p120438
139
140 CPU Clock Notes
141 ---------------
142
143 "The 6502 receives an external square-wave clock input signal on pin 37, which
144 is usually labeled PHI0. [...] This clock input is processed within the 6502
145 to form two clock outputs: PHI1 and PHI2 (pins 3 and 39, respectively). PHI2
146 is essentially a copy of PHI0; more specifically, PHI2 is PHI0 after it's been
147 through two inverters and a push-pull amplifier. The same network of
148 transistors within the 6502 which generates PHI2 is also tied to PHI1, and
149 generates PHI1 as the inverse of PHI0. The reason why PHI1 and PHI2 are made
150 available to external devices is so that they know when they can access the
151 CPU. When PHI1 is high, this means that external devices can read from the
152 address bus or data bus; when PHI2 is high, this means that external devices
153 can write to the data bus."
154
155 See: http://lateblt.livejournal.com/88105.html
156
157 "The 6502 has a synchronous memory bus where the master clock is divided into
158 two phases (Phase 1 and Phase 2). The address is always generated during Phase
159 1 and all memory accesses take place during Phase 2."
160
161 See: http://www.jmargolin.com/vgens/vgens.htm
162
163 Thus, the inverse of PHI OUT provides the "other phase" of the clock. "During
164 Phase 1" means when PHI0 - really PHI2 - is high and "during Phase 2" means
165 when PHI1 is high.
166
167 Bandwidth Figures
168 -----------------
169
170 Using an observation of 128 2MHz cycles per scanline, 256 active lines and 312
171 total lines, with 80 cycles occurring in the active periods of display
172 scanlines, the following bandwidth calculations can be performed:
173
174 Total theoretical maximum:
175 128 cycles * 312 lines
176 = 39936 bytes
177
178 MODE 0, 1, 2:
179 ULA: 80 cycles * 256 lines
180 = 20480 bytes
181 CPU: 48 cycles / 2 * 256 lines
182 + 128 cycles / 2 * (312 - 256) lines
183 = 9728 bytes
184
185 MODE 3:
186 ULA: 80 cycles * 24 rows * 8 lines
187 = 15360 bytes
188 CPU: 48 cycles / 2 * 24 rows * 8 lines
189 + 128 cycles / 2 * (312 - (24 rows * 8 lines))
190 = 12288 bytes
191
192 MODE 4, 5:
193 ULA: 40 cycles * 256 lines
194 = 10240 bytes
195 CPU: (40 cycles + 48 cycles / 2) * 256 lines
196 + 128 cycles / 2 * (312 - 256) lines
197 = 19968 bytes
198
199 MODE 6:
200 ULA: 40 cycles * 24 rows * 8 lines
201 = 7680 bytes
202 CPU: (40 cycles + 48 cycles / 2) * 24 rows * 8 lines
203 + 128 cycles / 2 * (312 - (24 rows * 8 lines))
204 = 19968 bytes
205
206 Here, the division of 2 for CPU accesses is performed to indicate that the CPU
207 only uses every other access opportunity even in uncontended periods. See the
208 2MHz RAM Access enhancement below for bandwidth calculations that consider
209 this limitation removed.
210
211 Video Timing
212 ------------
213
214 According to 8.7 in the Service Manual, and the PAL Wikipedia page,
215 approximately 4.7µs is used for the sync pulse, 5.7µs for the "back porch"
216 (including the "colour burst"), and 1.65µs for the "front porch", totalling
217 12.05µs and thus leaving 51.95µs for the active video signal for each
218 scanline. As the Service Manual suggests in the oscilloscope traces, the
219 display information is transmitted more or less centred within the active
220 video period since the ULA will only be providing pixel data for 40µs in each
221 scanline.
222
223 Each 62.5ns cycle happens to correspond to 64µs divided by 1024, meaning that
224 each scanline can be divided into 1024 cycles, although only 640 at most are
225 actively used to provide pixel data. Pixel data production should only occur
226 within a certain period on each scanline, approximately 262 cycles after the
227 start of hsync:
228
229 active video period = 51.95µs
230 pixel data period = 40µs
231 total silent period = 51.95µs - 40µs = 11.95µs
232 silent periods (before and after) = 11.95µs / 2 = 5.975µs
233 hsync and back porch period = 4.7µs + 5.7µs = 10.4µs
234 time before pixel data period = 10.4µs + 5.975µs = 16.375µs
235 pixel data period start cycle = 16.375µs / 62.5ns = 262
236
237 By choosing a number divisible by 8, the RAM access mechanism can be
238 synchronised with the pixel production. Thus, 256 is a more appropriate start
239 cycle, where the HS (horizontal sync) signal corresponding to the 4µs sync
240 pulse (or "normal sync" pulse as described by the "PAL TV timing and voltages"
241 document) occurs at cycle 0.
242
243 To summarise:
244
245 HS signal starts at cycle 0 on each horizontal scanline
246 HS signal ends approximately 4µs later at cycle 64
247 Pixel data starts approximately 12µs later at cycle 256
248
249 "Re: Electron Memory Contention" provides measurements that appear consistent
250 with these calculations.
251
252 The "vertical blanking period", meaning the period before picture information
253 in each field is 25 lines out of 312 (or 313) and thus lasts for 1.6ms. Of
254 this, 2.5 lines occur before the vsync (field sync) which also lasts for 2.5
255 lines. Thus, the first visible scanline on the first field of a frame occurs
256 half way through the 23rd scanline period measured from the start of vsync
257 (indicated by "V" in the diagrams below):
258
259 10 20 23
260 Line in frame: 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8
261 Line from 1: 0 22 3
262 Line on screen: .:::::VVVVV::::: 12233445566
263 |_________________________________________________|
264 25 line vertical blanking period
265
266 In the second field of a frame, the first visible scanline coincides with the
267 24th scanline period measured from the start of line 313 in the frame:
268
269 310 336
270 Line in frame: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
271 Line from 313: 0 23 4
272 Line on screen: 88:::::VVVVV:::: 11223344
273 288 | |
274 |_________________________________________________|
275 25 line vertical blanking period
276
277 In order to consider only full lines, we might consider the start of each
278 frame to occur 23 lines after the start of vsync.
279
280 Again, it is likely that pixel data production should only occur on scanlines
281 within a certain period on each frame. The "625/50" document indicates that
282 only a certain region is "safe" to use, suggesting a vertically centred region
283 with approximately 15 blank lines above and below the picture. However, the
284 "PAL TV timing and voltages" document suggests 28 blank lines above and below
285 the picture. This would centre the 256 lines within the 312 lines of each
286 field and thus provide a start of picture approximately 5.5 or 5 lines after
287 the end of the blanking period or 28 or 27.5 lines after the start of vsync.
288
289 To summarise:
290
291 CSYNC signal starts at cycle 0
292 CSYNC signal ends approximately 160µs (2.5 lines) later at cycle 2560
293 Start of line occurs approximately 1632µs (5.5 lines) later at cycle 28672
294
295 See: http://en.wikipedia.org/wiki/PAL
296 See: http://en.wikipedia.org/wiki/Analog_television#Structure_of_a_video_signal
297 See: The 625/50 PAL Video Signal and TV Compatible Graphics Modes
298 http://lipas.uwasa.fi/~f76998/video/modes/
299 See: PAL TV timing and voltages
300 http://www.retroleum.co.uk/electronics-articles/pal-tv-timing-and-voltages/
301 See: Line Standards
302 http://www.pembers.freeserve.co.uk/World-TV-Standards/Line-Standards.html
303 See: Horizontal Blanking Interval of 405-, 525-, 625- and 819-Line Standards
304 http://www.pembers.freeserve.co.uk/World-TV-Standards/HBI.pdf
305 See: Re: Electron Memory Contention
306 http://www.stardot.org.uk/forums/viewtopic.php?p=134109#p134109
307
308 RAM Integrated Circuits
309 -----------------------
310
311 Unicorn Electronics appears to offer 4164 RAM chips (as well as 6502 series
312 CPUs such as the 6502, 6502A, 6502B and 65C02). These 4164 devices are
313 available in 100ns (4164-100), 120ns (4164-120) and 150ns (4164-150) variants,
314 have 16 pins and address 65536 bits through a 1-bit wide channel. Similarly,
315 ByteDelight.com sell 4164 devices primarily for the ZX Spectrum.
316
317 The documentation for the Electron mentions 4164-15 RAM chips for IC4-7, and
318 the Samsung-produced KM41464 series is apparently equivalent to the Texas
319 Instruments 4164 chips presumably used in the Electron.
320
321 The TM4164EC4 series combines 4 64K x 1b units into a single package and
322 appears similar to the TM4164EA4 featured on the Electron's circuit diagram
323 (in the Advanced User Guide but not the Service Manual), and it also has 22
324 pins providing 3 additional inputs and 3 additional outputs over the 16 pins
325 of the individual 4164-15 modules, presumably allowing concurrent access to
326 the packaged memory units.
327
328 As far as currently available replacements are concerned, the NTE4164 is a
329 potential candidate: according to the Vetco Electronics entry, it is
330 supposedly a replacement for the TMS4164-15 amongst many other parts. Similar
331 parts include the NTE2164 and the NTE6664, both of which appear to have
332 largely the same performance and connection characteristics. Meanwhile, the
333 NTE21256 appears to be a 16-pin replacement with four times the capacity that
334 maintains the single data input and output pins. Using the NTE21256 as a
335 replacement for all ICs combined would be difficult because of the single bit
336 output.
337
338 Another device equivalent to the 4164-15 appears to be available under the
339 code 41662 from Jameco Electronics as the Siemens HYB 4164-2. The Jameco Web
340 site lists data sheets for other devices on the same page, but these are
341 different and actually appear to be provided under the 41574 product code (but
342 are listed under 41464-10) and appear to be replacements for the TM4164EC4:
343 the Samsung KM41464A-15 and NEC µPD41464 employ 18 pins, eliminating 4 pins by
344 employing 4 pins for both input and output.
345
346 Pins I/O pins Row access Column access
347 ---- -------- ---------- -------------
348 TM4164EC4 22 4 + 4 150ns (15) 90ns (15)
349 KM41464AP 18 4 150ns (15) 75ns (15)
350 NTE21256 16 1 + 1 150ns 75ns
351 HYB 4164-2 16 1 + 1 150ns 100ns
352 µPD41464 18 4 120ns (12) 60ns (12)
353
354 See: TM4164EC4 65,536 by 4-Bit Dynamic RAM Module
355 http://www.datasheetarchive.com/dl/Datasheets-112/DSAP0051030.pdf
356 See: Dynamic RAMS
357 http://www.unicornelectronics.com/IC/DYNAMIC.html
358 See: New old stock 8x 4164 chips
359 http://www.bytedelight.com/?product=8x-4164-chips-new-old-stock
360 See: KM4164B 64K x 1 Bit Dynamic RAM with Page Mode
361 http://images.ihscontent.net/vipimages/VipMasterIC/IC/SAMS/SAMSD020/SAMSD020-45.pdf
362 See: NTE2164 Integrated Circuit 65,536 X 1 Bit Dynamic Random Access Memory
363 http://www.vetco.net/catalog/product_info.php?products_id=2806
364 See: NTE4164 - IC-NMOS 64K DRAM 150NS
365 http://www.vetco.net/catalog/product_info.php?products_id=3680
366 See: NTE21256 - IC-256K DRAM 150NS
367 http://www.vetco.net/catalog/product_info.php?products_id=2799
368 See: NTE21256 262,144-Bit Dynamic Random Access Memory (DRAM)
369 http://www.nteinc.com/specs/21000to21999/pdf/nte21256.pdf
370 See: NTE6664 - IC-MOS 64K DRAM 150NS
371 http://www.vetco.net/catalog/product_info.php?products_id=5213
372 See: NTE6664 Integrated Circuit 64K-Bit Dynamic RAM
373 http://www.nteinc.com/specs/6600to6699/pdf/nte6664.pdf
374 See: 4164-150: MAJOR BRANDS
375 http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41662_-1
376 See: HYB 4164-1, HYB 4164-2, HYB 4164-3 65,536-Bit Dynamic Random Access Memory (RAM)
377 http://www.jameco.com/Jameco/Products/ProdDS/41662SIEMENS.pdf
378 See: KM41464A NMOS DRAM 64K x 4 Bit Dynamic RAM with Page Mode
379 http://www.jameco.com/Jameco/Products/ProdDS/41662SAM.pdf
380 See: NEC µ41464 65,536 x 4-Bit Dynamic NMOS RAM
381 http://www.jameco.com/Jameco/Products/ProdDS/41662NEC.pdf
382 See: 41464-10: MAJOR BRANDS
383 http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41574_-1
384
385 Interrupts
386 ----------
387
388 The ULA generates IRQs (maskable interrupts) according to certain conditions
389 and these conditions are controlled by location &FE00:
390
391 * Vertical sync (bottom of displayed screen)
392 * 50MHz real time clock
393 * Transmit data empty
394 * Receive data full
395 * High tone detect
396
397 The ULA is also used to clear interrupt conditions through location &FE05. Of
398 particular significance is bit 7, which must be set if an NMI (non-maskable
399 interrupt) has occurred and has thus suspended ULA access to memory, restoring
400 the normal function of the ULA.
401
402 ROM Paging
403 ----------
404
405 Accessing different ROMs involves bits 0 to 3 of &FE05. Some special ROM
406 mappings exist:
407
408 8 keyboard
409 9 keyboard (duplicate)
410 10 BASIC ROM
411 11 BASIC ROM (duplicate)
412
413 Paging in a ROM involves the following procedure:
414
415 1. Assert ROM page enable (bit 3) together with a ROM number n in bits 0 to
416 2, corresponding to ROM number 8+n, such that one of ROMs 12 to 15 is
417 selected.
418 2. Where a ROM numbered from 0 to 7 is to be selected, set bit 3 to zero
419 whilst writing the desired ROM number n in bits 0 to 2.
420
421 See: http://stardot.org.uk/forums/viewtopic.php?p=136686#p136686
422
423 Keyboard Access
424 ---------------
425
426 The keyboard pages appear to be accessed at 1MHz just like the RAM.
427
428 See: https://stardot.org.uk/forums/viewtopic.php?p=254155#p254155
429
430 Shadow/Expanded Memory
431 ----------------------
432
433 The Electron exposes all sixteen address lines and all eight data lines
434 through the expansion bus. Using such lines, it is possible to provide
435 additional memory - typically sideways ROM and RAM - on expansion cards and
436 through cartridges, although the official cartridge specification provides
437 fewer address lines and only seeks to provide access to memory in 16K units.
438
439 Various modifications and upgrades were developed to offer "turbo"
440 capabilities to the Electron, permitting the CPU to access a separate 8K of
441 RAM at 2MHz, presumably preventing access to the low 8K of RAM accessible via
442 the ULA through additional logic. However, an enhanced ULA might support
443 independent CPU access to memory over the expansion bus by allowing itself to
444 be discharged from providing access to memory, potentially for a range of
445 addresses, and for the CPU to communicate with external memory uninterrupted.
446
447 Sideways RAM/ROM and Upper Memory Access
448 ----------------------------------------
449
450 Although the ULA controls the CPU clock, effectively slowing or stopping the
451 CPU when the ULA needs to access screen memory, it is apparently able to allow
452 the CPU to access addresses of &8000 and above - the upper region of memory -
453 at 2MHz independently of any access to RAM that the ULA might be performing,
454 only blocking the CPU if it attempts to access addresses of &7FFF and below
455 during any ULA memory access - the lower region of memory - by stopping or
456 stalling its clock.
457
458 Thus, the ULA remains aware of the level of the A15 line, only inhibiting the
459 CPU clock if the line goes low, when the CPU is attempting to access the lower
460 region of memory.
461
462 Hardware Scrolling (and Enhancement)
463 ------------------------------------
464
465 On the standard ULA, &FE02 and &FE03 map to a 9 significant bits address with
466 the least significant 5 bits being zero, thus limiting the scrolling
467 resolution to 64 bytes. An enhanced ULA could support a resolution of 2 bytes
468 using the same layout of these addresses.
469
470 |--&FE02--------------| |--&FE03--------------|
471 XX XX 14 13 12 11 10 09 08 07 06 XX XX XX XX XX
472
473 XX 14 13 12 11 10 09 08 07 06 05 04 03 02 01 XX
474
475 Arguably, a resolution of 8 bytes is more useful, since the mapping of screen
476 memory to pixel locations is character oriented. A change in 8 bytes would
477 permit a horizontal scrolling resolution of 2 pixels in MODE 2, 4 pixels in
478 MODE 1 and 5, and 8 pixels in MODE 0, 3 and 6. This resolution is actually
479 observed on the BBC Micro (see 18.11.2 in the BBC Microcomputer Advanced User
480 Guide).
481
482 One argument for a 2 byte resolution is smooth vertical scrolling. A pitfall
483 of changing the screen address by 2 bytes is the change in the number of lines
484 from the initial and final character rows that need reading by the ULA, which
485 would need to maintain this state information (although this is a relatively
486 trivial change). Another pitfall is the complication that might be introduced
487 to software writing bitmaps of character height to the screen.
488
489 See: http://pastraiser.com/computers/acornelectron/acornelectron.html
490
491 Enhancement: Mode Layouts
492 -------------------------
493
494 Merely changing the screen memory mappings in order to have Archimedes-style
495 row-oriented screen addresses (instead of character-oriented addresses) could
496 be done for the existing modes, but this might not be sufficiently beneficial,
497 especially since accessing regions of the screen would involve incrementing
498 pointers by amounts that are inconvenient on an 8-bit CPU.
499
500 However, instead of using a Archimedes-style mapping, column-oriented screen
501 addresses could be more feasibly employed: incrementing the address would
502 reference the vertical screen location below the currently-referenced location
503 (just as occurs within characters using the existing ULA); instead of
504 returning to the top of the character row and referencing the next horizontal
505 location after eight bytes, the address would reference the next character row
506 and continue to reference locations downwards over the height of the screen
507 until reaching the bottom; at the bottom, the next location would be the next
508 horizontal location at the top of the screen.
509
510 In other words, the memory layout for the screen would resemble the following
511 (for MODE 2):
512
513 &3000 &3100 ... &7F00
514 &3001 &3101
515 ... ...
516 &3007
517 &3008
518 ...
519 ... ...
520 &30FF ... &7FFF
521
522 Since there are 256 pixel rows, each column of locations would be addressable
523 using the low byte of the address. Meanwhile, the high byte would be
524 incremented to address different columns. Thus, addressing screen locations
525 would become a lot more convenient and potentially much more efficient for
526 certain kinds of graphical output.
527
528 One potential complication with this simplified addressing scheme arises with
529 hardware scrolling. Vertical hardware scrolling by one pixel row (not supported
530 with the existing ULA) would be achieved by incrementing or decrementing the
531 screen start address; by one character row, it would involve adding or
532 subtracting 8. However, the ULA only supports multiples of 64 when changing the
533 screen start address. Thus, if such a scheme were to be adopted, three
534 additional bits would need to be supported in the screen start register (see
535 "Hardware Scrolling (and Enhancement)" for more details). However, horizontal
536 scrolling would be much improved even under the severe constraints of the
537 existing ULA: only adjustments of 256 to the screen start address would be
538 required to produce single-location scrolling of as few as two pixels in MODE 2
539 (four pixels in MODEs 1 and 5, eight pixels otherwise).
540
541 More disruptive is the effect of this alternative layout on software.
542 Presumably, compatibility with the BBC Micro was the primary goal of the
543 Electron's hardware design. With the character-oriented screen layout in
544 place, system software (and application software accessing the screen
545 directly) would be relying on this layout to run on the Electron with little
546 or no modification. Although it might have been possible to change the system
547 software to use this column-oriented layout instead, this would have incurred
548 a development cost and caused additional work porting things like games to the
549 Electron. Moreover, a separate branch of the software from that supporting the
550 BBC Micro and closer derivatives would then have needed maintaining.
551
552 The decision to use the character-oriented layout in the BBC Micro may have
553 been related to the choice of circuitry and to facilitate a convenient
554 hardware implementation, and by the time the Electron was planned, it was too
555 late to do anything about this somewhat unfortunate choice.
556
557 Pixel Layouts
558 -------------
559
560 The pixel layouts are as follows:
561
562 Modes Depth (bpp) Pixels (from bits)
563 ----- ----------- ------------------
564 0, 3, 4, 6 1 7 6 5 4 3 2 1 0
565 1, 5 2 73 62 51 40
566 2 4 7531 6420
567
568 Since the ULA reads a half-byte at a time, one might expect it to attempt to
569 produce pixels for every half-byte, as opposed to handling entire bytes.
570 However, the pixel layout is not conducive to producing pixels as soon as a
571 half-byte has been read for a given full-byte location: in 1bpp modes the
572 first four pixels can indeed be produced, but in 2bpp and 4bpp modes the pixel
573 data is spread across the entire byte in different ways.
574
575 An alternative arrangement might be as follows:
576
577 Modes Depth (bpp) Pixels (from bits)
578 ----- ----------- ------------------
579 0, 3, 4, 6 1 7 6 5 4 3 2 1 0
580 1, 5 2 76 54 32 10
581 2 4 7654 3210
582
583 Just as the mode layouts were presumably decided by compatibility with the BBC
584 Micro, the pixel layouts will have been maintained for similar reasons.
585 Unfortunately, this layout prevents any optimisation of the ULA for handling
586 half-byte pixel data generally.
587
588 Enhancement: The Missing MODE 4
589 -------------------------------
590
591 The Electron inherits its screen mode selection from the BBC Micro, where MODE
592 3 is a text version of MODE 0, and where MODE 6 is a text version of MODE 4.
593 Neither MODE 3 nor MODE 6 is a genuine character-based text mode like MODE 7,
594 however, and they are merely implemented by skipping two scanlines in every
595 ten after the eight required to produce a character line. Thus, such modes
596 provide a 24-row display.
597
598 In principle, nothing prevents this "text mode" effect being applied to other
599 modes. The 20-column modes are not well-suited to displaying text, which
600 leaves MODE 1 which, unlike MODEs 3 and 6, can display 4 colours rather than
601 2. Although the need for a non-monochrome 40-column text mode is addressed by
602 MODE 7 on the BBC Micro, the Electron lacks such a mode.
603
604 If the 4-colour, 24-row variant of MODE 1 were to be provided, logically it
605 would occupy MODE 4 instead of the current MODE 4:
606
607 Screen mode Size (kilobytes) Colours Rows Resolution
608 ----------- ---------------- ------- ---- ----------
609 0 20 2 32 640x256
610 1 20 4 32 320x256
611 2 20 16 32 160x256
612 3 16 2 24 640x256
613 4 (new) 16 4 24 320x256
614 4 (old) 10 2 32 320x256
615 5 10 4 32 160x256
616 6 8 2 24 320x256
617
618 Thus, for increasing mode numbers, the size of each mode would be the same or
619 less than the preceding mode.
620
621 Enhancement: 2MHz RAM Access
622 ----------------------------
623
624 Given that the CPU and ULA both access RAM at 2MHz, but given that the CPU
625 when not competing with the ULA only accesses RAM every other 2MHz cycle (as
626 if the ULA still needed to access the RAM), one useful enhancement would be a
627 mechanism to let the CPU take over the ULA cycles outside the ULA's period of
628 activity comparable to the way the ULA takes over the CPU cycles in MODE 0 to
629 3.
630
631 Thus, the RAM access cycles would resemble the following in MODE 0 to 3:
632
633 Upon a transition from display cycles: UUUUCCCC (instead of UUUUC_C_)
634 On a non-display line: CCCCCCCC (instead of C_C_C_C_)
635
636 In MODE 4 to 6:
637
638 Upon a transition from display cycles: CUCUCCCC (instead of CUCUC_C_)
639 On a non-display line: CCCCCCCC (instead of C_C_C_C_)
640
641 This would improve CPU bandwidth as follows:
642
643 Standard ULA Enhanced ULA % Total Bandwidth Speedup
644 MODE 0, 1, 2 9728 bytes 19456 bytes 24% -> 49% 2
645 MODE 3 12288 bytes 24576 bytes 31% -> 62% 2
646 MODE 4, 5 19968 bytes 29696 bytes 50% -> 74% 1.5
647 MODE 6 19968 bytes 32256 bytes 50% -> 81% 1.6
648
649 (Here, the uncontended total 2MHz bandwidth for a display period would be
650 39936 bytes, being 128 cycles per line over 312 lines.)
651
652 With such an enhancement, MODE 0 to 3 experience a doubling of CPU bandwidth
653 because all access opportunities to RAM are doubled. Meanwhile, in the other
654 modes, some CPU accesses occur alongside ULA accesses and thus cannot be
655 doubled, but the CPU bandwidth increase is still significant.
656
657 Unfortunately, the mechanism for accessing the RAM is too slow to provide data
658 within the time constraints of 2MHz operation. There is no time remaining in a
659 2MHz cycle for the CPU to receive and process any retrieved data once the
660 necessary signalling has been performed. The only way for the CPU to be able
661 to access the RAM quickly enough would be to do away with the double 4-bit
662 access mechanism and to have a single 8-bit channel to the memory. This would
663 require twice as many 1-bit RAM chips or a different kind of RAM chip, but it
664 would also potentially simplify the ULA.
665
666 Enhancement: Region Blanking
667 ----------------------------
668
669 The problem of permitting character-oriented blitting in programs whilst
670 scrolling the screen by sub-character amounts could be mitigated by permitting
671 a region of the display to be blank, such as the final lines of the display.
672 Consider the following vertical scrolling by 2 bytes that would cause an
673 initial character row of 6 lines and a final character row of 2 lines:
674
675 6 lines - initial, partial character row
676 248 lines - 31 complete rows
677 2 lines - final, partial character row
678
679 If a routine were in use that wrote 8 line bitmaps to the partial character
680 row now split in two, it would be advisable to hide one of the regions in
681 order to prevent content appearing in the wrong place on screen (such as
682 content meant to appear at the top "leaking" onto the bottom). Blanking 6
683 lines would be sufficient, as can be seen from the following cases.
684
685 Scrolling up by 2 lines:
686
687 6 lines - initial, partial character row
688 240 lines - 30 complete rows
689 4 lines - part of 1 complete row
690 -----------------------------------------------------------------
691 4 lines - part of 1 complete row (hidden to maintain 250 lines)
692 2 lines - final, partial character row (hidden)
693
694 Scrolling down by 2 lines:
695
696 2 lines - initial, partial character row
697 248 lines - 31 complete rows
698 ----------------------------------------------------------
699 6 lines - final, partial character row (hidden)
700
701 Thus, in this case, region blanking would impose a 250 line display with the
702 bottom 6 lines blank.
703
704 See the description of the display suspend enhancement for a more efficient
705 way of blanking lines than merely blanking the palette whilst allowing the CPU
706 to perform useful work during the blanking period.
707
708 To control the blanking or suspending of lines at the top and bottom of the
709 display, a memory location could be dedicated to the task: the upper 4 bits
710 could define a blanking region of up to 16 lines at the top of the screen,
711 whereas the lower 4 bits could define such a region at the bottom of the
712 screen. If more lines were required, two locations could be employed, allowing
713 the top and bottom regions to occupy the entire screen.
714
715 Enhancement: Screen Height Adjustment
716 -------------------------------------
717
718 The height of the screen could be configurable in order to reduce screen
719 memory consumption. This is not quite done in MODE 3 and 6 since the start of
720 the screen appears to be rounded down to the nearest page, but by reducing the
721 height by amounts more than a page, savings would be possible. For example:
722
723 Screen width Depth Height Bytes per line Saving in bytes Start address
724 ------------ ----- ------ -------------- --------------- -------------
725 640 1 252 80 320 &3140 -> &3100
726 640 1 248 80 640 &3280 -> &3200
727 320 1 240 40 640 &5A80 -> &5A00
728 320 2 240 80 1280 &3500
729
730 Screen Mode Selection
731 ---------------------
732
733 Bits 3, 4 and 5 of address &FE*7 control the selected screen mode. For a wider
734 range of modes, the other bits of &FE*7 (related to sound, cassette
735 input/output and the Caps Lock LED) would need to be reassigned and bit 0
736 potentially being made available for use.
737
738 Enhancement: Palette Definition
739 -------------------------------
740
741 Since all memory accesses go via the ULA, an enhanced ULA could employ more
742 specific addresses than &FE*X to perform enhanced functions. For example, the
743 palette control is done using &FE*8-F and merely involves selecting predefined
744 colours, whereas an enhanced ULA could support the redefinition of all 16
745 colours using specific ranges such as &FE18-F (colours 0 to 7) and &FE28-F
746 (colours 8 to 15), where a single byte might provide 8 bits per pixel colour
747 specifications similar to those used on the Archimedes.
748
749 The principal limitation here is actually the hardware: the Electron has only
750 a single output line for each of the red, green and blue channels, and if
751 those outputs are strictly digital and can only be set to a "high" and "low"
752 value, then only the existing eight colours are possible. If a modern ULA were
753 able to output analogue values (or values at well-defined points between the
754 high and low values, such as the half-on value supported by the Amstrad CPC
755 series), it would still need to be assessed whether the circuitry could
756 successfully handle and propagate such values. Various sources indicate that
757 only "TTL levels" are supported by the RGB output circuit, and since there are
758 74LS08 AND logic gates involved in the RGB component outputs from the ULA, it
759 is likely that the ULA is expected to provide only "high" or "low" values.
760
761 Short of adding extra outputs from the ULA (either additional red, green and
762 blue outputs or a combined intensity output), another approach might involve
763 some kind of modulation where an output value might be encoded in multiple
764 pulses at a higher frequency than the pixel frequency. However, this would
765 demand additional circuitry outside the ULA, and component RGB monitors would
766 probably not be able to take advantage of this feature; only UHF and composite
767 video devices (the latter with the composite video colour support enabled on
768 the Electron's circuit board) would potentially benefit.
769
770 Flashing Colours
771 ----------------
772
773 According to the Advanced User Guide, "The cursor and flashing colours are
774 entirely generated in software: This means that all of the logical to physical
775 colour map must be changed to cause colours to flash." This appears to suggest
776 that the palette registers must be updated upon the flash counter - read and
777 written by OSBYTE &C1 (193) - reaching zero and that some way of changing the
778 colour pairs to be any combination of colours might be possible, instead of
779 having colour complements as pairs.
780
781 It is conceivable that the interrupt code responsible does the simple thing
782 and merely inverts the current values for any logical colours (LC) for which
783 the associated physical colour (as supplied as the second parameter to the VDU
784 19 call) has the top bit of its four bit value set. These top bits are not
785 recorded in the palette registers but are presumably recorded separately and
786 used to build bitmaps as follows:
787
788 LC 2 colour 4 colour 16 colour 4-bit value for inversion
789 -- -------- -------- --------- -------------------------
790 0 00010001 00010001 00010001 1, 1, 1
791 1 01000100 00100010 00010001 4, 2, 1
792 2 01000100 00100010 4, 2
793 3 10001000 00100010 8, 2
794 4 00010001 1
795 5 00010001 1
796 6 00100010 2
797 7 00100010 2
798 8 01000100 4
799 9 01000100 4
800 10 10001000 8
801 11 10001000 8
802 12 01000100 4
803 13 01000100 4
804 14 10001000 8
805 15 10001000 8
806
807 Inversion value calculation:
808
809 2 colour formula: 1 << (colour * 2)
810 4 colour formula: 1 << colour
811 16 colour formula: 1 << ((colour & 2) + ((colour & 8) * 2))
812
813 For example, where logical colour 0 has been mapped to a physical colour in
814 the range 8 to 15, a bitmap of 00010001 would be chosen as its contribution to
815 the inversion operation. (The lower three bits of the physical colour would be
816 used to set the underlying colour information affected by the inversion
817 operation.)
818
819 An operation in the interrupt code would then combine the bitmaps for all
820 logical colours in 2 and 4 colour modes, with the 16 colour bitmaps being
821 combined for groups of logical colours as follows:
822
823 Logical colours
824 ---------------
825 0, 2, 8, 10
826 4, 6, 12, 14
827 5, 7, 13, 15
828 1, 3, 9, 11
829
830 These combined bitmaps would be EORed with the existing palette register
831 values in order to perform the value inversion necessary to produce the
832 flashing effect.
833
834 Thus, in the VDU 19 operation, the appropriate inversion value would be
835 calculated for the logical colour, and this value would then be combined with
836 other inversion values in a dedicated memory location corresponding to the
837 colour's group as indicated above. Meanwhile, the palette channel values would
838 be derived from the lower three bits of the specified physical colour and
839 combined with other palette data in dedicated memory locations corresponding
840 to the palette registers.
841
842 Interestingly, although flashing colours on the BBC Micro are controlled by
843 toggling bit 0 of the &FE20 control register location for the Video ULA, the
844 actual colour inversion is done in hardware.
845
846 Enhancement: Palette Definition Lists
847 -------------------------------------
848
849 It can be useful to redefine the palette in order to change the colours
850 available for a particular region of the screen, particularly in modes where
851 the choice of colours is constrained, and if an increased colour depth were
852 available, palette redefinition would be useful to give the illusion of more
853 than 16 colours in MODE 2. Traditionally, palette redefinition has been done
854 by using interrupt-driven timers, but a more efficient approach would involve
855 presenting lists of palette definitions to the ULA so that it can change the
856 palette at a particular display line.
857
858 One might define a palette redefinition list in a region of memory and then
859 communicate its contents to the ULA by writing the address and length of the
860 list, along with the display line at which the palette is to be changed, to
861 ULA registers such that the ULA buffers the list and performs the redefinition
862 at the appropriate time. Throughput/bandwidth considerations might impose
863 restrictions on the practical length of such a list, however.
864
865 Enhancement: Display Synchronisation Interrupts
866 -----------------------------------------------
867
868 When completing each scanline of the display, the ULA could trigger an
869 interrupt. Since this might impact system performance substantially, the
870 feature would probably need to be configurable, and it might be sufficient to
871 have an interrupt only after a certain number of display lines instead.
872 Permitting the CPU to take action after eight lines would allow palette
873 switching and other effects to occur on a character row basis.
874
875 The ULA provides an interrupt at the end of the display period, presumably so
876 that software can schedule updates to the screen, avoid flickering or tearing,
877 and so on. However, some applications might benefit from an interrupt at, or
878 just before, the start of the display period so that palette modifications or
879 similar effects could be scheduled.
880
881 Enhancement: Palette-Free Modes
882 -------------------------------
883
884 Palette-free modes might be defined where bit values directly correspond to
885 the red, green and blue channels, although this would mostly make sense only
886 for modes with depths greater than the standard 4 bits per pixel, and such
887 modes would require more memory than MODE 2 if they were to have an acceptable
888 resolution.
889
890 Enhancement: Display Suspend
891 ----------------------------
892
893 Especially when writing to the screen memory, it could be beneficial to be
894 able to suspend the ULA's access to the memory, instead producing blank values
895 for all screen pixels until a program is ready to reveal the screen. This is
896 different from palette blanking since with a blank palette, the ULA is still
897 reading screen memory and translating its contents into pixel values that end
898 up being blank.
899
900 This function is reminiscent of a capability of the ZX81, albeit necessary on
901 that hardware to reduce the load on the system CPU which was responsible for
902 producing the video output. By allowing display suspend on the Electron, the
903 performance benefit would be derived from giving the CPU full access to the
904 memory bandwidth.
905
906 The region blanking feature mentioned above could be implemented using this
907 enhancement instead of employing palette blanking for the affected lines of
908 the display.
909
910 Enhancement: Memory Filling
911 ---------------------------
912
913 A capability that could be given to an enhanced ULA is that of permitting the
914 ULA to write to screen memory as well being able to read from it. Although
915 such a capability would probably not be useful in conjunction with the
916 existing read operations when producing a screen display, and insufficient
917 bandwidth would exist to do so in high-bandwidth screen modes anyway, the
918 capability could be offered during a display suspend period (as described
919 above), permitting a more efficient mechanism to rapidly fill memory with a
920 predetermined value.
921
922 This capability could also support block filling, where the limits of the
923 filled memory would be defined by the position and size of a screen area,
924 although this would demand the provision of additional registers in the ULA to
925 retain the details of such areas and additional logic to control the fill
926 operation.
927
928 Enhancement: Region Filling
929 ---------------------------
930
931 An alternative to memory writing might involve indicating regions using
932 additional registers or memory where the ULA fills regions of the screen with
933 content instead of reading from memory. Unlike hardware sprites which should
934 realistically provide varied content, region filling could employ single
935 colours or patterns, and one advantage of doing so would be that the ULA need
936 not access memory at all within a particular region.
937
938 Regions would be defined on a row-by-row basis. Instead of reading memory and
939 blitting a direct representation to the screen, the ULA would read region
940 definitions containing a start column, region width and colour details. There
941 might be a certain number of definitions allowed per row, or the ULA might
942 just traverse an ordered list of such definitions with each one indicating the
943 row, start column, region width and colour details.
944
945 One could even compress this information further by requiring only the row,
946 start column and colour details with each subsequent definition terminating
947 the effect of the previous one. However, one would also need to consider the
948 convenience of preparing such definitions and whether efficient access to
949 definitions for a particular row might be desirable. It might also be
950 desirable to avoid having to prepare definitions for "empty" areas of the
951 screen, effectively making the definition of the screen contents employ
952 run-length encoding and employ only colour plus length information.
953
954 One application of region filling is that of simple 2D and 3D shape rendering.
955 Although it is entirely possible to plot such shapes to the screen and have
956 the ULA blit the memory contents to the screen, such operations consume
957 bandwidth both in the initial plotting and in the final transfer to the
958 screen. Region filling would reduce such bandwidth usage substantially.
959
960 This way of representing screen images would make certain kinds of images
961 unfeasible to represent - consider alternating single pixel values which could
962 easily occur in some character bitmaps - even if an internal queue of regions
963 were to be supported such that the ULA could read ahead and buffer such
964 "bandwidth intensive" areas. Thus, the ULA might be better served providing
965 this feature for certain areas of the display only as some kind of special
966 graphics window.
967
968 Enhancement: Hardware Sprites
969 -----------------------------
970
971 An enhanced ULA might provide hardware sprites, but this would be done in an
972 way that is incompatible with the standard ULA, since no &FE*X locations are
973 available for allocation. To keep the facility simple, hardware sprites would
974 have a standard byte width and height.
975
976 The specification of sprites could involve the reservation of 16 locations
977 (for example, &FE20-F) specifying a fixed number of eight sprites, with each
978 location pair referring to the sprite data. By limiting the ULA to dealing
979 with a fixed number of sprites, the work required inside the ULA would be
980 reduced since it would avoid having to deal with arbitrary numbers of sprites.
981
982 The principal limitation on providing hardware sprites is that of having to
983 obtain sprite data, given that the ULA is usually required to retrieve screen
984 data, and given the lack of memory bandwidth available to retrieve sprite data
985 (particularly from multiple sprites supposedly at the same position) and
986 screen data simultaneously. Although the ULA could potentially read sprite
987 data and screen data in alternate memory accesses in screen modes where the
988 bandwidth is not already fully utilised, this would result in a degradation of
989 performance.
990
991 Enhancement: Additional Screen Mode Configurations
992 --------------------------------------------------
993
994 Alternative screen mode configurations could be supported. The ULA has to
995 produce 640 pixel values across the screen, with pixel doubling or quadrupling
996 employed to fill the screen width:
997
998 Screen width Columns Scaling Depth Bytes
999 ------------ ------- ------- ----- -----
1000 640 80 x1 1 80
1001 320 40 x2 1, 2 40, 80
1002 160 20 x4 2, 4 40, 80
1003
1004 It must also use at most 80 byte-sized memory accesses to provide the
1005 information for the display. Given that characters must occupy an 8x8 pixel
1006 array, if a configuration featuring anything other than 20, 40 or 80 character
1007 columns is to be supported, compromises must be made such as the introduction
1008 of blank pixels either between characters (such as occurs between rows in MODE
1009 3 and 6) or at the end of a scanline (such as occurs at the end of the frame
1010 in MODE 3 and 6). Consider the following configuration:
1011
1012 Screen width Columns Scaling Depth Bytes Blank
1013 ------------ ------- ------- ----- ------ -----
1014 208 26 x3 1, 2 26, 52 16
1015
1016 Here, if the ULA can triple pixels, a 26 column mode with either 2 or 4
1017 colours could be provided, with 16 blank pixel values (out of a total of 640)
1018 generated either at the start or end (or split between the start and end) of
1019 each scanline.
1020
1021 Enhancement: Character Attributes
1022 ---------------------------------
1023
1024 The BBC Micro MODE 7 employs something resembling character attributes to
1025 support teletext displays, but depends on circuitry providing a character
1026 generator. The ZX Spectrum, on the other hand, provides character attributes
1027 as a means of colouring bitmapped graphics. Although such a feature is very
1028 limiting as the sole means of providing multicolour graphics, in situations
1029 where the choice is between low resolution multicolour graphics or high
1030 resolution monochrome graphics, character attributes provide a potentially
1031 useful compromise.
1032
1033 For each byte read, the ULA must deliver 8 pixel values (out of a total of
1034 640) to the video output, doing so by either emptying its pixel buffer on a
1035 pixel per cycle basis, or by multiplying pixels and thus holding them for more
1036 than one cycle. For example for a screen mode having 640 pixels in width:
1037
1038 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1039 Reads: B B
1040 Pixels: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
1041
1042 And for a screen mode having 320 pixels in width:
1043
1044 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1045 Reads: B
1046 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
1047
1048 However, in modes where less than 80 bytes are required to generate the pixel
1049 values, an enhanced ULA might be able to read additional bytes between those
1050 providing the bitmapped graphics data:
1051
1052 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1053 Reads: B A
1054 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
1055
1056 These additional bytes could provide colour information for the bitmapped data
1057 in the following character column (of 8 pixels). Since it would be desirable
1058 to apply attribute data to the first column, the initial 8 cycles might be
1059 configured to not produce pixel values.
1060
1061 For an entire character, attribute data need only be read for the first row of
1062 pixels for a character. The subsequent rows would have attribute information
1063 applied to them, although this would require the attribute data to be stored
1064 in some kind of buffer. Thus, the following access pattern would be observed:
1065
1066 Reads: A B _ B _ B _ B _ B _ B _ B _ B ...
1067
1068 In modes 3 and 6, the blank display lines could be used to retrieve attribute
1069 data:
1070
1071 Reads (blank): A _ A _ A _ A _ A _ A _ A _ A _ ...
1072 Reads (active): B _ B _ B _ B _ B _ B _ B _ B _ ...
1073 Reads (active): B _ B _ B _ B _ B _ B _ B _ B _ ...
1074 ...
1075
1076 See below for a discussion of using this for character data as well.
1077
1078 A whole byte used for colour information for a whole character would result in
1079 a choice of 256 colours, and this might be somewhat excessive. By only reading
1080 attribute bytes at every other opportunity, a choice of 16 colours could be
1081 applied individually to two characters.
1082
1083 Cycle: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
1084 Reads: B A B -
1085 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
1086
1087 Further reductions in attribute data access, offering 4 colours for every
1088 character in a four character block, for example, might also be worth
1089 considering.
1090
1091 Consider the following configurations for screen modes with a colour depth of
1092 1 bit per pixel for bitmap information:
1093
1094 Screen width Columns Scaling Bytes (B) Bytes (A) Colours Screen start
1095 ------------ ------- ------- --------- --------- ------- ------------
1096 320 40 x2 40 40 256 &5300
1097 320 40 x2 40 20 16 &5580 -> &5500
1098 320 40 x2 40 10 4 &56C0 -> &5600
1099 208 26 x3 26 26 256 &62C0 -> &6200
1100 208 26 x3 26 13 16 &6460 -> &6400
1101
1102 Enhancement: Text-Only Modes using Character and Attribute Data
1103 ---------------------------------------------------------------
1104
1105 In modes 3 and 6, the blank display lines could be used to retrieve character
1106 and attribute data instead of trying to insert it between bitmap data accesses,
1107 but this data would then need to be retained:
1108
1109 Reads: A C A C A C A C A C A C A C A C ...
1110 Reads: B _ B _ B _ B _ B _ B _ B _ B _ ...
1111
1112 Only attribute (A) and character (C) reads would require screen memory
1113 storage. Bitmap data reads (B) would involve either accesses to memory to
1114 obtain character definition details or could, at the cost of special storage
1115 in the ULA, involve accesses within the ULA that would then free up the RAM.
1116 However, the CPU would not benefit from having any extra access slots due to
1117 the limitations of the RAM access mechanism.
1118
1119 A scheme without caching might be possible. The same line of memory addresses
1120 might be visited over and over again for eight display lines, with an index
1121 into the bitmap data being incremented from zero to seven. The access patterns
1122 would look like this:
1123
1124 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 0)
1125 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 1)
1126 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 2)
1127 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 3)
1128 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 4)
1129 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 5)
1130 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 6)
1131 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 7)
1132
1133 The bandwidth requirements would be the sum of the accesses to read the
1134 character values (repeatedly) and those to read the bitmap data to reproduce
1135 the characters on screen.
1136
1137 Enhancement: MODE 7 Emulation using Character Attributes
1138 --------------------------------------------------------
1139
1140 If the scheme of applying attributes to character regions were employed to
1141 emulate MODE 7, in conjunction with the MODE 6 display technique, the
1142 following configuration would be required:
1143
1144 Screen width Columns Rows Bytes (B) Bytes (A) Colours Screen start
1145 ------------ ------- ---- --------- --------- ------- ------------
1146 320 40 25 40 20 16 &5ECC -> &5E00
1147 320 40 25 40 10 4 &5FC6 -> &5F00
1148
1149 Although this requires much more memory than MODE 7 (8500 bytes versus MODE
1150 7's 1000 bytes), it does not need much more memory than MODE 6, and it would
1151 at least make a limited 40-column multicolour mode available as a substitute
1152 for MODE 7.
1153
1154 Using the text-only enhancement with caching of data or with repeated reads of
1155 the same character data line for eight display lines, the storage requirements
1156 would be diminished substantially:
1157
1158 Screen width Columns Rows Bytes (C) Bytes (A) Colours Screen start
1159 ------------ ------- ---- --------- --------- ------- ------------
1160 320 40 25 40 20 16 &7A94 -> &7A00
1161 320 40 25 40 10 4 &7B1E -> &7B00
1162 320 40 25 40 5 2 &7B9B -> &7B00
1163 320 40 25 40 0 (2) &7C18 -> &7C00
1164 640 80 25 80 40 16 &7448 -> &7400
1165 640 80 25 80 20 4 &763C -> &7600
1166 640 80 25 80 10 2 &7736 -> &7700
1167 640 80 25 80 0 (2) &7830 -> &7800
1168
1169 Note that the colours describe the locally defined attributes for each
1170 character. When no attribute information is provided, the colours are defined
1171 globally.
1172
1173 Enhancement: Compressed Character Data
1174 --------------------------------------
1175
1176 Another observation about text-only modes is that they only need to store a
1177 restricted set of bitmapped data values. Encoding this set of values in a
1178 smaller unit of storage than a byte could possibly help to reduce the amount
1179 of storage and bandwidth required to reproduce the characters on the display.
1180
1181 Enhancement: High Resolution Graphics
1182 -------------------------------------
1183
1184 Screen modes with higher resolutions and larger colour depths might be
1185 possible, but this would in most cases involve the allocation of more screen
1186 memory, and the ULA would probably then be obliged to page in such memory for
1187 the CPU to be able to sensibly access it all.
1188
1189 Enhancement: Genlock Support
1190 ----------------------------
1191
1192 The ULA generates a video signal in conjunction with circuitry producing the
1193 output features necessary for the correct display of the screen image.
1194 However, it appears that the ULA drives the video synchronisation mechanism
1195 instead of reacting to an existing signal. Genlock support might be possible
1196 if the ULA were made to be responsive to such external signals, resetting its
1197 address generators upon receiving synchronisation events.
1198
1199 Enhancement: Improved Sound
1200 ---------------------------
1201
1202 The standard ULA reserves &FE*6 for sound generation and cassette input/output
1203 (with bits 1 and 2 of &FE*7 being used to select either sound generation or
1204 cassette I/O), thus making it impossible to support multiple channels within
1205 the given framework. The BBC Micro ULA employs &FE40-&FE4F for sound control,
1206 and an enhanced ULA could adopt this interface.
1207
1208 The BBC Micro uses the SN76489 chip to produce sound, and the entire
1209 functionality of this chip could be emulated for enhanced sound, with a subset
1210 of the functionality exposed via the &FE*6 interface.
1211
1212 See: http://en.wikipedia.org/wiki/Texas_Instruments_SN76489
1213 See: http://www.smspower.org/Development/SN76489
1214
1215 Enhancement: Waveform Upload
1216 ----------------------------
1217
1218 As with a hardware sprite function, waveforms could be uploaded or referenced
1219 using locations as registers referencing memory regions.
1220
1221 Enhancement: Sound Input/Output
1222 -------------------------------
1223
1224 Since the ULA already controls audio input/output for cassette-based data, it
1225 would have been interesting to entertain the idea of sampling and output of
1226 sounds through the cassette interface. However, a significant amount of
1227 circuitry is employed to process the input signal for use by the ULA and to
1228 process the output signal for recording.
1229
1230 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw_03.htm#3.11
1231
1232 Enhancement: BBC ULA Compatibility
1233 ----------------------------------
1234
1235 Although some new ULA functions could be defined in a way that is also
1236 compatible with the BBC Micro, the BBC ULA is itself incompatible with the
1237 Electron ULA: &FE00-7 is reserved for the video controller in the BBC memory
1238 map, but controls various functions specific to the 6845 video controller;
1239 &FE08-F is reserved for the serial controller. It therefore becomes possible
1240 to disregard compatibility where compatibility is already disregarded for a
1241 particular area of functionality.
1242
1243 &FE20-F maps to video ULA functionality on the BBC Micro which provides
1244 control over the palette (using address &FE21, compared to &FE07-F on the
1245 Electron) and other system-specific functions. Since the location usage is
1246 generally incompatible, this region could be reused for other purposes.
1247
1248 Enhancement: Increased RAM, ULA and CPU Performance
1249 ---------------------------------------------------
1250
1251 More modern implementations of the hardware might feature faster RAM coupled
1252 with an increased ULA clock frequency in order to increase the bandwidth
1253 available to the ULA and to the CPU in situations where the ULA is not needed
1254 to perform work. A ULA employing a 32MHz clock would be able to complete the
1255 retrieval of a byte from RAM in only 250ns and thus be able to enable the CPU
1256 to access the RAM for the following 250ns even in display modes requiring the
1257 retrieval of a byte for the display every 500ns. The CPU could, subject to
1258 timing issues, run at 2MHz even in MODE 0, 1 and 2.
1259
1260 A scheme such as that described above would have a similar effect to the
1261 scheme employed in the BBC Micro, although the latter made use of RAM with a
1262 wider bandwidth in order to complete memory transfers within 250ns and thus
1263 permit the CPU to run continuously at 2MHz.
1264
1265 Higher bandwidth could potentially be used to implement exotic features such
1266 as RAM-resident hardware sprites or indeed any feature demanding RAM access
1267 concurrent with the production of the display image.
1268
1269 Enhancement: Multiple CPU Stacks and Zero Pages
1270 -----------------------------------------------
1271
1272 The 6502 maintains a stack for subroutine calls and register storage in page
1273 &01. Although the stack register can be manipulated using the TSX and TXS
1274 instructions, thereby permitting the maintenance of multiple stack regions and
1275 thus the potential coexistence of multiple programs each using a separate
1276 region, only programs that make little use of the stack (perhaps avoiding
1277 deeply-nested subroutine invocations and significant register storage) would
1278 be able to coexist without overwriting each other's stacks.
1279
1280 One way that this issue could be alleviated would involve the provision of a
1281 facility to redirect accesses to page &01 to other areas of memory. The ULA
1282 would provide a register that defines a physical page for the use of the CPU's
1283 "logical" page &01, and upon any access to page &01 by the CPU, the ULA would
1284 change the asserted address lines to redirect the access to the appropriate
1285 physical region.
1286
1287 By providing an 8-bit register, mapping to the most significant byte (MSB) of
1288 a 16-bit address, the ULA could then replace any MSB equal to &01 with the
1289 register value before the access is made. Where multiple programs coexist,
1290 upon switching programs, the register would be updated to point the ULA to the
1291 appropriate stack location, thus providing a simple memory management unit
1292 (MMU) capability.
1293
1294 In a similar fashion, zero page accesses could also be redirected so that code
1295 could run from sideways RAM and have zero page operations redirected to "upper
1296 memory" - for example, to page &BE (with stack accesses redirected to page
1297 &BF, perhaps) - thereby permitting most CPU operations to occur without
1298 inadvertent accesses to "lower memory" (the RAM) which would risk stalling the
1299 CPU as it contends with the ULA for memory access.
1300
1301 Such facilities could also be provided by a separate circuit between the CPU
1302 and ULA in a fashion similar to that employed by a "turbo" board, but unlike
1303 such boards, no additional RAM would be provided: all memory accesses would
1304 occur as normal through the ULA, albeit redirected when configured
1305 appropriately.
1306
1307 ULA Pin Functions
1308 -----------------
1309
1310 The functions of the ULA pins are described in the Electron Service Manual. Of
1311 interest to video processing are the following:
1312
1313 CSYNC (low during horizontal or vertical synchronisation periods, high
1314 otherwise)
1315
1316 HS (low during horizontal synchronisation periods, high otherwise)
1317
1318 RED, GREEN, BLUE (pixel colour outputs)
1319
1320 CLOCK IN (a 16MHz clock input, 4V peak to peak)
1321
1322 PHI OUT (a 1MHz, 2MHz and stopped clock signal for the CPU)
1323
1324 More general memory access pins:
1325
1326 RAM0...RAM3 (data lines to/from the RAM)
1327
1328 RA0...RA7 (address lines for sending both row and column addresses to the RAM)
1329
1330 RAS (row address strobe setting the row address on a negative edge - see the
1331 timing notes)
1332
1333 CAS (column address strobe setting the column address on a negative edge -
1334 see the timing notes)
1335
1336 WE (sets write enable with logic 0, read with logic 1)
1337
1338 ROM (select data access from ROM)
1339
1340 CPU-oriented memory access pins:
1341
1342 A0...A15 (CPU address lines)
1343
1344 PD0...PD7 (CPU data lines)
1345
1346 R/W (indicates CPU write with logic 0, CPU read with logic 1)
1347
1348 Interrupt-related pins:
1349
1350 NMI (CPU request for uninterrupted 1MHz access to memory)
1351
1352 IRQ (signal event to CPU)
1353
1354 POR (power-on reset, resetting the ULA on a positive edge and asserting the
1355 CPU's RST pin)
1356
1357 RST (master reset for the CPU signalled on power-up and by the Break key)
1358
1359 Keyboard-related pins:
1360
1361 KBD0...KBD3 (keyboard inputs)
1362
1363 CAPS LOCK (control status LED)
1364
1365 Sound-related pins:
1366
1367 SOUND O/P (sound output using internal oscillator)
1368
1369 Cassette-related pins:
1370
1371 CAS IN (cassette circuit input, between 0.5V to 2V peak to peak)
1372
1373 CAS OUT (pseudo-sinusoidal output, 1.8V peak to peak)
1374
1375 CAS RC (detect high tone)
1376
1377 CAS MO (motor relay output)
1378
1379 ÷13 IN (~1200 baud clock input)
1380
1381 ULA Socket
1382 ----------
1383
1384 The socket used for the ULA is a 3M/TexTool 268-5400 68-pin socket.
1385
1386 References
1387 ----------
1388
1389 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw.htm
1390
1391 About this Document
1392 -------------------
1393
1394 The most recent version of this document and accompanying distribution should
1395 be available from the following location:
1396
1397 http://hgweb.boddie.org.uk/ULA
1398
1399 Copyright and licence information can be found in the docs directory of this
1400 distribution - see docs/COPYING.txt for more information.