ULA

ULA.txt

80:89b5767d944d
2015-10-12 Paul Boddie Added a note about redirecting zero page accesses as well as stack accesses.
     1 The Acorn Electron ULA
     2 ======================
     3 
     4 Principal Design and Feature Constraints
     5 ----------------------------------------
     6 
     7 The features of the ULA are limited by the amount of time and resources that
     8 can be allocated to each activity necessary to support such features given the
     9 fundamental obligations of the unit. Maintaining a screen display based on the
    10 contents of RAM itself requires the ULA to have exclusive access to such
    11 hardware resources for a significant period of time. Whilst other elements of
    12 the ULA can in principle run in parallel with this activity, they cannot also
    13 access the RAM. Consequently, other features that might use the RAM must
    14 accept a reduced allocation of that resource in comparison to a hypothetical
    15 architecture where concurrent RAM access is possible.
    16 
    17 Thus, the principal constraint for many features is bandwidth. The duration of
    18 access to hardware resources is one aspect of this; the rate at which such
    19 resources can be accessed is another. For example, the RAM is not fast enough
    20 to support access more frequently than one byte per 2MHz cycle, and for screen
    21 modes involving 80 bytes of screen data per scanline, there are no free cycles
    22 for anything other than the production of pixel output during the active
    23 scanline periods.
    24 
    25 Timing
    26 ------
    27 
    28 According to 15.3.2 in the Advanced User Guide, there are 312 scanlines, 256
    29 of which are used to generate pixel data. At 50Hz, this means that 128 cycles
    30 are spent on each scanline (2000000 cycles / 50 = 40000 cycles; 40000 cycles /
    31 312 ~= 128 cycles). This is consistent with the observation that each scanline
    32 requires at most 80 bytes of data, and that the ULA is apparently busy for 40
    33 out of 64 microseconds in each scanline.
    34 
    35 (In fact, since the ULA is seeking to provide an image for an interlaced
    36 625-line display, there are in fact two "fields" involved, one providing 312
    37 scanlines and one providing 313 scanlines. See below for a description of the
    38 video system.)
    39 
    40 Access to RAM involves accessing four 64Kb dynamic RAM devices (IC4 to IC7,
    41 each providing two bits of each byte) using two cycles within the 500ns period
    42 of the 2MHz clock to complete each access operation. Since the CPU and ULA
    43 have to take turns in accessing the RAM in MODE 4, 5 and 6, the CPU must
    44 effectively run at 1MHz (since every other 500ns period involves the ULA
    45 accessing RAM). The CPU is driven by an external clock (IC8) whose 16MHz
    46 frequency is divided by the ULA (IC1) depending on the screen mode in use.
    47 
    48 Each 16MHz cycle is approximately 62.5ns. To access the memory, the following
    49 patterns corresponding to 16MHz cycles are required:
    50 
    51      Time (ns):  0-------------- 500------------ ...
    52    2 MHz cycle:  0               1               ...
    53   16 MHz cycle:  0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
    54           ~RAS:    0           1   0           1 ...
    55           ~CAS:      0   1 0   1     0   1 0   1 ...
    56                    A B     C       A B     C     ...
    57                        F     S         F     S   ...
    58                  a b     c       a b     c       ...
    59 
    60 Here, "A" and "B" respectively indicate the row and first column addresses
    61 being latched into the RAM (on a negative edge for ~RAS and ~CAS
    62 respectively), and "C" indicates the second column address being latched into
    63 the RAM. Presumably, the first and second half-bytes can be read at "F" and
    64 "S" respectively, and the row and column addresses must be made available at
    65 "a" and "b" (and "c") respectively at the latest.
    66 
    67 The TM4164EC4-15 has a row address access time of 150ns (maximum) and a column
    68 address access time of 90ns (maximum), which appears to mean that
    69 approximately two 16MHz cycles after the row address is latched, and one and a
    70 half cycles after the column address is latched, the data becomes available.
    71 
    72 Note that the Service Manual refers to the negative edge of RAS and CAS, but
    73 the datasheet for the similar TM4164EC4 product shows latching on the negative
    74 edge of ~RAS and ~CAS. It is possible that the Service Manual also intended to
    75 communicate the latter behaviour. In the TM4164EC4 datasheet, it appears that
    76 "page mode" provides the appropriate behaviour for that particular product.
    77 
    78 The CPU, when accessing the RAM alone, apparently does not make use of the
    79 vacated "slot" that the ULA would otherwise use (when interleaving accesses in
    80 MODE 4, 5 and 6). It only employs a full 2MHz access frequency to memory when
    81 accessing ROM (and potentially sideways RAM).
    82 
    83 See: Acorn Electron Advanced User Guide
    84 See: Acorn Electron Service Manual
    85      http://acorn.chriswhy.co.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf
    86 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
    87 See: http://stardot.org.uk/forums/viewtopic.php?p=120438#p120438
    88 
    89 Bandwidth Figures
    90 -----------------
    91 
    92 Using an observation of 128 2MHz cycles per scanline, 256 active lines and 312
    93 total lines, with 80 cycles occurring in the active periods of display
    94 scanlines, the following bandwidth calculations can be performed:
    95 
    96 Total theoretical maximum:
    97        128 cycles * 312 lines
    98      = 39936 bytes
    99 
   100 MODE 0, 1, 2:
   101 ULA:    80 cycles * 256 lines
   102      = 20480 bytes
   103 CPU:    48 cycles / 2 * 256 lines
   104      + 128 cycles / 2 * (312 - 256) lines
   105      = 9728 bytes
   106 
   107 MODE 3:
   108 ULA:    80 cycles * 24 rows * 8 lines
   109      = 15360 bytes
   110 CPU:    48 cycles / 2 * 24 rows * 8 lines
   111      + 128 cycles / 2 * (312 - (24 rows * 8 lines))
   112      = 12288 bytes
   113 
   114 MODE 4, 5:
   115 ULA:    40 cycles * 256 lines
   116      = 10240 bytes
   117 CPU:   (40 cycles + 48 cycles / 2) * 256 lines
   118      + 128 cycles / 2 * (312 - 256) lines
   119      = 19968 bytes
   120 
   121 MODE 6:
   122 ULA:    40 cycles * 24 rows * 8 lines
   123      = 7680 bytes
   124 CPU:   (40 cycles + 48 cycles / 2) * 24 rows * 8 lines
   125      + 128 cycles / 2 * (312 - (24 rows * 8 lines))
   126      = 19968 bytes
   127 
   128 Here, the division of 2 for CPU accesses is performed to indicate that the CPU
   129 only uses every other access opportunity even in uncontended periods. See the
   130 2MHz RAM Access enhancement below for bandwidth calculations that consider
   131 this limitation removed.
   132 
   133 Video Timing
   134 ------------
   135 
   136 According to 8.7 in the Service Manual, and the PAL Wikipedia page,
   137 approximately 4.7s is used for the sync pulse, 5.7s for the "back porch"
   138 (including the "colour burst"), and 1.65s for the "front porch", totalling
   139 12.05s and thus leaving 51.95s for the active video signal for each
   140 scanline. As the Service Manual suggests in the oscilloscope traces, the
   141 display information is transmitted more or less centred within the active
   142 video period since the ULA will only be providing pixel data for 40s in each
   143 scanline.
   144 
   145 Each 62.5ns cycle happens to correspond to 64s divided by 1024, meaning that
   146 each scanline can be divided into 1024 cycles, although only 640 at most are
   147 actively used to provide pixel data. Pixel data production should only occur
   148 within a certain period on each scanline, approximately 262 cycles after the
   149 start of hsync:
   150 
   151   active video period = 51.95s
   152   pixel data period = 40s
   153   total silent period = 51.95s - 40s = 11.95s
   154   silent periods (before and after) = 11.95s / 2 = 5.975s
   155   hsync and back porch period = 4.7s + 5.7s = 10.4s
   156   time before pixel data period = 10.4s + 5.975s = 16.375s
   157   pixel data period start cycle = 16.375s / 62.5ns = 262
   158 
   159 By choosing a number divisible by 8, the RAM access mechanism can be
   160 synchronised with the pixel production. Thus, 264 is a more appropriate start
   161 cycle.
   162 
   163 The "vertical blanking period", meaning the period before picture information
   164 in each field is 25 lines out of 312 (or 313) and thus lasts for 1.6ms. Of
   165 this, 2.5 lines occur before the vsync (field sync) which also lasts for 2.5
   166 lines. Thus, the first visible scanline on the first field of a frame occurs
   167 half way through the 23rd scanline period measured from the start of vsync:
   168 
   169                                         10                  20    23
   170   Line in frame:       1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8
   171     Line from 1:       0                                          22 3
   172  Line on screen: .:::::VVVVV:::::                                   12233445566
   173                   |_________________________________________________|
   174                            25 line vertical blanking period
   175 
   176 In the second field of a frame, the first visible scanline coincides with the
   177 24th scanline period measured from the start of line 313 in the frame:
   178 
   179                310                                                 336
   180   Line in frame: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
   181   Line from 313:       0                                            23 4
   182  Line on screen: 88:::::VVVVV::::                                    11223344
   183                288 |                                                 |
   184                    |_________________________________________________|
   185                             25 line vertical blanking period
   186 
   187 In order to consider only full lines, we might consider the start of each
   188 frame to occur 23 lines after the start of vsync.
   189 
   190 Again, it is likely that pixel data production should only occur on scanlines
   191 within a certain period on each frame. The "625/50" document indicates that
   192 only a certain region is "safe" to use, suggesting a vertically centred region
   193 with approximately 15 blank lines above and below the picture. Thus, the start
   194 of the picture could be chosen as 38 lines after the start of vsync.
   195 
   196 See: http://en.wikipedia.org/wiki/PAL
   197 See: http://en.wikipedia.org/wiki/Analog_television#Structure_of_a_video_signal
   198 See: The 625/50 PAL Video Signal and TV Compatible Graphics Modes
   199      http://lipas.uwasa.fi/~f76998/video/modes/
   200 See: PAL TV timing and voltages
   201      http://www.retroleum.co.uk/electronics-articles/pal-tv-timing-and-voltages/
   202 See: Line Standards
   203      http://www.pembers.freeserve.co.uk/World-TV-Standards/Line-Standards.html
   204 
   205 RAM Integrated Circuits
   206 -----------------------
   207 
   208 Unicorn Electronics appears to offer 4164 RAM chips (as well as 6502 series
   209 CPUs such as the 6502, 6502A, 6502B and 65C02). These 4164 devices are
   210 available in 100ns (4164-100), 120ns (4164-120) and 150ns (4164-150) variants,
   211 have 16 pins and address 65536 bits through a 1-bit wide channel. Similarly,
   212 ByteDelight.com sell 4164 devices primarily for the ZX Spectrum.
   213 
   214 The documentation for the Electron mentions 4164-15 RAM chips for IC4-7, and
   215 the Samsung-produced KM41464 series is apparently equivalent to the Texas
   216 Instruments 4164 chips presumably used in the Electron.
   217 
   218 The TM4164EC4 series combines 4 64K x 1b units into a single package and
   219 appears similar to the TM4164EA4 featured on the Electron's circuit diagram
   220 (in the Advanced User Guide but not the Service Manual), and it also has 22
   221 pins providing 3 additional inputs and 3 additional outputs over the 16 pins
   222 of the individual 4164-15 modules, presumably allowing concurrent access to
   223 the packaged memory units.
   224 
   225 As far as currently available replacements are concerned, the NTE4164 is a
   226 potential candidate: according to the Vetco Electronics entry, it is
   227 supposedly a replacement for the TMS4164-15 amongst many other parts. Similar
   228 parts include the NTE2164 and the NTE6664, both of which appear to have
   229 largely the same performance and connection characteristics. Meanwhile, the
   230 NTE21256 appears to be a 16-pin replacement with four times the capacity that
   231 maintains the single data input and output pins. Using the NTE21256 as a
   232 replacement for all ICs combined would be difficult because of the single bit
   233 output.
   234 
   235 Another device equivalent to the 4164-15 appears to be available under the
   236 code 41662 from Jameco Electronics as the Siemens HYB 4164-2. The Jameco Web
   237 site lists data sheets for other devices on the same page, but these are
   238 different and actually appear to be provided under the 41574 product code (but
   239 are listed under 41464-10) and appear to be replacements for the TM4164EC4:
   240 the Samsung KM41464A-15 and NEC PD41464 employ 18 pins, eliminating 4 pins by
   241 employing 4 pins for both input and output.
   242 
   243             Pins    I/O pins    Row access  Column access
   244             ----    --------    ----------  -------------
   245 TM4164EC4   22      4 + 4       150ns (15)  90ns (15)
   246 KM41464AP   18      4           150ns (15)  75ns (15)
   247 NTE21256    16      1 + 1       150ns       75ns
   248 HYB 4164-2  16      1 + 1       150ns       100ns
   249 PD41464    18      4           120ns (12)  60ns (12)
   250 
   251 See: TM4164EC4 65,536 by 4-Bit Dynamic RAM Module
   252      http://www.datasheetarchive.com/dl/Datasheets-112/DSAP0051030.pdf
   253 See: Dynamic RAMS
   254      http://www.unicornelectronics.com/IC/DYNAMIC.html
   255 See: New old stock 8x 4164 chips
   256      http://www.bytedelight.com/?product=8x-4164-chips-new-old-stock
   257 See: KM4164B 64K x 1 Bit Dynamic RAM with Page Mode
   258      http://images.ihscontent.net/vipimages/VipMasterIC/IC/SAMS/SAMSD020/SAMSD020-45.pdf
   259 See: NTE2164 Integrated Circuit 65,536 X 1 Bit Dynamic Random Access Memory
   260      http://www.vetco.net/catalog/product_info.php?products_id=2806
   261 See: NTE4164 - IC-NMOS 64K DRAM 150NS
   262      http://www.vetco.net/catalog/product_info.php?products_id=3680
   263 See: NTE21256 - IC-256K DRAM 150NS
   264      http://www.vetco.net/catalog/product_info.php?products_id=2799
   265 See: NTE21256 262,144-Bit Dynamic Random Access Memory (DRAM)
   266      http://www.nteinc.com/specs/21000to21999/pdf/nte21256.pdf
   267 See: NTE6664 - IC-MOS 64K DRAM 150NS
   268      http://www.vetco.net/catalog/product_info.php?products_id=5213
   269 See: NTE6664 Integrated Circuit 64K-Bit Dynamic RAM
   270      http://www.nteinc.com/specs/6600to6699/pdf/nte6664.pdf
   271 See: 4164-150: MAJOR BRANDS
   272      http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41662_-1
   273 See: HYB 4164-1, HYB 4164-2, HYB 4164-3 65,536-Bit Dynamic Random Access Memory (RAM)
   274      http://www.jameco.com/Jameco/Products/ProdDS/41662SIEMENS.pdf
   275 See: KM41464A NMOS DRAM 64K x 4 Bit Dynamic RAM with Page Mode
   276      http://www.jameco.com/Jameco/Products/ProdDS/41662SAM.pdf
   277 See: NEC 41464 65,536 x 4-Bit Dynamic NMOS RAM
   278      http://www.jameco.com/Jameco/Products/ProdDS/41662NEC.pdf
   279 See: 41464-10: MAJOR BRANDS
   280      http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41574_-1
   281 
   282 Interrupts
   283 ----------
   284 
   285 The ULA generates IRQs (maskable interrupts) according to certain conditions
   286 and these conditions are controlled by location &FE00:
   287 
   288   * Vertical sync (bottom of displayed screen)
   289   * 50MHz real time clock
   290   * Transmit data empty
   291   * Receive data full
   292   * High tone detect
   293 
   294 The ULA is also used to clear interrupt conditions through location &FE05. Of
   295 particular significance is bit 7, which must be set if an NMI (non-maskable
   296 interrupt) has occurred and has thus suspended ULA access to memory, restoring
   297 the normal function of the ULA.
   298 
   299 ROM Paging
   300 ----------
   301 
   302 Accessing different ROMs involves bits 0 to 3 of &FE05. Some special ROM
   303 mappings exist:
   304 
   305    8    keyboard
   306    9    keyboard (duplicate)
   307   10    BASIC ROM
   308   11    BASIC ROM (duplicate)
   309 
   310 Paging in a ROM involves the following procedure:
   311 
   312  1. Assert ROM page enable (bit 3) together with a ROM number n in bits 0 to
   313     2, corresponding to ROM number 8+n, such that one of ROMs 12 to 15 is
   314     selected.
   315  2. Where a ROM numbered from 0 to 7 is to be selected, set bit 3 to zero
   316     whilst writing the desired ROM number n in bits 0 to 2.
   317 
   318 Shadow/Expanded Memory
   319 ----------------------
   320 
   321 The Electron exposes all sixteen address lines and all eight data lines
   322 through the expansion bus. Using such lines, it is possible to provide
   323 additional memory - typically sideways ROM and RAM - on expansion cards and
   324 through cartridges, although the official cartridge specification provides
   325 fewer address lines and only seeks to provide access to memory in 16K units.
   326 
   327 Various modifications and upgrades were developed to offer "turbo"
   328 capabilities to the Electron, permitting the CPU to access a separate 8K of
   329 RAM at 2MHz, presumably preventing access to the low 8K of RAM accessible via
   330 the ULA through additional logic. However, an enhanced ULA might support
   331 independent CPU access to memory over the expansion bus by allowing itself to
   332 be discharged from providing access to memory, potentially for a range of
   333 addresses, and for the CPU to communicate with external memory uninterrupted.
   334 
   335 Sideways RAM/ROM and Upper Memory Access
   336 ----------------------------------------
   337 
   338 Although the ULA controls the CPU clock, effectively slowing or stopping the
   339 CPU when the ULA needs to access screen memory, it is apparently able to allow
   340 the CPU to access addresses of &8000 and above - the upper region of memory -
   341 at 2MHz independently of any access to RAM that the ULA might be performing,
   342 only blocking the CPU if it attempts to access addresses of &7FFF and below
   343 during any ULA memory access - the lower region of memory - by stopping or
   344 stalling its clock.
   345 
   346 Thus, the ULA remains aware of the level of the A15 line, only inhibiting the
   347 CPU clock if the line goes low, when the CPU is attempting to access the lower
   348 region of memory.
   349 
   350 Hardware Scrolling (and Enhancement)
   351 ------------------------------------
   352 
   353 On the standard ULA, &FE02 and &FE03 map to a 9 significant bits address with
   354 the least significant 5 bits being zero, thus limiting the scrolling
   355 resolution to 64 bytes. An enhanced ULA could support a resolution of 2 bytes
   356 using the same layout of these addresses.
   357 
   358 |--&FE02--------------| |--&FE03--------------|
   359 XX XX 14 13 12 11 10 09 08 07 06 XX XX XX XX XX
   360 
   361    XX 14 13 12 11 10 09 08 07 06 05 04 03 02 01 XX
   362 
   363 Arguably, a resolution of 8 bytes is more useful, since the mapping of screen
   364 memory to pixel locations is character oriented. A change in 8 bytes would
   365 permit a horizontal scrolling resolution of 2 pixels in MODE 2, 4 pixels in
   366 MODE 1 and 5, and 8 pixels in MODE 0, 3 and 6. This resolution is actually
   367 observed on the BBC Micro (see 18.11.2 in the BBC Microcomputer Advanced User
   368 Guide).
   369 
   370 One argument for a 2 byte resolution is smooth vertical scrolling. A pitfall
   371 of changing the screen address by 2 bytes is the change in the number of lines
   372 from the initial and final character rows that need reading by the ULA, which
   373 would need to maintain this state information (although this is a relatively
   374 trivial change). Another pitfall is the complication that might be introduced
   375 to software writing bitmaps of character height to the screen.
   376 
   377 Enhancement: The Missing MODE 4
   378 -------------------------------
   379 
   380 The Electron inherits its screen mode selection from the BBC Micro, where MODE
   381 3 is a text version of MODE 0, and where MODE 6 is a text version of MODE 4.
   382 Neither MODE 3 nor MODE 6 is a genuine character-based text mode like MODE 7,
   383 however, and they are merely implemented by skipping two scanlines in every
   384 ten after the eight required to produce a character line. Thus, such modes
   385 provide a 24-row display.
   386 
   387 In principle, nothing prevents this "text mode" effect being applied to other
   388 modes. The 20-column modes are not well-suited to displaying text, which
   389 leaves MODE 1 which, unlike MODEs 3 and 6, can display 4 colours rather than
   390 2. Although the need for a non-monochrome 40-column text mode is addressed by
   391 MODE 7 on the BBC Micro, the Electron lacks such a mode.
   392 
   393 If the 4-colour, 24-row variant of MODE 1 were to be provided, logically it
   394 would occupy MODE 4 instead of the current MODE 4:
   395 
   396   Screen mode  Size (kilobytes)  Colours  Rows  Resolution
   397   -----------  ----------------  -------  ----  ----------
   398   0            20                2        32    640x256
   399   1            20                4        32    320x256
   400   2            20                16       32    160x256
   401   3            16                2        24    640x256
   402   4 (new)      16                4        24    320x256
   403   4 (old)      10                2        32    320x256
   404   5            10                4        32    160x256
   405   6            8                 2        24    320x256
   406 
   407 Thus, for increasing mode numbers, the size of each mode would be the same or
   408 less than the preceding mode.
   409 
   410 Enhancement: 2MHz RAM Access
   411 ----------------------------
   412 
   413 Given that the CPU and ULA both access RAM at 2MHz, but given that the CPU
   414 when not competing with the ULA only accesses RAM every other 2MHz cycle (as
   415 if the ULA still needed to access the RAM), one useful enhancement would be a
   416 mechanism to let the CPU take over the ULA cycles outside the ULA's period of
   417 activity comparable to the way the ULA takes over the CPU cycles in MODE 0 to
   418 3.
   419 
   420 Thus, the RAM access cycles would resemble the following in MODE 0 to 3:
   421 
   422   Upon a transition from display cycles: UUUUCCCC (instead of UUUUC_C_)
   423   On a non-display line:                 CCCCCCCC (instead of C_C_C_C_)
   424 
   425 In MODE 4 to 6:
   426  
   427   Upon a transition from display cycles: CUCUCCCC (instead of CUCUC_C_)
   428   On a non-display line:                 CCCCCCCC (instead of C_C_C_C_)
   429 
   430 This would improve CPU bandwidth as follows:
   431 
   432                 Standard ULA    Enhanced ULA
   433 MODE 0, 1, 2    9728 bytes      19456 bytes
   434 MODE 3          12288 bytes     24576 bytes
   435 MODE 4, 5       19968 bytes     29696 bytes
   436 MODE 6          19968 bytes     32256 bytes
   437 
   438 With such an enhancement, MODE 0 to 3 experience a doubling of CPU bandwidth
   439 because all access opportunities to RAM are doubled. Meanwhile, in the other
   440 modes, some CPU accesses occur alongside ULA accesses and thus cannot be
   441 doubled, but the CPU bandwidth increase is still significant.
   442 
   443 Enhancement: Region Blanking
   444 ----------------------------
   445 
   446 The problem of permitting character-oriented blitting in programs whilst
   447 scrolling the screen by sub-character amounts could be mitigated by permitting
   448 a region of the display to be blank, such as the final lines of the display.
   449 Consider the following vertical scrolling by 2 bytes that would cause an
   450 initial character row of 6 lines and a final character row of 2 lines:
   451 
   452     6 lines - initial, partial character row
   453   248 lines - 31 complete rows
   454     2 lines - final, partial character row
   455 
   456 If a routine were in use that wrote 8 line bitmaps to the partial character
   457 row now split in two, it would be advisable to hide one of the regions in
   458 order to prevent content appearing in the wrong place on screen (such as
   459 content meant to appear at the top "leaking" onto the bottom). Blanking 6
   460 lines would be sufficient, as can be seen from the following cases.
   461 
   462 Scrolling up by 2 lines:
   463 
   464     6 lines - initial, partial character row
   465   240 lines - 30 complete rows
   466     4 lines - part of 1 complete row
   467   -----------------------------------------------------------------
   468     4 lines - part of 1 complete row (hidden to maintain 250 lines)
   469     2 lines - final, partial character row (hidden)
   470 
   471 Scrolling down by 2 lines:
   472 
   473     2 lines - initial, partial character row
   474   248 lines - 31 complete rows
   475   ----------------------------------------------------------
   476     6 lines - final, partial character row (hidden)
   477 
   478 Thus, in this case, region blanking would impose a 250 line display with the
   479 bottom 6 lines blank.
   480 
   481 See the description of the display suspend enhancement for a more efficient
   482 way of blanking lines than merely blanking the palette whilst allowing the CPU
   483 to perform useful work during the blanking period.
   484 
   485 To control the blanking or suspending of lines at the top and bottom of the
   486 display, a memory location could be dedicated to the task: the upper 4 bits
   487 could define a blanking region of up to 16 lines at the top of the screen,
   488 whereas the lower 4 bits could define such a region at the bottom of the
   489 screen. If more lines were required, two locations could be employed, allowing
   490 the top and bottom regions to occupy the entire screen.
   491 
   492 Enhancement: Screen Height Adjustment
   493 -------------------------------------
   494 
   495 The height of the screen could be configurable in order to reduce screen
   496 memory consumption. This is not quite done in MODE 3 and 6 since the start of
   497 the screen appears to be rounded down to the nearest page, but by reducing the
   498 height by amounts more than a page, savings would be possible. For example:
   499 
   500   Screen width  Depth  Height  Bytes per line  Saving in bytes  Start address
   501   ------------  -----  ------  --------------  ---------------  -------------
   502   640           1      252     80              320              &3140 -> &3100
   503   640           1      248     80              640              &3280 -> &3200
   504   320           1      240     40              640              &5A80 -> &5A00
   505   320           2      240     80              1280             &3500
   506 
   507 Screen Mode Selection
   508 ---------------------
   509 
   510 Bits 3, 4 and 5 of address &FE*7 control the selected screen mode. For a wider
   511 range of modes, the other bits of &FE*7 (related to sound, cassette
   512 input/output and the Caps Lock LED) would need to be reassigned and bit 0
   513 potentially being made available for use.
   514 
   515 Enhancement: Palette Definition
   516 -------------------------------
   517 
   518 Since all memory accesses go via the ULA, an enhanced ULA could employ more
   519 specific addresses than &FE*X to perform enhanced functions. For example, the
   520 palette control is done using &FE*8-F and merely involves selecting predefined
   521 colours, whereas an enhanced ULA could support the redefinition of all 16
   522 colours using specific ranges such as &FE18-F (colours 0 to 7) and &FE28-F
   523 (colours 8 to 15), where a single byte might provide 8 bits per pixel colour
   524 specifications similar to those used on the Archimedes.
   525 
   526 The principal limitation here is actually the hardware: the Electron has only
   527 a single output line for each of the red, green and blue channels, and if
   528 those outputs are strictly digital and can only be set to a "high" and "low"
   529 value, then only the existing eight colours are possible. If a modern ULA were
   530 able to output analogue values, it would still need to be assessed whether the
   531 circuitry could successfully handle and propagate such values. Various sources
   532 indicate that only "TTL levels" are supported by the RGB output circuit, and
   533 since there are 74LS08 AND logic gates involved in the RGB component outputs
   534 from the ULA, it is likely that the ULA is expected to provide only "high" or
   535 "low" values.
   536 
   537 Short of adding extra outputs from the ULA (either additional red, green and
   538 blue outputs or a combined intensity output, the former employed on the
   539 Amstrad CPC series), another approach might involve some kind of modulation
   540 where an output value might be encoded in multiple pulses at a higher
   541 frequency than the pixel frequency. However, this would demand additional
   542 circuitry outside the ULA, and component RGB monitors would probably not be
   543 able to take advantage of this feature; only UHF and composite video devices
   544 (the latter with the composite video colour support enabled on the Electron's
   545 circuit board) would potentially benefit.
   546 
   547 Flashing Colours
   548 ----------------
   549 
   550 According to the Advanced User Guide, "The cursor and flashing colours are
   551 entirely generated in software: This means that all of the logical to physical
   552 colour map must be changed to cause colours to flash." This appears to suggest
   553 that the palette registers must be updated upon the flash counter - read and
   554 written by OSBYTE &C1 (193) - reaching zero and that some way of changing the
   555 colour pairs to be any combination of colours might be possible, instead of
   556 having colour complements as pairs.
   557 
   558 It is conceivable that the interrupt code responsible does the simple thing
   559 and merely inverts the current values for any logical colours (LC) for which
   560 the associated physical colour (as supplied as the second parameter to the VDU
   561 19 call) has the top bit of its four bit value set. These top bits are not
   562 recorded in the palette registers but are presumably recorded separately and
   563 used to build bitmaps as follows:
   564 
   565   LC  2 colour  4 colour  16 colour  4-bit value for inversion
   566   --  --------  --------  ---------  -------------------------
   567    0  00010001  00010001  00010001   1, 1, 1
   568    1  01000100  00100010  00010001   4, 2, 1
   569    2            01000100  00100010      4, 2
   570    3            10001000  00100010      8, 2
   571    4                      00010001         1
   572    5                      00010001         1
   573    6                      00100010         2
   574    7                      00100010         2
   575    8                      01000100         4
   576    9                      01000100         4
   577   10                      10001000         8
   578   11                      10001000         8
   579   12                      01000100         4
   580   13                      01000100         4
   581   14                      10001000         8
   582   15                      10001000         8
   583 
   584   Inversion value calculation:
   585 
   586    2 colour formula: 1 << (colour * 2)
   587    4 colour formula: 1 << colour
   588   16 colour formula: 1 << ((colour & 2) + ((colour & 8) * 2))
   589 
   590 For example, where logical colour 0 has been mapped to a physical colour in
   591 the range 8 to 15, a bitmap of 00010001 would be chosen as its contribution to
   592 the inversion operation. (The lower three bits of the physical colour would be
   593 used to set the underlying colour information affected by the inversion
   594 operation.)
   595 
   596 An operation in the interrupt code would then combine the bitmaps for all
   597 logical colours in 2 and 4 colour modes, with the 16 colour bitmaps being
   598 combined for groups of logical colours as follows:
   599 
   600    Logical colours
   601    ---------------
   602    0,  2,  8, 10
   603    4,  6, 12, 14
   604    5,  7, 13, 15
   605    1,  3,  9, 11
   606 
   607 These combined bitmaps would be EORed with the existing palette register
   608 values in order to perform the value inversion necessary to produce the
   609 flashing effect.
   610 
   611 Thus, in the VDU 19 operation, the appropriate inversion value would be
   612 calculated for the logical colour, and this value would then be combined with
   613 other inversion values in a dedicated memory location corresponding to the
   614 colour's group as indicated above. Meanwhile, the palette channel values would
   615 be derived from the lower three bits of the specified physical colour and
   616 combined with other palette data in dedicated memory locations corresponding
   617 to the palette registers.
   618 
   619 Interestingly, although flashing colours on the BBC Micro are controlled by
   620 toggling bit 0 of the &FE20 control register location for the Video ULA, the
   621 actual colour inversion is done in hardware.
   622 
   623 Enhancement: Palette Definition Lists
   624 -------------------------------------
   625 
   626 It can be useful to redefine the palette in order to change the colours
   627 available for a particular region of the screen, particularly in modes where
   628 the choice of colours is constrained, and if an increased colour depth were
   629 available, palette redefinition would be useful to give the illusion of more
   630 than 16 colours in MODE 2. Traditionally, palette redefinition has been done
   631 by using interrupt-driven timers, but a more efficient approach would involve
   632 presenting lists of palette definitions to the ULA so that it can change the
   633 palette at a particular display line.
   634 
   635 One might define a palette redefinition list in a region of memory and then
   636 communicate its contents to the ULA by writing the address and length of the
   637 list, along with the display line at which the palette is to be changed, to
   638 ULA registers such that the ULA buffers the list and performs the redefinition
   639 at the appropriate time. Throughput/bandwidth considerations might impose
   640 restrictions on the practical length of such a list, however.
   641 
   642 Enhancement: Display Synchronisation Interrupts
   643 -----------------------------------------------
   644 
   645 When completing each scanline of the display, the ULA could trigger an
   646 interrupt. Since this might impact system performance substantially, the
   647 feature would probably need to be configurable, and it might be sufficient to
   648 have an interrupt only after a certain number of display lines instead.
   649 Permitting the CPU to take action after eight lines would allow palette
   650 switching and other effects to occur on a character row basis.
   651 
   652 The ULA provides an interrupt at the end of the display period, presumably so
   653 that software can schedule updates to the screen, avoid flickering or tearing,
   654 and so on. However, some applications might benefit from an interrupt at, or
   655 just before, the start of the display period so that palette modifications or
   656 similar effects could be scheduled.
   657 
   658 Enhancement: Palette-Free Modes
   659 -------------------------------
   660 
   661 Palette-free modes might be defined where bit values directly correspond to
   662 the red, green and blue channels, although this would mostly make sense only
   663 for modes with depths greater than the standard 4 bits per pixel, and such
   664 modes would require more memory than MODE 2 if they were to have an acceptable
   665 resolution.
   666 
   667 Enhancement: Display Suspend
   668 ----------------------------
   669 
   670 Especially when writing to the screen memory, it could be beneficial to be
   671 able to suspend the ULA's access to the memory, instead producing blank values
   672 for all screen pixels until a program is ready to reveal the screen. This is
   673 different from palette blanking since with a blank palette, the ULA is still
   674 reading screen memory and translating its contents into pixel values that end
   675 up being blank.
   676 
   677 This function is reminiscent of a capability of the ZX81, albeit necessary on
   678 that hardware to reduce the load on the system CPU which was responsible for
   679 producing the video output. By allowing display suspend on the Electron, the
   680 performance benefit would be derived from giving the CPU full access to the
   681 memory bandwidth.
   682 
   683 The region blanking feature mentioned above could be implemented using this
   684 enhancement instead of employing palette blanking for the affected lines of
   685 the display.
   686 
   687 Enhancement: Memory Filling
   688 ---------------------------
   689 
   690 A capability that could be given to an enhanced ULA is that of permitting the
   691 ULA to write to screen memory as well being able to read from it. Although
   692 such a capability would probably not be useful in conjunction with the
   693 existing read operations when producing a screen display, and insufficient
   694 bandwidth would exist to do so in high-bandwidth screen modes anyway, the
   695 capability could be offered during a display suspend period (as described
   696 above), permitting a more efficient mechanism to rapidly fill memory with a
   697 predetermined value.
   698 
   699 This capability could also support block filling, where the limits of the
   700 filled memory would be defined by the position and size of a screen area,
   701 although this would demand the provision of additional registers in the ULA to
   702 retain the details of such areas and additional logic to control the fill
   703 operation.
   704 
   705 Enhancement: Region Filling
   706 ---------------------------
   707 
   708 An alternative to memory writing might involve indicating regions using
   709 additional registers or memory where the ULA fills regions of the screen with
   710 content instead of reading from memory. Unlike hardware sprites which should
   711 realistically provide varied content, region filling could employ single
   712 colours or patterns, and one advantage of doing so would be that the ULA need
   713 not access memory at all within a particular region.
   714 
   715 Regions would be defined on a row-by-row basis. Instead of reading memory and
   716 blitting a direct representation to the screen, the ULA would read region
   717 definitions containing a start column, region width and colour details. There
   718 might be a certain number of definitions allowed per row, or the ULA might
   719 just traverse an ordered list of such definitions with each one indicating the
   720 row, start column, region width and colour details.
   721 
   722 One could even compress this information further by requiring only the row,
   723 start column and colour details with each subsequent definition terminating
   724 the effect of the previous one. However, one would also need to consider the
   725 convenience of preparing such definitions and whether efficient access to
   726 definitions for a particular row might be desirable. It might also be
   727 desirable to avoid having to prepare definitions for "empty" areas of the
   728 screen, effectively making the definition of the screen contents employ
   729 run-length encoding and employ only colour plus length information.
   730 
   731 One application of region filling is that of simple 2D and 3D shape rendering.
   732 Although it is entirely possible to plot such shapes to the screen and have
   733 the ULA blit the memory contents to the screen, such operations consume
   734 bandwidth both in the initial plotting and in the final transfer to the
   735 screen. Region filling would reduce such bandwidth usage substantially.
   736 
   737 This way of representing screen images would make certain kinds of images
   738 unfeasible to represent - consider alternating single pixel values which could
   739 easily occur in some character bitmaps - even if an internal queue of regions
   740 were to be supported such that the ULA could read ahead and buffer such
   741 "bandwidth intensive" areas. Thus, the ULA might be better served providing
   742 this feature for certain areas of the display only as some kind of special
   743 graphics window.
   744 
   745 Enhancement: Hardware Sprites
   746 -----------------------------
   747 
   748 An enhanced ULA might provide hardware sprites, but this would be done in an
   749 way that is incompatible with the standard ULA, since no &FE*X locations are
   750 available for allocation. To keep the facility simple, hardware sprites would
   751 have a standard byte width and height.
   752 
   753 The specification of sprites could involve the reservation of 16 locations
   754 (for example, &FE20-F) specifying a fixed number of eight sprites, with each
   755 location pair referring to the sprite data. By limiting the ULA to dealing
   756 with a fixed number of sprites, the work required inside the ULA would be
   757 reduced since it would avoid having to deal with arbitrary numbers of sprites.
   758 
   759 The principal limitation on providing hardware sprites is that of having to
   760 obtain sprite data, given that the ULA is usually required to retrieve screen
   761 data, and given the lack of memory bandwidth available to retrieve sprite data
   762 (particularly from multiple sprites supposedly at the same position) and
   763 screen data simultaneously. Although the ULA could potentially read sprite
   764 data and screen data in alternate memory accesses in screen modes where the
   765 bandwidth is not already fully utilised, this would result in a degradation of
   766 performance.
   767 
   768 Enhancement: Additional Screen Mode Configurations
   769 --------------------------------------------------
   770 
   771 Alternative screen mode configurations could be supported. The ULA has to
   772 produce 640 pixel values across the screen, with pixel doubling or quadrupling
   773 employed to fill the screen width:
   774 
   775   Screen width      Columns     Scaling     Depth       Bytes
   776   ------------      -------     -------     -----       -----
   777   640               80          x1          1           80
   778   320               40          x2          1, 2        40, 80
   779   160               20          x4          2, 4        40, 80
   780 
   781 It must also use at most 80 byte-sized memory accesses to provide the
   782 information for the display. Given that characters must occupy an 8x8 pixel
   783 array, if a configuration featuring anything other than 20, 40 or 80 character
   784 columns is to be supported, compromises must be made such as the introduction
   785 of blank pixels either between characters (such as occurs between rows in MODE
   786 3 and 6) or at the end of a scanline (such as occurs at the end of the frame
   787 in MODE 3 and 6). Consider the following configuration:
   788 
   789   Screen width      Columns     Scaling     Depth       Bytes       Blank
   790   ------------      -------     -------     -----       ------      -----
   791   208               26          x3          1, 2        26, 52      16
   792 
   793 Here, if the ULA can triple pixels, a 26 column mode with either 2 or 4
   794 colours could be provided, with 16 blank pixel values (out of a total of 640)
   795 generated either at the start or end (or split between the start and end) of
   796 each scanline.
   797 
   798 Enhancement: Character Attributes
   799 ---------------------------------
   800 
   801 The BBC Micro MODE 7 employs something resembling character attributes to
   802 support teletext displays, but depends on circuitry providing a character
   803 generator. The ZX Spectrum, on the other hand, provides character attributes
   804 as a means of colouring bitmapped graphics. Although such a feature is very
   805 limiting as the sole means of providing multicolour graphics, in situations
   806 where the choice is between low resolution multicolour graphics or high
   807 resolution monochrome graphics, character attributes provide a potentially
   808 useful compromise.
   809 
   810 For each byte read, the ULA must deliver 8 pixel values (out of a total of
   811 640) to the video output, doing so by either emptying its pixel buffer on a
   812 pixel per cycle basis, or by multiplying pixels and thus holding them for more
   813 than one cycle. For example for a screen mode having 640 pixels in width:
   814 
   815   Cycle:    0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15
   816   Reads:    B                               B
   817   Pixels:   0   1   2   3   4   5   6   7   0   1   2   3   4   5   6   7
   818 
   819 And for a screen mode having 320 pixels in width:
   820 
   821   Cycle:    0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15
   822   Reads:    B
   823   Pixels:   0   0   1   1   2   2   3   3   4   4   5   5   6   6   7   7
   824 
   825 However, in modes where less than 80 bytes are required to generate the pixel
   826 values, an enhanced ULA might be able to read additional bytes between those
   827 providing the bitmapped graphics data:
   828 
   829   Cycle:    0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15
   830   Reads:    B                               A
   831   Pixels:   0   0   1   1   2   2   3   3   4   4   5   5   6   6   7   7
   832 
   833 These additional bytes could provide colour information for the bitmapped data
   834 in the following character column (of 8 pixels). Since it would be desirable
   835 to apply attribute data to the first column, the initial 8 cycles might be
   836 configured to not produce pixel values.
   837 
   838 For an entire character, attribute data need only be read for the first row of
   839 pixels for a character. The subsequent rows would have attribute information
   840 applied to them, although this would require the attribute data to be stored
   841 in some kind of buffer. Thus, the following access pattern would be observed:
   842 
   843   Cycle:    A B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ...
   844 
   845 A whole byte used for colour information for a whole character would result in
   846 a choice of 256 colours, and this might be somewhat excessive. By only reading
   847 attribute bytes at every other opportunity, a choice of 16 colours could be
   848 applied individually to two characters.
   849 
   850   Cycle:    0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
   851   Reads:    B               A               B               -
   852   Pixels:   0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
   853 
   854 Further reductions in attribute data access, offering 4 colours for every
   855 character in a four character block, for example, might also be worth
   856 considering.
   857 
   858 Consider the following configurations for screen modes with a colour depth of
   859 1 bit per pixel for bitmap information:
   860 
   861   Screen width  Columns  Scaling  Bytes (B)  Bytes (A)  Colours  Screen start
   862   ------------  -------  -------  ---------  ---------  -------  ------------
   863   320           40       x2       40         40         256      &5300
   864   320           40       x2       40         20         16       &5580 -> &5500
   865   320           40       x2       40         10         4        &56C0 -> &5600
   866   208           26       x3       26         26         256      &62C0 -> &6200
   867   208           26       x3       26         13         16       &6460 -> &6400
   868 
   869 Enhancement: MODE 7 Emulation using Character Attributes
   870 --------------------------------------------------------
   871 
   872 If the scheme of applying attributes to character regions were employed to
   873 emulate MODE 7, in conjunction with the MODE 6 display technique, the
   874 following configuration would be required:
   875 
   876   Screen width  Columns  Rows  Bytes (B)  Bytes (A)  Colours  Screen start
   877   ------------  -------  ----  ---------  ---------  -------  ------------
   878   320           40       25    40         20         16       &5ECC -> &5E00
   879   320           40       25    40         10         4        &5FC6 -> &5F00
   880 
   881 Although this requires much more memory than MODE 7 (8500 bytes versus MODE
   882 7's 1000 bytes), it does not need much more memory than MODE 6, and it would
   883 at least make a limited 40-column multicolour mode available as a substitute
   884 for MODE 7.
   885 
   886 Enhancement: High Resolution Graphics and Mode Layouts
   887 ------------------------------------------------------
   888 
   889 Screen modes with different screen memory mappings, higher resolutions and
   890 larger colour depths might be possible, but this would in most cases involve
   891 the allocation of more screen memory, and the ULA would probably then be
   892 obliged to page in such memory for the CPU to be able to sensibly access it
   893 all. Merely changing the memory mappings in order to have Archimedes-style
   894 row-oriented screen addresses (instead of character-oriented addresses) could
   895 be done for the existing modes, but this might not be sufficiently beneficial,
   896 especially since accessing regions of the screen would involve incrementing
   897 pointers by amounts that are inconvenient on an 8-bit CPU.
   898 
   899 Enhancement: Genlock Support
   900 ----------------------------
   901 
   902 The ULA generates a video signal in conjunction with circuitry producing the
   903 output features necessary for the correct display of the screen image.
   904 However, it appears that the ULA drives the video synchronisation mechanism
   905 instead of reacting to an existing signal. Genlock support might be possible
   906 if the ULA were made to be responsive to such external signals, resetting its
   907 address generators upon receiving synchronisation events.
   908 
   909 Enhancement: Improved Sound
   910 ---------------------------
   911 
   912 The standard ULA reserves &FE*6 for sound generation and cassette input/output
   913 (with bits 1 and 2 of &FE*7 being used to select either sound generation or
   914 cassette I/O), thus making it impossible to support multiple channels within
   915 the given framework. The BBC Micro ULA employs &FE40-&FE4F for sound control,
   916 and an enhanced ULA could adopt this interface.
   917 
   918 The BBC Micro uses the SN76489 chip to produce sound, and the entire
   919 functionality of this chip could be emulated for enhanced sound, with a subset
   920 of the functionality exposed via the &FE*6 interface.
   921 
   922 See: http://en.wikipedia.org/wiki/Texas_Instruments_SN76489
   923 
   924 Enhancement: Waveform Upload
   925 ----------------------------
   926 
   927 As with a hardware sprite function, waveforms could be uploaded or referenced
   928 using locations as registers referencing memory regions.
   929 
   930 Enhancement: Sound Input/Output
   931 -------------------------------
   932 
   933 Since the ULA already controls audio input/output for cassette-based data, it
   934 would have been interesting to entertain the idea of sampling and output of
   935 sounds through the cassette interface. However, a significant amount of
   936 circuitry is employed to process the input signal for use by the ULA and to
   937 process the output signal for recording.
   938 
   939 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw_03.htm#3.11
   940 
   941 Enhancement: BBC ULA Compatibility
   942 ----------------------------------
   943 
   944 Although some new ULA functions could be defined in a way that is also
   945 compatible with the BBC Micro, the BBC ULA is itself incompatible with the
   946 Electron ULA: &FE00-7 is reserved for the video controller in the BBC memory
   947 map, but controls various functions specific to the 6845 video controller;
   948 &FE08-F is reserved for the serial controller. It therefore becomes possible
   949 to disregard compatibility where compatibility is already disregarded for a
   950 particular area of functionality.
   951 
   952 &FE20-F maps to video ULA functionality on the BBC Micro which provides
   953 control over the palette (using address &FE21, compared to &FE07-F on the
   954 Electron) and other system-specific functions. Since the location usage is
   955 generally incompatible, this region could be reused for other purposes.
   956 
   957 Enhancement: Increased RAM, ULA and CPU Performance
   958 ---------------------------------------------------
   959 
   960 More modern implementations of the hardware might feature faster RAM coupled
   961 with an increased ULA clock frequency in order to increase the bandwidth
   962 available to the ULA and to the CPU in situations where the ULA is not needed
   963 to perform work. A ULA employing a 32MHz clock would be able to complete the
   964 retrieval of a byte from RAM in only 250ns and thus be able to enable the CPU
   965 to access the RAM for the following 250ns even in display modes requiring the
   966 retrieval of a byte for the display every 500ns. The CPU could, subject to
   967 timing issues, run at 2MHz even in MODE 0, 1 and 2.
   968 
   969 A scheme such as that described above would have a similar effect to the
   970 scheme employed in the BBC Micro, although the latter made use of RAM with a
   971 wider bandwidth in order to complete memory transfers within 250ns and thus
   972 permit the CPU to run continuously at 2MHz.
   973 
   974 Higher bandwidth could potentially be used to implement exotic features such
   975 as RAM-resident hardware sprites or indeed any feature demanding RAM access
   976 concurrent with the production of the display image.
   977 
   978 Enhancement: Multiple CPU Stacks and Zero Pages
   979 -----------------------------------------------
   980 
   981 The 6502 maintains a stack for subroutine calls and register storage in page
   982 &01. Although the stack register can be manipulated using the TSX and TXS
   983 instructions, thereby permitting the maintenance of multiple stack regions and
   984 thus the potential coexistence of multiple programs each using a separate
   985 region, only programs that make little use of the stack (perhaps avoiding
   986 deeply-nested subroutine invocations and significant register storage) would
   987 be able to coexist without overwriting each other's stacks.
   988 
   989 One way that this issue could be alleviated would involve the provision of a
   990 facility to redirect accesses to page &01 to other areas of memory. The ULA
   991 would provide a register that defines a physical page for the use of the CPU's
   992 "logical" page &01, and upon any access to page &01 by the CPU, the ULA would
   993 change the asserted address lines to redirect the access to the appropriate
   994 physical region.
   995 
   996 By providing an 8-bit register, mapping to the most significant byte (MSB) of
   997 a 16-bit address, the ULA could then replace any MSB equal to &01 with the
   998 register value before the access is made. Where multiple programs coexist,
   999 upon switching programs, the register would be updated to point the ULA to the
  1000 appropriate stack location, thus providing a simple memory management unit
  1001 (MMU) capability.
  1002 
  1003 In a similar fashion, zero page accesses could also be redirected so that code
  1004 could run from sideways RAM and have zero page operations redirected to "upper
  1005 memory" - for example, to page &BE (with stack accesses redirected to page
  1006 &BF, perhaps) - thereby permitting most CPU operations to occur without
  1007 inadvertent accesses to "lower memory" (the RAM) which would risk stalling the
  1008 CPU as it contends with the ULA for memory access.
  1009 
  1010 Such facilities could also be provided by a separate circuit between the CPU
  1011 and ULA in a fashion similar to that employed by a "turbo" board, but unlike
  1012 such boards, no additional RAM would be provided: all memory accesses would
  1013 occur as normal through the ULA, albeit redirected when configured
  1014 appropriately.
  1015 
  1016 ULA Pin Functions
  1017 -----------------
  1018 
  1019 The functions of the ULA pins are described in the Electron Service Manual. Of
  1020 interest to video processing are the following:
  1021 
  1022   CSYNC (low during horizontal or vertical synchronisation periods, high
  1023          otherwise)
  1024 
  1025   HS (low during horizontal synchronisation periods, high otherwise)
  1026 
  1027   RED, GREEN, BLUE (pixel colour outputs)
  1028 
  1029   CLOCK IN (a 16MHz clock input, 4V peak to peak)
  1030 
  1031   PHI OUT (a 1MHz, 2MHz and stopped clock signal for the CPU)
  1032 
  1033 More general memory access pins:
  1034 
  1035   RAM0...RAM3 (data lines to/from the RAM)
  1036 
  1037   RA0...RA7 (address lines for sending both row and column addresses to the RAM)
  1038 
  1039   RAS (row address strobe setting the row address on a negative edge - see the
  1040        timing notes)
  1041 
  1042   CAS (column address strobe setting the column address on a negative edge -
  1043        see the timing notes)
  1044 
  1045   WE (sets write enable with logic 0, read with logic 1)
  1046 
  1047   ROM (select data access from ROM)
  1048 
  1049 CPU-oriented memory access pins:
  1050 
  1051   A0...A15 (CPU address lines)
  1052 
  1053   PD0...PD7 (CPU data lines)
  1054 
  1055   R/W (indicates CPU write with logic 0, CPU read with logic 1)
  1056 
  1057 Interrupt-related pins:
  1058 
  1059   NMI (CPU request for uninterrupted 1MHz access to memory)
  1060 
  1061   IRQ (signal event to CPU)
  1062 
  1063   POR (power-on reset, resetting the ULA on a positive edge and asserting the
  1064        CPU's RST pin)
  1065 
  1066   RST (master reset for the CPU signalled on power-up and by the Break key)
  1067 
  1068 Keyboard-related pins:
  1069 
  1070   KBD0...KBD3 (keyboard inputs)
  1071 
  1072   CAPS LOCK (control status LED)
  1073 
  1074 Sound-related pins:
  1075 
  1076   SOUND O/P (sound output using internal oscillator)
  1077 
  1078 Cassette-related pins:
  1079 
  1080   CAS IN (cassette circuit input, between 0.5V to 2V peak to peak)
  1081 
  1082   CAS OUT (pseudo-sinusoidal output, 1.8V peak to peak)
  1083 
  1084   CAS RC (detect high tone)
  1085 
  1086   CAS MO (motor relay output)
  1087 
  1088   13 IN (~1200 baud clock input)
  1089 
  1090 ULA Socket
  1091 ----------
  1092 
  1093 The socket used for the ULA is a 3M/TexTool 268-5400 68-pin socket.
  1094 
  1095 References
  1096 ----------
  1097 
  1098 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw.htm
  1099 
  1100 About this Document
  1101 -------------------
  1102 
  1103 The most recent version of this document and accompanying distribution should
  1104 be available from the following location:
  1105 
  1106 http://hgweb.boddie.org.uk/ULA
  1107 
  1108 Copyright and licence information can be found in the docs directory of this
  1109 distribution - see docs/COPYING.txt for more information.