1 Timing
2 ------
3
4 According to the above (15.3.2 in the AUG), there are 312 scanlines, 256 of
5 which are used to generate pixel data. At 50Hz, this means that 128 cycles are
6 used to produce pixel data (2000000 cycles / 50 = 40000 cycles; 40000 cycles /
7 312 ~= 128 cycles). This is consistent with the observation that each scanline
8 requires at most 80 bytes of data, and that the ULA is apparently busy for 40
9 out of 64 microseconds in each scanline.
10
11 See: Acorn Electron Advanced User Guide
12 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
13
14 Access to RAM involves accessing four 64Kb dynamic RAM devices (IC4 to IC7,
15 each providing two bits of each byte) using two cycles within the 500ns period
16 of the 2MHz clock to complete each access operation. Since the CPU and ULA
17 have to take turns in accessing the RAM in MODE 4, 5 and 6, the CPU must
18 effectively run at 1MHz (since every other 500ns period involves the ULA
19 accessing RAM). The CPU is driven by an external clock (IC8) whose 16MHz
20 frequency is divided by the ULA (IC1) depending on the screen mode in use.
21
22 See: Acorn Electron Service Manual
23 http://acorn.chriswhy.co.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf
24
25 Each 16MHz cycle is approximately 62.5ns. To access the memory, the following
26 patterns corresponding to 16MHz cycles are required:
27
28 Time (ns): 0-------------- 500------------
29 2 MHz cycle: 0 1 ...
30 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
31 ~RAS: 0 1 0 1 ...
32 ~CAS: 0 1 0 1 0 1 0 1 ...
33 A B B A B B
34 F S F S
35
36 Here, "A" indicates the row and column addresses being latched into the RAM
37 (on a negative edge for ~RAS and ~CAS respectively), and "B" indicates the
38 second column address being latched into the RAM. Presumably, the first and
39 second half-bytes can be read at "F" and "S" respectively.
40
41 Note that the Service Manual refers to the negative edge of RAS and CAS, but
42 the datasheet for the similar TM4164EC4 product shows latching on the negative
43 edge of ~RAS and ~CAS. It is possible that the Service Manual also intended to
44 communicate the latter behaviour. In the TM4164EC4 datasheet, it appears that
45 "page mode" provides the appropriate behaviour for that particular product.
46
47 Shadow/Expanded Memory
48 ----------------------
49
50 The Electron exposes all sixteen address lines and all eight data lines
51 through the expansion bus. Using such lines, it is possible to provide
52 additional memory - typically sideways ROM and RAM - on expansion cards and
53 through cartridges, although the official cartridge specification provides
54 fewer address lines and only seeks to provide access to memory in 16K units.
55
56 Various modifications and upgrades were developed to offer "turbo"
57 capabilities to the Electron, permitting the CPU to access a separate 8K of
58 RAM at 2MHz, presumably preventing access to the low 8K of RAM accessible via
59 the ULA through additional logic. However, an enhanced ULA might support
60 independent CPU access to memory over the expansion bus by allowing itself to
61 be discharged from providing access to memory, potentially for a range of
62 addresses, and for the CPU to communicate with external memory uninterrupted.
63
64 Hardware Scrolling
65 ------------------
66
67 On the standard ULA, &FE02 and &FE03 map to a 9 significant bits address with
68 the least significant 5 bits being zero, thus limiting the scrolling
69 resolution to 64 bytes. An enhanced ULA could support a resolution of 2 bytes
70 using the same layout of these addresses.
71
72 |--&FE02--------------| |--&FE03--------------|
73 XX XX 14 13 12 11 10 09 08 07 06 XX XX XX XX XX
74
75 XX 14 13 12 11 10 09 08 07 06 05 04 03 02 01 XX
76
77 Arguably, a resolution of 8 bytes is more useful, since the mapping of screen
78 memory to pixel locations is character oriented. A change in 8 bytes would
79 permit a horizontal scrolling resolution of 2 pixels in MODE 2, 4 pixels in
80 MODE 1 and 5, and 8 pixels in MODE 0, 3 and 6. This resolution is actually
81 observed on the BBC Micro (see 18.11.2 in the BBC Microcomputer Advanced User
82 Guide).
83
84 One argument for a 2 byte resolution is smooth vertical scrolling. A pitfall
85 of changing the screen address by 2 bytes is the change in the number of lines
86 from the initial and final character rows that need reading by the ULA, which
87 would need to maintain this state information (although this is a relatively
88 trivial change). Another pitfall is the complication that might be introduced
89 to software writing bitmaps of character height to the screen.
90
91 Region Blanking
92 ---------------
93
94 The problem of permitting character-oriented blitting in programs whilst
95 scrolling the screen by sub-character amounts could be mitigated by permitting
96 a region of the display to be blank, such as the final lines of the display.
97 Consider the following vertical scrolling by 2 bytes that would cause an
98 initial character row of 6 lines and a final character row of 2 lines:
99
100 6 lines - initial, partial character row
101 248 lines - 31 complete rows
102 2 lines - final, partial character row
103
104 If a routine were in use that wrote 8 line bitmaps to the partial character
105 row now split in two, it would be advisable to hide one of the regions in
106 order to prevent content appearing in the wrong place on screen (such as
107 content meant to appear at the top "leaking" onto the bottom). Blanking 6
108 lines would be sufficient, as can be seen from the following cases.
109
110 Scrolling up by 2 lines:
111
112 6 lines - initial, partial character row
113 240 lines - 30 complete rows
114 4 lines - part of 1 complete row
115 -----------------------------------------------------------------
116 4 lines - part of 1 complete row (hidden to maintain 250 lines)
117 2 lines - final, partial character row (hidden)
118
119 Scrolling down by 2 lines:
120
121 2 lines - initial, partial character row
122 248 lines - 31 complete rows
123 ----------------------------------------------------------
124 6 lines - final, partial character row (hidden)
125
126 Thus, in this case, region blanking would impose a 250 line display with the
127 bottom 6 lines blank.
128
129 Screen Height Adjustment
130 ------------------------
131
132 The height of the screen could be configurable in order to reduce screen
133 memory consumption. This is not quite done in MODE 3 and 6 since the start of
134 the screen appears to be rounded down to the nearest page, but by reducing the
135 height by amounts more than a page, savings would be possible. For example:
136
137 Screen width Depth Height Bytes per line Saving in bytes Start address
138 ------------ ----- ------ -------------- --------------- -------------
139 640 1 252 80 320 &3140 -> &3100
140 640 1 248 80 640 &3280 -> &3200
141 320 1 240 40 640 &5A80 -> &5A00
142 320 2 240 80 1280 &3500
143
144 Palette Definition
145 ------------------
146
147 Since all memory accesses go via the ULA, an enhanced ULA could employ more
148 specific addresses than &FE*X to perform enhanced functions. For example, the
149 palette control is done using &FE*8-F and merely involves selecting predefined
150 colours, whereas an enhanced ULA could support the redefinition of all 16
151 colours using specific ranges such as &FE18-F (colours 0 to 7) and &FE28-F
152 (colours 8 to 15), where a single byte might provide 8 bits per pixel colour
153 specifications similar to those used on the Archimedes.
154
155 The principal limitation here is actually the hardware: the Electron has only
156 a single output line for each of the red, green and blue channels, and if
157 those outputs are strictly digital and can only be set to a "high" and "low"
158 value, then only the existing eight colours are possible. If a modern ULA were
159 able to output analogue values, it would still need to be assessed whether the
160 circuitry could successfully handle and propagate such values.
161
162 Palette Definition Lists
163 ------------------------
164
165 It can be useful to redefine the palette in order to change the colours
166 available for a particular region of the screen, particularly in modes where
167 the choice of colours is constrained, and if an increased colour depth were
168 available, palette redefinition would be useful to give the illusion of more
169 than 16 colours in MODE 2. Traditionally, palette redefinition has been done
170 by using interrupt-driven timers, but a more efficient approach would involve
171 presenting lists of palette definitions to the ULA so that it can change the
172 palette at a particular display line.
173
174 One might define a palette redefinition list in a region of memory and then
175 communicate its contents to the ULA by writing the address and length of the
176 list, along with the display line at which the palette is to be changed, to
177 ULA registers such that the ULA buffers the list and performs the redefinition
178 at the appropriate time. Throughput/bandwidth considerations might impose
179 restrictions on the practical length of such a list, however.
180
181 Palette-Free Modes
182 ------------------
183
184 Palette-free modes might be defined where bit values directly correspond to
185 the red, green and blue channels, although this would mostly make sense only
186 for modes with depths greater than the standard 4 bits per pixel, and such
187 modes would require more memory than MODE 2 if they were to have an acceptable
188 resolution.
189
190 Display Suspend
191 ---------------
192
193 Especially when writing to the screen memory, it could be beneficial to be
194 able to suspend the ULA's access to the memory, instead producing blank values
195 for all screen pixels until a program is ready to reveal the screen. This is
196 different from palette blanking since with a blank palette, the ULA is still
197 reading screen memory and translating its contents into pixel values that end
198 up being blank.
199
200 This function is reminiscent of a capability of the ZX81, albeit necessary on
201 that hardware to reduce the load on the system CPU which was responsible for
202 producing the video output.
203
204 Hardware Sprites
205 ----------------
206
207 An enhanced ULA might provide hardware sprites, but this would be done in an
208 way that is incompatible with the standard ULA, since no &FE*X locations are
209 available for allocation. To keep the facility simple, hardware sprites would
210 have a standard byte width and height.
211
212 The specification of sprites could involve the reservation of 16 locations
213 (for example, &FE20-F) specifying a fixed number of eight sprites, with each
214 location pair referring to the sprite data. By limiting the ULA to dealing
215 with a fixed number of sprites, the work required inside the ULA would be
216 reduced since it would avoid having to deal with arbitrary numbers of sprites.
217
218 The principal limitation on providing hardware sprites is that of having to
219 obtain sprite data, given that the ULA is usually required to retrieve screen
220 data, and given the lack of memory bandwidth available to retrieve sprite data
221 (particularly from multiple sprites supposedly at the same position) and
222 screen data simultaneously. Although the ULA could potentially read sprite
223 data and screen data in alternate memory accesses in screen modes where the
224 bandwidth is not already fully utilised, this would result in a degradation of
225 performance.
226
227 Additional Screen Mode Configurations
228 -------------------------------------
229
230 Alternative screen mode configurations could be supported. The ULA has to
231 produce 640 pixel values across the screen, with pixel doubling or quadrupling
232 employed to fill the screen width:
233
234 Screen width Columns Scaling Depth Bytes
235 ------------ ------- ------- ----- -----
236 640 80 x1 1 80
237 320 40 x2 1, 2 40, 80
238 160 20 x4 2, 4 40, 80
239
240 It must also use at most 80 byte-sized memory accesses to provide the
241 information for the display. Given that characters must occupy an 8x8 pixel
242 array, if a configuration featuring anything other than 20, 40 or 80 character
243 columns is to be supported, compromises must be made such as the introduction
244 of blank pixels either between characters (such as occurs between rows in MODE
245 3 and 6) or at the end of a scanline (such as occurs at the end of the frame
246 in MODE 3 and 6). Consider the following configuration:
247
248 Screen width Columns Scaling Depth Bytes Blank
249 ------------ ------- ------- ----- ------ -----
250 208 26 x3 1, 2 26, 52 16
251
252 Here, if the ULA can triple pixels, a 26 column mode with either 2 or 4
253 colours could be provided, with 16 blank pixel values (out of a total of 640)
254 generated either at the start or end (or split between the start and end) of
255 each scanline.
256
257 Character Attributes
258 --------------------
259
260 The BBC Micro MODE 7 employs something resembling character attributes to
261 support teletext displays, but depends on circuitry providing a character
262 generator. The ZX Spectrum, on the other hand, provides character attributes
263 as a means of colouring bitmapped graphics. Although such a feature is very
264 limiting as the sole means of providing multicolour graphics, in situations
265 where the choice is between low resolution multicolour graphics or high
266 resolution monochrome graphics, character attributes provide a potentially
267 useful compromise.
268
269 For each byte read, the ULA must deliver 8 pixel values (out of a total of
270 640) to the video output, doing so by either emptying its pixel buffer on a
271 pixel per cycle basis, or by multiplying pixels and thus holding them for more
272 than one cycle. For example for a screen mode having 640 pixels in width:
273
274 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
275 Reads: B B
276 Pixels: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
277
278 And for a screen mode having 320 pixels in width:
279
280 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
281 Reads: B
282 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
283
284 However, in modes where less than 80 bytes are required to generate the pixel
285 values, an enhanced ULA might be able to read additional bytes between those
286 providing the bitmapped graphics data:
287
288 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
289 Reads: B A
290 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
291
292 These additional bytes could provide colour information for the bitmapped data
293 in the following character column (of 8 pixels). Since it would be desirable
294 to apply attribute data to the first column, the initial 8 cycles might be
295 configured to not produce pixel values.
296
297 For an entire character, attribute data need only be read for the first row of
298 pixels for a character. The subsequent rows would have attribute information
299 applied to them, although this would require the attribute data to be stored
300 in some kind of buffer. Thus, the following access pattern would be observed:
301
302 Cycle: A B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ...
303
304 A whole byte used for colour information for a whole character would result in
305 a choice of 256 colours, and this might be somewhat excessive. By only reading
306 attribute bytes at every other opportunity, a choice of 16 colours could be
307 applied individually to two characters.
308
309 Cycle: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
310 Reads: B A B -
311 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
312
313 Further reductions in attribute data access, offering 4 colours for every
314 character in a four character block, for example, might also be worth
315 considering.
316
317 Consider the following configurations for screen modes with a colour depth of
318 1 bit per pixel for bitmap information:
319
320 Screen width Columns Scaling Bytes (B) Bytes (A) Colours Screen start
321 ------------ ------- ------- --------- --------- ------- ------------
322 320 40 x2 40 40 256 &5300
323 320 40 x2 40 20 16 &5580 -> &5500
324 320 40 x2 40 10 4 &56C0 -> &5600
325 208 26 x3 26 26 256 &62C0 -> &6200
326 208 26 x3 26 13 16 &6460 -> &6400
327
328 MODE 7 Emulation using Character Attributes
329 -------------------------------------------
330
331 If the scheme of applying attributes to character regions were employed to
332 emulate MODE 7, in conjunction with the MODE 6 display technique, the
333 following configuration would be required:
334
335 Screen width Columns Rows Bytes (B) Bytes (A) Colours Screen start
336 ------------ ------- ---- --------- --------- ------- ------------
337 320 40 25 40 20 16 &5ECC -> &5E00
338 320 40 25 40 10 4 &5FC6 -> &5F00
339
340 Although this requires much more memory than MODE 7 (8500 bytes versus MODE
341 7's 1000 bytes), it does not need much more memory than MODE 6, and it would
342 at least make a limited 40-column multicolour mode available as a substitute
343 for MODE 7.
344
345 Enhanced Graphics and Mode Layouts
346 ----------------------------------
347
348 Screen modes with different screen memory mappings, higher resolutions and
349 larger colour depths might be possible, but this would in most cases involve
350 the allocation of more screen memory, and the ULA would probably then be
351 obliged to page in such memory for the CPU to be able to sensibly access it
352 all. Merely changing the memory mappings in order to have Archimedes-style
353 row-oriented screen addresses (instead of character-oriented addresses) could
354 be done for the existing modes, but this might not be sufficiently beneficial,
355 especially since accessing regions of the screen would involve incrementing
356 pointers by amounts that are inconvenient on an 8-bit CPU.
357
358 Enhanced Sound
359 --------------
360
361 The standard ULA reserves &FE*6 for sound generation and cassette
362 input/output, thus making it impossible to support multiple channels within
363 the given framework. The BBC Micro ULA employs &FE40-&FE4F for sound control,
364 and an enhanced ULA could adopt this interface.
365
366 The BBC Micro uses the SN76489 chip to produce sound, and the entire
367 functionality of this chip could be emulated for enhanced sound, with a subset
368 of the functionality exposed via the &FE*6 interface.
369
370 See: http://en.wikipedia.org/wiki/Texas_Instruments_SN76489
371
372 Waveform Upload
373 ---------------
374
375 As with a hardware sprite function, waveforms could be uploaded or referenced
376 using locations as registers referencing memory regions.
377
378 BBC ULA Compatibility
379 ---------------------
380
381 Although some new ULA functions could be defined in a way that is also
382 compatible with the BBC Micro, the BBC ULA is itself incompatible with the
383 Electron ULA: &FE00-7 is reserved for the video controller in the BBC memory
384 map, but controls various functions specific to the 6845 video controller;
385 &FE08-F is reserved for the serial controller. It therefore becomes possible
386 to disregard compatibility where compatibility is already disregarded for a
387 particular area of functionality.
388
389 &FE20-F maps to video ULA functionality on the BBC Micro which provides
390 control over the palette (using address &FE21, compared to &FE07-F on the
391 Electron) and other system-specific functions. Since the location usage is
392 generally incompatible, this region could be reused for other purposes.
393
394 ULA Pin Functions
395 -----------------
396
397 The functions of the ULA pins are described in the Electron Service Manual. Of
398 interest to video processing are the following:
399
400 CSYNC (low during horizontal or vertical synchronisation periods, high
401 otherwise)
402
403 HS (low during horizontal synchronisation periods, high otherwise)
404
405 RED, GREEN, BLUE (pixel colour outputs)
406
407 CLOCK IN (a 16MHz clock input, 4V peak to peak)
408
409 PHI OUT (a 1MHz, 2MHz and stopped clock signal for the CPU)
410
411 More general memory access pins:
412
413 RAM0...RAM3 (data lines to/from the RAM)
414
415 RA0...RA7 (address lines for sending both row and column addresses to the RAM)
416
417 RAS (row address strobe setting the row address on a negative edge - see the
418 timing notes)
419
420 CAS (column address strobe setting the column address on a negative edge -
421 see the timing notes)
422
423 WE (sets write enable with logic 0, read with logic 1)
424
425 ROM (select data access from ROM)
426
427 CPU-oriented memory access pins:
428
429 A0...A15 (CPU address lines)
430
431 PD0...PD7 (CPU data lines)
432
433 R/W (indicates CPU write with logic 0, CPU read with logic 1)
434
435 Interrupt-related pins:
436
437 NMI (CPU request for uninterrupted 1MHz access to memory)
438
439 IRQ (signal event to CPU)
440
441 POR (power-on reset, resetting the ULA on a positive edge and asserting the
442 CPU's RST pin)
443
444 RST (master reset for the CPU signalled on power-up and by the Break key)
445
446 Keyboard-related pins:
447
448 KBD0...KBD3 (keyboard inputs)
449
450 CAPS LOCK (control status LED)
451
452 Sound-related pins:
453
454 SOUND O/P (sound output using internal oscillator)
455
456 Cassette-related pins:
457
458 CAS IN (cassette circuit input, between 0.5V to 2V peak to peak)
459
460 CAS OUT (pseudo-sinusoidal output, 1.8V peak to peak)
461
462 CAS RC (detect high tone)
463
464 CAS MO (motor relay output)
465
466 ÷13 IN (~1200 baud clock input)