1 Timing
2 ------
3
4 According to 15.3.2 in the Advanced User Guide, there are 312 scanlines, 256
5 of which are used to generate pixel data. At 50Hz, this means that 128 cycles
6 are spent on each scanline (2000000 cycles / 50 = 40000 cycles; 40000 cycles /
7 312 ~= 128 cycles). This is consistent with the observation that each scanline
8 requires at most 80 bytes of data, and that the ULA is apparently busy for 40
9 out of 64 microseconds in each scanline.
10
11 Access to RAM involves accessing four 64Kb dynamic RAM devices (IC4 to IC7,
12 each providing two bits of each byte) using two cycles within the 500ns period
13 of the 2MHz clock to complete each access operation. Since the CPU and ULA
14 have to take turns in accessing the RAM in MODE 4, 5 and 6, the CPU must
15 effectively run at 1MHz (since every other 500ns period involves the ULA
16 accessing RAM). The CPU is driven by an external clock (IC8) whose 16MHz
17 frequency is divided by the ULA (IC1) depending on the screen mode in use.
18
19 Each 16MHz cycle is approximately 62.5ns. To access the memory, the following
20 patterns corresponding to 16MHz cycles are required:
21
22 Time (ns): 0-------------- 500------------ ...
23 2 MHz cycle: 0 1 ...
24 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
25 ~RAS: 0 1 0 1 ...
26 ~CAS: 0 1 0 1 0 1 0 1 ...
27 A B B A B B ...
28 F S F S ...
29 a b b a b b ...
30
31 Here, "A" indicates the row and column addresses being latched into the RAM
32 (on a negative edge for ~RAS and ~CAS respectively), and "B" indicates the
33 second column address being latched into the RAM. Presumably, the first and
34 second half-bytes can be read at "F" and "S" respectively, and the row and
35 column addresses must be made available at "a" and "b" respectively at the
36 latest.
37
38 Note that the Service Manual refers to the negative edge of RAS and CAS, but
39 the datasheet for the similar TM4164EC4 product shows latching on the negative
40 edge of ~RAS and ~CAS. It is possible that the Service Manual also intended to
41 communicate the latter behaviour. In the TM4164EC4 datasheet, it appears that
42 "page mode" provides the appropriate behaviour for that particular product.
43
44 Video Timing
45 ------------
46
47 According to 8.7 in the Service Manual, and the PAL Wikipedia page,
48 approximately 4.7µs is used for the sync pulse, 5.7µs for the "back porch"
49 (including the "colour burst"), and 1.65µs for the "front porch", totalling
50 12.05µs and thus leaving 51.95µs for the active video signal for each
51 scanline. As the Service Manual suggests in the oscilloscope traces, the
52 display information is transmitted more or less centred within the active
53 video period since the ULA will only be providing pixel data for 40µs in each
54 scanline.
55
56 Each 62.5ns cycle happens to correspond to 64µs divided by 1024, meaning that
57 each scanline can be divided into 1024 cycles, although only 640 at most are
58 actively used to provide pixel data. Pixel data production should only occur
59 within a certain period on each scanline, approximately 262 cycles after the
60 start of hsync:
61
62 active video period = 51.95µs
63 pixel data period = 40µs
64 total silent period = 51.95µs - 40µs = 11.95µs
65 silent periods (before and after) = 11.95µs / 2 = 5.975µs
66 hsync and back porch period = 4.7µs + 5.7µs = 10.4µs
67 time before pixel data period = 10.4µs + 5.975µs = 16.375µs
68 pixel data period start cycle = 16.375µs / 62.5ns = 262
69
70 By choosing a number divisible by 8, the RAM access mechanism can be
71 synchronised with the pixel production. Thus, 264 is a more appropriate start
72 cycle.
73
74 The "vertical blanking period", meaning the period before picture information
75 in each field is 25 lines out of 312 (strictly 312.5) and thus lasts for
76 1.6ms. Of this, 2.5 lines occur before the vsync (field sync) which also lasts
77 for 2.5 lines. Thus, the first visible scanline on the first field of a frame
78 occurs half way through the 23rd scanline period measured from the start of
79 vsync:
80
81 10 20 23
82 Line in frame: 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8
83 Line from 1: 0 22 3
84 Line on screen: .:::::VVVVV::::: 12233445566
85 |_________________________________________________|
86 25 line vertical blanking period
87
88 In the second field of a frame, the first visible scanline coincides with the
89 24th scanline period measured from the start of line 313 in the frame:
90
91 310 336
92 Line in frame: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
93 Line from 313: 0 23
94 Line on screen: 88:::::VVVVV:::: 11223344
95 288 | |
96 |_________________________________________________|
97 25 line vertical blanking period
98
99 In order to consider only full lines, we might consider the start of each
100 frame to occur 23 lines after the start of vsync.
101
102 Again, it is likely that pixel data production should only occur on scanlines
103 within a certain period on each frame. The "625/50" document indicates that
104 only a certain region is "safe" to use, suggesting a vertically centred region
105 with approximately 15 blank lines above and below the picture. Thus, the start
106 of the picture could be chosen as 38 lines after the start of vsync.
107
108 See: Acorn Electron Advanced User Guide
109 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
110 See: http://en.wikipedia.org/wiki/PAL
111 See: http://en.wikipedia.org/wiki/Analog_television#Structure_of_a_video_signal
112 See: The 625/50 PAL Video Signal and TV Compatible Graphics Modes
113 http://lipas.uwasa.fi/~f76998/video/modes/
114 See: PAL TV timing and voltages
115 http://www.retroleum.co.uk/electronics-articles/pal-tv-timing-and-voltages/
116 See: Line Standards
117 http://www.pembers.freeserve.co.uk/World-TV-Standards/Line-Standards.html
118 See: TM4164EC4 65,536 by 4-Bit Dynamic RAM Module
119 http://www.datasheetarchive.com/dl/Datasheets-112/DSAP0051030.pdf
120 See: Acorn Electron Service Manual
121 http://acorn.chriswhy.co.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf
122
123 Shadow/Expanded Memory
124 ----------------------
125
126 The Electron exposes all sixteen address lines and all eight data lines
127 through the expansion bus. Using such lines, it is possible to provide
128 additional memory - typically sideways ROM and RAM - on expansion cards and
129 through cartridges, although the official cartridge specification provides
130 fewer address lines and only seeks to provide access to memory in 16K units.
131
132 Various modifications and upgrades were developed to offer "turbo"
133 capabilities to the Electron, permitting the CPU to access a separate 8K of
134 RAM at 2MHz, presumably preventing access to the low 8K of RAM accessible via
135 the ULA through additional logic. However, an enhanced ULA might support
136 independent CPU access to memory over the expansion bus by allowing itself to
137 be discharged from providing access to memory, potentially for a range of
138 addresses, and for the CPU to communicate with external memory uninterrupted.
139
140 Hardware Scrolling
141 ------------------
142
143 On the standard ULA, &FE02 and &FE03 map to a 9 significant bits address with
144 the least significant 5 bits being zero, thus limiting the scrolling
145 resolution to 64 bytes. An enhanced ULA could support a resolution of 2 bytes
146 using the same layout of these addresses.
147
148 |--&FE02--------------| |--&FE03--------------|
149 XX XX 14 13 12 11 10 09 08 07 06 XX XX XX XX XX
150
151 XX 14 13 12 11 10 09 08 07 06 05 04 03 02 01 XX
152
153 Arguably, a resolution of 8 bytes is more useful, since the mapping of screen
154 memory to pixel locations is character oriented. A change in 8 bytes would
155 permit a horizontal scrolling resolution of 2 pixels in MODE 2, 4 pixels in
156 MODE 1 and 5, and 8 pixels in MODE 0, 3 and 6. This resolution is actually
157 observed on the BBC Micro (see 18.11.2 in the BBC Microcomputer Advanced User
158 Guide).
159
160 One argument for a 2 byte resolution is smooth vertical scrolling. A pitfall
161 of changing the screen address by 2 bytes is the change in the number of lines
162 from the initial and final character rows that need reading by the ULA, which
163 would need to maintain this state information (although this is a relatively
164 trivial change). Another pitfall is the complication that might be introduced
165 to software writing bitmaps of character height to the screen.
166
167 Region Blanking
168 ---------------
169
170 The problem of permitting character-oriented blitting in programs whilst
171 scrolling the screen by sub-character amounts could be mitigated by permitting
172 a region of the display to be blank, such as the final lines of the display.
173 Consider the following vertical scrolling by 2 bytes that would cause an
174 initial character row of 6 lines and a final character row of 2 lines:
175
176 6 lines - initial, partial character row
177 248 lines - 31 complete rows
178 2 lines - final, partial character row
179
180 If a routine were in use that wrote 8 line bitmaps to the partial character
181 row now split in two, it would be advisable to hide one of the regions in
182 order to prevent content appearing in the wrong place on screen (such as
183 content meant to appear at the top "leaking" onto the bottom). Blanking 6
184 lines would be sufficient, as can be seen from the following cases.
185
186 Scrolling up by 2 lines:
187
188 6 lines - initial, partial character row
189 240 lines - 30 complete rows
190 4 lines - part of 1 complete row
191 -----------------------------------------------------------------
192 4 lines - part of 1 complete row (hidden to maintain 250 lines)
193 2 lines - final, partial character row (hidden)
194
195 Scrolling down by 2 lines:
196
197 2 lines - initial, partial character row
198 248 lines - 31 complete rows
199 ----------------------------------------------------------
200 6 lines - final, partial character row (hidden)
201
202 Thus, in this case, region blanking would impose a 250 line display with the
203 bottom 6 lines blank.
204
205 Screen Height Adjustment
206 ------------------------
207
208 The height of the screen could be configurable in order to reduce screen
209 memory consumption. This is not quite done in MODE 3 and 6 since the start of
210 the screen appears to be rounded down to the nearest page, but by reducing the
211 height by amounts more than a page, savings would be possible. For example:
212
213 Screen width Depth Height Bytes per line Saving in bytes Start address
214 ------------ ----- ------ -------------- --------------- -------------
215 640 1 252 80 320 &3140 -> &3100
216 640 1 248 80 640 &3280 -> &3200
217 320 1 240 40 640 &5A80 -> &5A00
218 320 2 240 80 1280 &3500
219
220 Palette Definition
221 ------------------
222
223 Since all memory accesses go via the ULA, an enhanced ULA could employ more
224 specific addresses than &FE*X to perform enhanced functions. For example, the
225 palette control is done using &FE*8-F and merely involves selecting predefined
226 colours, whereas an enhanced ULA could support the redefinition of all 16
227 colours using specific ranges such as &FE18-F (colours 0 to 7) and &FE28-F
228 (colours 8 to 15), where a single byte might provide 8 bits per pixel colour
229 specifications similar to those used on the Archimedes.
230
231 The principal limitation here is actually the hardware: the Electron has only
232 a single output line for each of the red, green and blue channels, and if
233 those outputs are strictly digital and can only be set to a "high" and "low"
234 value, then only the existing eight colours are possible. If a modern ULA were
235 able to output analogue values, it would still need to be assessed whether the
236 circuitry could successfully handle and propagate such values.
237
238 Palette Definition Lists
239 ------------------------
240
241 It can be useful to redefine the palette in order to change the colours
242 available for a particular region of the screen, particularly in modes where
243 the choice of colours is constrained, and if an increased colour depth were
244 available, palette redefinition would be useful to give the illusion of more
245 than 16 colours in MODE 2. Traditionally, palette redefinition has been done
246 by using interrupt-driven timers, but a more efficient approach would involve
247 presenting lists of palette definitions to the ULA so that it can change the
248 palette at a particular display line.
249
250 One might define a palette redefinition list in a region of memory and then
251 communicate its contents to the ULA by writing the address and length of the
252 list, along with the display line at which the palette is to be changed, to
253 ULA registers such that the ULA buffers the list and performs the redefinition
254 at the appropriate time. Throughput/bandwidth considerations might impose
255 restrictions on the practical length of such a list, however.
256
257 Palette-Free Modes
258 ------------------
259
260 Palette-free modes might be defined where bit values directly correspond to
261 the red, green and blue channels, although this would mostly make sense only
262 for modes with depths greater than the standard 4 bits per pixel, and such
263 modes would require more memory than MODE 2 if they were to have an acceptable
264 resolution.
265
266 Display Suspend
267 ---------------
268
269 Especially when writing to the screen memory, it could be beneficial to be
270 able to suspend the ULA's access to the memory, instead producing blank values
271 for all screen pixels until a program is ready to reveal the screen. This is
272 different from palette blanking since with a blank palette, the ULA is still
273 reading screen memory and translating its contents into pixel values that end
274 up being blank.
275
276 This function is reminiscent of a capability of the ZX81, albeit necessary on
277 that hardware to reduce the load on the system CPU which was responsible for
278 producing the video output.
279
280 Hardware Sprites
281 ----------------
282
283 An enhanced ULA might provide hardware sprites, but this would be done in an
284 way that is incompatible with the standard ULA, since no &FE*X locations are
285 available for allocation. To keep the facility simple, hardware sprites would
286 have a standard byte width and height.
287
288 The specification of sprites could involve the reservation of 16 locations
289 (for example, &FE20-F) specifying a fixed number of eight sprites, with each
290 location pair referring to the sprite data. By limiting the ULA to dealing
291 with a fixed number of sprites, the work required inside the ULA would be
292 reduced since it would avoid having to deal with arbitrary numbers of sprites.
293
294 The principal limitation on providing hardware sprites is that of having to
295 obtain sprite data, given that the ULA is usually required to retrieve screen
296 data, and given the lack of memory bandwidth available to retrieve sprite data
297 (particularly from multiple sprites supposedly at the same position) and
298 screen data simultaneously. Although the ULA could potentially read sprite
299 data and screen data in alternate memory accesses in screen modes where the
300 bandwidth is not already fully utilised, this would result in a degradation of
301 performance.
302
303 Additional Screen Mode Configurations
304 -------------------------------------
305
306 Alternative screen mode configurations could be supported. The ULA has to
307 produce 640 pixel values across the screen, with pixel doubling or quadrupling
308 employed to fill the screen width:
309
310 Screen width Columns Scaling Depth Bytes
311 ------------ ------- ------- ----- -----
312 640 80 x1 1 80
313 320 40 x2 1, 2 40, 80
314 160 20 x4 2, 4 40, 80
315
316 It must also use at most 80 byte-sized memory accesses to provide the
317 information for the display. Given that characters must occupy an 8x8 pixel
318 array, if a configuration featuring anything other than 20, 40 or 80 character
319 columns is to be supported, compromises must be made such as the introduction
320 of blank pixels either between characters (such as occurs between rows in MODE
321 3 and 6) or at the end of a scanline (such as occurs at the end of the frame
322 in MODE 3 and 6). Consider the following configuration:
323
324 Screen width Columns Scaling Depth Bytes Blank
325 ------------ ------- ------- ----- ------ -----
326 208 26 x3 1, 2 26, 52 16
327
328 Here, if the ULA can triple pixels, a 26 column mode with either 2 or 4
329 colours could be provided, with 16 blank pixel values (out of a total of 640)
330 generated either at the start or end (or split between the start and end) of
331 each scanline.
332
333 Character Attributes
334 --------------------
335
336 The BBC Micro MODE 7 employs something resembling character attributes to
337 support teletext displays, but depends on circuitry providing a character
338 generator. The ZX Spectrum, on the other hand, provides character attributes
339 as a means of colouring bitmapped graphics. Although such a feature is very
340 limiting as the sole means of providing multicolour graphics, in situations
341 where the choice is between low resolution multicolour graphics or high
342 resolution monochrome graphics, character attributes provide a potentially
343 useful compromise.
344
345 For each byte read, the ULA must deliver 8 pixel values (out of a total of
346 640) to the video output, doing so by either emptying its pixel buffer on a
347 pixel per cycle basis, or by multiplying pixels and thus holding them for more
348 than one cycle. For example for a screen mode having 640 pixels in width:
349
350 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
351 Reads: B B
352 Pixels: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
353
354 And for a screen mode having 320 pixels in width:
355
356 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
357 Reads: B
358 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
359
360 However, in modes where less than 80 bytes are required to generate the pixel
361 values, an enhanced ULA might be able to read additional bytes between those
362 providing the bitmapped graphics data:
363
364 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
365 Reads: B A
366 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
367
368 These additional bytes could provide colour information for the bitmapped data
369 in the following character column (of 8 pixels). Since it would be desirable
370 to apply attribute data to the first column, the initial 8 cycles might be
371 configured to not produce pixel values.
372
373 For an entire character, attribute data need only be read for the first row of
374 pixels for a character. The subsequent rows would have attribute information
375 applied to them, although this would require the attribute data to be stored
376 in some kind of buffer. Thus, the following access pattern would be observed:
377
378 Cycle: A B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ...
379
380 A whole byte used for colour information for a whole character would result in
381 a choice of 256 colours, and this might be somewhat excessive. By only reading
382 attribute bytes at every other opportunity, a choice of 16 colours could be
383 applied individually to two characters.
384
385 Cycle: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
386 Reads: B A B -
387 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
388
389 Further reductions in attribute data access, offering 4 colours for every
390 character in a four character block, for example, might also be worth
391 considering.
392
393 Consider the following configurations for screen modes with a colour depth of
394 1 bit per pixel for bitmap information:
395
396 Screen width Columns Scaling Bytes (B) Bytes (A) Colours Screen start
397 ------------ ------- ------- --------- --------- ------- ------------
398 320 40 x2 40 40 256 &5300
399 320 40 x2 40 20 16 &5580 -> &5500
400 320 40 x2 40 10 4 &56C0 -> &5600
401 208 26 x3 26 26 256 &62C0 -> &6200
402 208 26 x3 26 13 16 &6460 -> &6400
403
404 MODE 7 Emulation using Character Attributes
405 -------------------------------------------
406
407 If the scheme of applying attributes to character regions were employed to
408 emulate MODE 7, in conjunction with the MODE 6 display technique, the
409 following configuration would be required:
410
411 Screen width Columns Rows Bytes (B) Bytes (A) Colours Screen start
412 ------------ ------- ---- --------- --------- ------- ------------
413 320 40 25 40 20 16 &5ECC -> &5E00
414 320 40 25 40 10 4 &5FC6 -> &5F00
415
416 Although this requires much more memory than MODE 7 (8500 bytes versus MODE
417 7's 1000 bytes), it does not need much more memory than MODE 6, and it would
418 at least make a limited 40-column multicolour mode available as a substitute
419 for MODE 7.
420
421 Enhanced Graphics and Mode Layouts
422 ----------------------------------
423
424 Screen modes with different screen memory mappings, higher resolutions and
425 larger colour depths might be possible, but this would in most cases involve
426 the allocation of more screen memory, and the ULA would probably then be
427 obliged to page in such memory for the CPU to be able to sensibly access it
428 all. Merely changing the memory mappings in order to have Archimedes-style
429 row-oriented screen addresses (instead of character-oriented addresses) could
430 be done for the existing modes, but this might not be sufficiently beneficial,
431 especially since accessing regions of the screen would involve incrementing
432 pointers by amounts that are inconvenient on an 8-bit CPU.
433
434 Enhanced Sound
435 --------------
436
437 The standard ULA reserves &FE*6 for sound generation and cassette
438 input/output, thus making it impossible to support multiple channels within
439 the given framework. The BBC Micro ULA employs &FE40-&FE4F for sound control,
440 and an enhanced ULA could adopt this interface.
441
442 The BBC Micro uses the SN76489 chip to produce sound, and the entire
443 functionality of this chip could be emulated for enhanced sound, with a subset
444 of the functionality exposed via the &FE*6 interface.
445
446 See: http://en.wikipedia.org/wiki/Texas_Instruments_SN76489
447
448 Waveform Upload
449 ---------------
450
451 As with a hardware sprite function, waveforms could be uploaded or referenced
452 using locations as registers referencing memory regions.
453
454 BBC ULA Compatibility
455 ---------------------
456
457 Although some new ULA functions could be defined in a way that is also
458 compatible with the BBC Micro, the BBC ULA is itself incompatible with the
459 Electron ULA: &FE00-7 is reserved for the video controller in the BBC memory
460 map, but controls various functions specific to the 6845 video controller;
461 &FE08-F is reserved for the serial controller. It therefore becomes possible
462 to disregard compatibility where compatibility is already disregarded for a
463 particular area of functionality.
464
465 &FE20-F maps to video ULA functionality on the BBC Micro which provides
466 control over the palette (using address &FE21, compared to &FE07-F on the
467 Electron) and other system-specific functions. Since the location usage is
468 generally incompatible, this region could be reused for other purposes.
469
470 ULA Pin Functions
471 -----------------
472
473 The functions of the ULA pins are described in the Electron Service Manual. Of
474 interest to video processing are the following:
475
476 CSYNC (low during horizontal or vertical synchronisation periods, high
477 otherwise)
478
479 HS (low during horizontal synchronisation periods, high otherwise)
480
481 RED, GREEN, BLUE (pixel colour outputs)
482
483 CLOCK IN (a 16MHz clock input, 4V peak to peak)
484
485 PHI OUT (a 1MHz, 2MHz and stopped clock signal for the CPU)
486
487 More general memory access pins:
488
489 RAM0...RAM3 (data lines to/from the RAM)
490
491 RA0...RA7 (address lines for sending both row and column addresses to the RAM)
492
493 RAS (row address strobe setting the row address on a negative edge - see the
494 timing notes)
495
496 CAS (column address strobe setting the column address on a negative edge -
497 see the timing notes)
498
499 WE (sets write enable with logic 0, read with logic 1)
500
501 ROM (select data access from ROM)
502
503 CPU-oriented memory access pins:
504
505 A0...A15 (CPU address lines)
506
507 PD0...PD7 (CPU data lines)
508
509 R/W (indicates CPU write with logic 0, CPU read with logic 1)
510
511 Interrupt-related pins:
512
513 NMI (CPU request for uninterrupted 1MHz access to memory)
514
515 IRQ (signal event to CPU)
516
517 POR (power-on reset, resetting the ULA on a positive edge and asserting the
518 CPU's RST pin)
519
520 RST (master reset for the CPU signalled on power-up and by the Break key)
521
522 Keyboard-related pins:
523
524 KBD0...KBD3 (keyboard inputs)
525
526 CAPS LOCK (control status LED)
527
528 Sound-related pins:
529
530 SOUND O/P (sound output using internal oscillator)
531
532 Cassette-related pins:
533
534 CAS IN (cassette circuit input, between 0.5V to 2V peak to peak)
535
536 CAS OUT (pseudo-sinusoidal output, 1.8V peak to peak)
537
538 CAS RC (detect high tone)
539
540 CAS MO (motor relay output)
541
542 ÷13 IN (~1200 baud clock input)