1 The Acorn Electron ULA
2 ======================
3
4 Principal Design and Feature Constraints
5 ----------------------------------------
6
7 The features of the ULA are limited in sophistication by the amount of time
8 and resources that can be allocated to each activity supporting the
9 fundamental features and obligations of the unit. Maintaining a screen display
10 based on the contents of RAM itself requires the ULA to have exclusive access
11 to various hardware resources for a significant period of time.
12
13 Whilst other elements of the ULA can in principle run in parallel with the
14 display refresh activity, they cannot also access the RAM at the same time.
15 Consequently, other features that might use the RAM must accept a reduced
16 allocation of that resource in comparison to a hypothetical architecture where
17 concurrent RAM access is possible at all times.
18
19 Thus, the principal constraint for many features is bandwidth. The duration of
20 access to hardware resources is one aspect of this; the rate at which such
21 resources can be accessed is another. For example, the RAM is not fast enough
22 to support access more frequently than one byte per 2MHz cycle, and for screen
23 modes involving 80 bytes of screen data per scanline, there are no free cycles
24 for anything other than the production of pixel output during the active
25 scanline periods.
26
27 Another constraint is imposed by the method of RAM access provided by the ULA.
28 The ULA is able to access RAM by fetching 4 bits at a time and thus managing
29 to transfer 8 bits within a single 2MHz cycle, this being sufficient to
30 provide display data for the most demanding screen modes. However, this
31 mechanism's timing requirements are beyond the capabilities of the CPU when
32 running at 2MHz.
33
34 Consequently, the CPU will only ever be able to access RAM via the ULA at
35 1MHz, even when the ULA is not accessing the RAM. Fortunately, when needing to
36 refresh the display, the ULA is still able to make use of the idle part of
37 each 1MHz cycle (or, rather, the idle 2MHz cycle unused by the CPU) to itself
38 access the RAM at a rate of 1 byte per 1MHz cycle (or 1 byte every other 2MHz
39 cycle), thus supporting the less demanding screen modes.
40
41 Timing
42 ------
43
44 According to 15.3.2 in the Advanced User Guide, there are 312 scanlines, 256
45 of which are used to generate pixel data. At 50Hz, this means that 128 cycles
46 are spent on each scanline (2000000 cycles / 50 = 40000 cycles; 40000 cycles /
47 312 ~= 128 cycles). This is consistent with the observation that each scanline
48 requires at most 80 bytes of data, and that the ULA is apparently busy for 40
49 out of 64 microseconds in each scanline.
50
51 (In fact, since the ULA is seeking to provide an image for an interlaced
52 625-line display, there are in fact two "fields" involved, one providing 312
53 scanlines and one providing 313 scanlines. See below for a description of the
54 video system.)
55
56 Access to RAM involves accessing four 64Kb dynamic RAM devices (IC4 to IC7,
57 each providing two bits of each byte) using two cycles within the 500ns period
58 of the 2MHz clock to complete each access operation. Since the CPU and ULA
59 have to take turns in accessing the RAM in MODE 4, 5 and 6, the CPU must
60 effectively run at 1MHz (since every other 500ns period involves the ULA
61 accessing RAM) during transfers of screen data.
62
63 The CPU is driven by an external clock (IC8) whose 16MHz frequency is divided
64 by the ULA (IC1) depending on the screen mode in use. Each 16MHz cycle is
65 approximately 62.5ns. To access the memory, the following patterns
66 corresponding to 16MHz cycles are required:
67
68 Time (ns): 0-------------- 500------------- ...
69 2 MHz cycle: 0 1 ...
70 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
71 /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ ...
72 ~RAS: /---\___________/---\___________ ...
73 ~CAS: /-----\___/-\___/-----\___/-\___ ...
74 Address events: A B C A B C ...
75 Data events: F S F S ...
76
77 ~RAS ops: 1 0 1 0 ...
78 ~CAS ops: 1 0 1 0 1 0 1 0 ...
79
80 Address ops: a b c a b c ...
81 Data ops: s f s f ...
82
83 ~WE: ......W ...
84 PHI OUT: \_______________/--------------- ...
85 CPU (RAM): L D ...
86 RnW: R ...
87
88 PHI OUT: \_______/-------\_______/------- ...
89 CPU (ROM): L D L D ...
90 RnW: R R ...
91
92 ~RAS must be high for 100ns, ~CAS must be high for 50ns.
93 ~RAS must be low for 150ns, ~CAS must be low for 90ns.
94 Data is available 150ns after ~RAS goes low, 90ns after ~CAS goes low.
95
96 Here, "A" and "B" respectively indicate the row and first column addresses
97 being latched into the RAM (on a negative edge for ~RAS and ~CAS
98 respectively), and "C" indicates the second column address being latched into
99 the RAM. Presumably, the first and second half-bytes can be read at "F" and
100 "S" respectively, and the row and column addresses must be made available at
101 "a" and "b" (and "c") respectively at the latest. Data can be read at "f" and
102 "s" for the first and second half-bytes respectively.
103
104 For the CPU, "L" indicates the point at which an address is taken from the CPU
105 address bus, on a negative edge of PHI OUT, with "D" being the point at which
106 data may either be read or be asserted for writing, on a positive edge of PHI
107 OUT. Here, PHI OUT is driven at 1MHz. Given that ~WE needs to be driven low
108 for writing or high for reading, and thus propagates RnW from the CPU, this
109 would need to be done before data would be retrieved and, according to the
110 TM4164EC4 datasheet, even as late as the column address is presented and ~CAS
111 brought low.
112
113 The TM4164EC4-15 has a row address access time of 150ns (maximum) and a column
114 address access time of 90ns (maximum), which appears to mean that ~RAS must be
115 held low for at least 150ns and that ~CAS must be held low for at least 90ns
116 before data becomes available. 150ns is 2.4 cycles (at 16MHz) and 90ns is 1.44
117 cycles. Thus, "A" to "F" is 2.5 cycles, "B" to "F" is 1.5 cycles, "C" to "S"
118 is 1.5 cycles.
119
120 Note that the Service Manual refers to the negative edge of RAS and CAS, but
121 the datasheet for the similar TM4164EC4 product shows latching on the negative
122 edge of ~RAS and ~CAS. It is possible that the Service Manual also intended to
123 communicate the latter behaviour. In the TM4164EC4 datasheet, it appears that
124 "page mode" provides the appropriate behaviour for that particular product.
125
126 The CPU, when accessing the RAM alone, apparently does not make use of the
127 vacated "slot" that the ULA would otherwise use (when interleaving accesses in
128 MODE 4, 5 and 6). It only employs a full 2MHz access frequency to memory when
129 accessing ROM (and potentially sideways RAM). The principal limitation is the
130 amount of time needed between issuing an address and receiving an entire byte
131 from the RAM, which is approximately 7 cycles (at 16MHz): much longer than the
132 4 cycles that would be required for 2MHz operation.
133
134 See: Acorn Electron Advanced User Guide
135 See: Acorn Electron Service Manual
136 http://chrisacorns.computinghistory.org.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf
137 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
138 See: http://stardot.org.uk/forums/viewtopic.php?p=120438#p120438
139 See: One of the Most Popular 65,536-Bit (64K) Dynamic RAMs The TMS 4164
140 http://smithsonianchips.si.edu/augarten/p64.htm
141
142 A Note on 8-Bit Wide RAM Access
143 -------------------------------
144
145 It is worth considering the timing when 8 bits of data can be obtained at once
146 from the RAM chips:
147
148 Time (ns): 0-------------- 500------------- ...
149 2 MHz cycle: 0 1 ...
150 8 MHz cycle: 0 1 2 3 0 1 2 3 ...
151 /-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_ ...
152 ~RAS: /---\___________/---\___________ ...
153 ~CAS: /-------\_______/-------\_______ ...
154 Address events: A B A B ...
155 Data events: E E ...
156
157 ~RAS ops: 1 0 1 0 ...
158 ~CAS ops: 1 0 1 0 ...
159
160 Address ops: a b a b ...
161 Data ops: f s f ...
162
163 ~WE: ........W ...
164 PHI OUT: \_______/-------\_______/------- ...
165 CPU: L D L D ...
166 RnW: R R ...
167
168 Here, "E" indicates the availability of an entire byte.
169
170 Since only one fetch is required per 2MHz cycle, instead of two fetches for
171 the 4-bit wide RAM arrangement, it seems likely that longer 8MHz cycles could
172 be used to coordinate the necessary signalling.
173
174 Another conceivable simplification from using an 8-bit wide RAM access channel
175 with a single access within each 2MHz cycle is the possibility of allowing the
176 CPU to signal directly to the RAM instead of having the ULA perform the access
177 signalling on the CPU's behalf. Note that it is this more leisurely signalling
178 that would allow the CPU to conduct accesses at 2MHz: the "compressed"
179 signalling being beyond the capabilities of the CPU.
180
181 Note that 16MHz cycles would still be needed for the pixel clock in MODE 0,
182 which needs to output eight pixels per 2MHz cycle, producing 640 monochrome
183 pixels per 80-byte line.
184
185 An obvious consideration with regard to 8-bit wide access is whether the ULA
186 could still conduct the "compressed" signalling for its own RAM accesses:
187
188 Time (ns): 0-------------- 500------------- ...
189 2 MHz cycle: 0 1 ...
190 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
191 /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ ...
192 ~RAS: /---\___________/---\___________ ...
193 ~CAS: /-----\___/-\___/-----\___/-\___ ...
194 Address events: A B C A B C ...
195 Data events: 1 2 1 2 ...
196
197 ~RAS ops: 1 0 1 0 ...
198 ~CAS ops: 1 0 1 0 1 0 1 0 ...
199
200 Address ops: a b c a b c ...
201 Data ops: s f s f ...
202
203 ~WE: ......W ...
204 PHI OUT: \_______/-------\_______/------- ...
205 CPU: L D L D ...
206 RnW: R R ...
207
208 Here, "1" and "2" in the data events correspond to whole byte accesses,
209 effectively upgrading the half-byte "F" and "S" events in the existing ULA
210 arrangement.
211
212 Although the provision of access for the CPU would adhere to the relevant
213 timing constraints, providing only one byte per 2MHz cycle, the ULA could
214 obtain two bytes per cycle. This would then free up bandwidth for the CPU in
215 screen modes where the ULA would normally be dominant (MODE 0 to 3), albeit at
216 the cost of extra buffering. Such buffering could also be done for modes where
217 the bandwidth is shared (MODE 4 to 6), consolidating pairs of ULA accesses into
218 single cycles and freeing up an extra cycle for CPU accesses.
219
220 A further consideration is whether the CPU and ULA could access the memory on
221 interleaved 4MHz cycles, thus replicating the arrangement used by the CPU and
222 Video ULA on the BBC Micro. One potential obstacle is that the apparent 4MHz
223 access rate employed by the ULA does not involve the complete process for
224 accessing the RAM: upon setting up the address and issuing the ~RAS signal,
225 the ULA is able to make a pair of column accesses on the same "row" of memory,
226 effectively achieving an average access rate of 4MHz in an 8-bit
227 configuration.
228
229 However, if arbitrary pairs of column accesses were to be attempted, as would
230 be required by CPU and ULA interleaving, the ~RAS signal would need to be
231 re-issued with different addresses being set up. This would expand the time to
232 access a memory location to beyond the period of a 4MHz cycle, making it
233 impossible to employ interleaved accesses at such a rate.
234
235 In conclusion, a strict interleaving strategy is not possible, but by using
236 pixel data buffering and employing two ULA accesses per 2MHz cycle to obtain
237 two bytes in that cycle, each adjacent 2MHz cycle can be given to the CPU,
238 thus achieving an effective throughput during display update periods of 3
239 bytes for every pair of cycles (2 bytes for the ULA, 1 byte for the CPU), and
240 thus 1.5 bytes per cycle, giving an illusion of 3MHz access to RAM.
241
242 Some other considerations apply to introducing 8-bit wide access. The ULA
243 employs four pins for data transfer to and from the memory devices (RAM0..3),
244 and obviously another four pins would be needed in an 8-bit wide scheme.
245 However, there may have been a physical limitation on the number of pins
246 permissible on a ULA package or the device's socket. This would necessitate
247 the reassignment of pins, although few are readily available for such
248 reassignment.
249
250 One approach might involve connecting the RAM devices to the CPU data bus,
251 with each line connecting to a different RAM chip. The signalling of the RAM
252 would remain under the control of the ULA, thus preventing the RAM devices
253 from interfering with other memory transfer operations, with the ROM
254 signalling also remaining under the ULA's control. One potential disadvantage
255 of this scheme would involve the elimination of the separate data paths
256 between the CPU and ROM and between the ULA and RAM.
257
258 Another approach might involve reclaiming the keyboard input pins (KBD0..3) as
259 data pins for ULA access to RAM. This would necessitate the reorganisation of
260 the keyboard interface, perhaps integrating the keyboard matrix more directly
261 as a kind of ROM device. A bus transceiver could be used to isolate the
262 keyboard inputs, with a pin being used to control the transceiver, since the
263 keyboard data lines are pulled high. In effect, the transceiver would act as a
264 kind of output enable for the keyboard.
265
266 To make the matrix appear within the sideways ROM region of the memory map,
267 A15 would need to be set to a high value and A14 to a low value. Signals A13
268 to A0 would then be brought low to select the appropriate column, with the
269 individual key states being made available via data lines, perhaps D3 to D0.
270 This mostly retains the existing addressing arrangement and scanning
271 mechanism. Internally, the ULA would continue to enable access to the keyboard
272 through the ROM paging mechanism, but instead of integrating separate data
273 pins into the CPU's data path, it would integrate the keyboard inputs using
274 the transceiver.
275
276 Enhancement: Keyboard Matrix Scanning
277 -------------------------------------
278
279 The keyboard scanning mechanism is presumably designed to be as inexpensive as
280 possible, being driven by software and avoiding extra logic, but at the
281 expense of occupying large regions of the memory map when paged in. A more
282 efficient mapping of the keyboard columns could possibly be done using
283 decoders such as the 74xx138 part which permits the decoding of three inputs
284 to select one of eight outputs. Using two of these parts, six address lines
285 would be dedicated to the keyboard columns as follows:
286
287 A5...A3 select up to eight columns via one decoder
288 A2...A0 select up to eight columns via another decoder
289
290 In this arrangement, only one of the two ranges of pins would be used at any
291 given time. If the ULA were to require a certain combination of the remaining
292 address bits, a region as small as 64 bytes could be dedicated to the
293 keyboard.
294
295 A more efficient arrangement could be used by introducing logic that allows
296 the decoders to work together to address the keyboard:
297
298 A2...A0 select up to eight columns via both decoders
299 A3 would enable one decoder if low and the other decoder if high
300
301 With ULA constraints on the remaining address bits, a 16-byte region could be
302 used to represent the keyboard.
303
304 A further refinement might involve combining the existing columns into groups
305 of eight keys. This would reduce the number of columns to seven, requiring
306 only three address lines, with all eight data lines being used to read the
307 matrix.
308
309 On the BBC Micro, the system 6522 VIA is used to monitor and read from the
310 keyboard. The memory locations involved with this chip are located in the
311 region from &FE40 to &FE7F inclusive, although the memory is allocated in a
312 way that is appropriate to operate that chip, as opposed to merely exposing
313 the keyboard matrix.
314
315 Enhancement: Hardware Device Selection
316 --------------------------------------
317
318 An alternative to the existing, rather cumbersome, sideways ROM mapping of the
319 keyboard might involve making it accessible via a hardware-related memory page
320 like page FE. With ULA addresses confined to FE0x, and with the ULA itself
321 having to trap accesses to page FE, the page selection signal might be brought
322 out of the ULA instead of any dedicated signal for the keyboard. Various
323 address lines corresponding to A7 through A4, or a subset of these, could be
324 fed into a decoder to permit the selection of other devices, with the keyboard
325 being one of these.
326
327 Meanwhile, a more efficient keyboard mapping using the above matrix
328 enhancement would permit the different keyboard columns to appear as a group
329 of sixteen or eight bytes. Thus:
330
331 A15...A8 select page FE
332 A7...A4 select a device or peripheral
333 A3...A0 select a register or keyboard column
334
335 Conceivably, devices such as sound generators could be mapped to device
336 regions.
337
338 CPU Clock Notes
339 ---------------
340
341 "The 6502 receives an external square-wave clock input signal on pin 37, which
342 is usually labeled PHI0. [...] This clock input is processed within the 6502
343 to form two clock outputs: PHI1 and PHI2 (pins 3 and 39, respectively). PHI2
344 is essentially a copy of PHI0; more specifically, PHI2 is PHI0 after it's been
345 through two inverters and a push-pull amplifier. The same network of
346 transistors within the 6502 which generates PHI2 is also tied to PHI1, and
347 generates PHI1 as the inverse of PHI0. The reason why PHI1 and PHI2 are made
348 available to external devices is so that they know when they can access the
349 CPU. When PHI1 is high, this means that external devices can read from the
350 address bus or data bus; when PHI2 is high, this means that external devices
351 can write to the data bus."
352
353 See: http://lateblt.livejournal.com/88105.html
354
355 "The 6502 has a synchronous memory bus where the master clock is divided into
356 two phases (Phase 1 and Phase 2). The address is always generated during Phase
357 1 and all memory accesses take place during Phase 2."
358
359 See: http://www.jmargolin.com/vgens/vgens.htm
360
361 Thus, the inverse of PHI OUT provides the "other phase" of the clock. "During
362 Phase 1" means when PHI0 - really PHI2 - is high and "during Phase 2" means
363 when PHI1 is high.
364
365 Bandwidth Figures
366 -----------------
367
368 Using an observation of 128 2MHz cycles per scanline, 256 active lines and 312
369 total lines, with 80 cycles occurring in the active periods of display
370 scanlines, the following bandwidth calculations can be performed:
371
372 Total theoretical maximum:
373 128 cycles * 312 lines
374 = 39936 bytes
375
376 MODE 0, 1, 2:
377 ULA: 80 cycles * 256 lines
378 = 20480 bytes
379 CPU: 48 cycles / 2 * 256 lines
380 + 128 cycles / 2 * (312 - 256) lines
381 = 9728 bytes
382
383 MODE 3:
384 ULA: 80 cycles * 24 rows * 8 lines
385 = 15360 bytes
386 CPU: 48 cycles / 2 * 24 rows * 8 lines
387 + 128 cycles / 2 * (312 - (24 rows * 8 lines))
388 = 12288 bytes
389
390 MODE 4, 5:
391 ULA: 40 cycles * 256 lines
392 = 10240 bytes
393 CPU: (40 cycles + 48 cycles / 2) * 256 lines
394 + 128 cycles / 2 * (312 - 256) lines
395 = 19968 bytes
396
397 MODE 6:
398 ULA: 40 cycles * 24 rows * 8 lines
399 = 7680 bytes
400 CPU: (40 cycles + 48 cycles / 2) * 24 rows * 8 lines
401 + 128 cycles / 2 * (312 - (24 rows * 8 lines))
402 = 19968 bytes
403
404 Here, the division of 2 for CPU accesses is performed to indicate that the CPU
405 only uses every other access opportunity even in uncontended periods. See the
406 2MHz RAM Access enhancement below for bandwidth calculations that consider
407 this limitation removed.
408
409 A summary of the bandwidth figures is as follows (with extra timing details
410 described below):
411
412 Standard ULA % Total Slowdown BBC-10s BBC-34s
413 MODE 0, 1, 2 9728 bytes 24% 4.11 43s 105s
414 MODE 3 12288 bytes 31% 3.25 34s
415 MODE 4, 5 19968 bytes 50% 2 20s
416 MODE 6 19968 bytes 50% 2 20s 50s
417
418 The review of the Electron in Practical Computing (October 1983) provides a
419 concise overview of the RAM access limitations and gives timing comparisons
420 between modes and BBC Micro performance. In the above, "BBC-10s" is the
421 measured or stated time given for a program taking 10 seconds on the BBC
422 Micro, whereas "BBC-34s" is the apparently measured time given for the
423 "Persian" program taking 34 seconds to complete on the BBC Micro, with a
424 "quick" mode presumably switching to MODE 6 using the ULA directly in order to
425 reduce display bandwidth usage while the program draws to the screen.
426 Evidently, the measured slowdown is slightly lower than the theoretical
427 slowdown, most likely due to the running time not being entirely dominated by
428 RAM access performance characteristics.
429
430 Video Timing
431 ------------
432
433 According to 8.7 in the Service Manual, and the PAL Wikipedia page,
434 approximately 4.7µs is used for the sync pulse, 5.7µs for the "back porch"
435 (including the "colour burst"), and 1.65µs for the "front porch", totalling
436 12.05µs and thus leaving 51.95µs for the active video signal for each
437 scanline. As the Service Manual suggests in the oscilloscope traces, the
438 display information is transmitted more or less centred within the active
439 video period since the ULA will only be providing pixel data for 40µs in each
440 scanline.
441
442 Each 62.5ns cycle happens to correspond to 64µs divided by 1024, meaning that
443 each scanline can be divided into 1024 cycles, although only 640 at most are
444 actively used to provide pixel data. Pixel data production should only occur
445 within a certain period on each scanline, approximately 262 cycles after the
446 start of hsync:
447
448 active video period = 51.95µs
449 pixel data period = 40µs
450 total silent period = 51.95µs - 40µs = 11.95µs
451 silent periods (before and after) = 11.95µs / 2 = 5.975µs
452 hsync and back porch period = 4.7µs + 5.7µs = 10.4µs
453 time before pixel data period = 10.4µs + 5.975µs = 16.375µs
454 pixel data period start cycle = 16.375µs / 62.5ns = 262
455
456 By choosing a number divisible by 8, the RAM access mechanism can be
457 synchronised with the pixel production. Thus, 256 is a more appropriate start
458 cycle, where the HS (horizontal sync) signal corresponding to the 4µs sync
459 pulse (or "normal sync" pulse as described by the "PAL TV timing and voltages"
460 document) occurs at cycle 0.
461
462 To summarise:
463
464 HS signal starts at cycle 0 on each horizontal scanline
465 HS signal ends approximately 4µs later at cycle 64
466 Pixel data starts approximately 12µs later at cycle 256
467
468 "Re: Electron Memory Contention" provides measurements that appear consistent
469 with these calculations.
470
471 The "vertical blanking period", meaning the period before picture information
472 in each field is 25 lines out of 312 (or 313) and thus lasts for 1.6ms. Of
473 this, 2.5 lines occur before the vsync (field sync) which also lasts for 2.5
474 lines. Thus, the first visible scanline on the first field of a frame occurs
475 half way through the 23rd scanline period measured from the start of vsync
476 (indicated by "V" in the diagrams below):
477
478 10 20 23
479 Line in frame: 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8
480 Line from 1: 0 22 3
481 Line on screen: .:::::VVVVV::::: 12233445566
482 |_________________________________________________|
483 25 line vertical blanking period
484
485 In the second field of a frame, the first visible scanline coincides with the
486 24th scanline period measured from the start of line 313 in the frame:
487
488 310 336
489 Line in frame: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
490 Line from 313: 0 23 4
491 Line on screen: 88:::::VVVVV:::: 11223344
492 288 | |
493 |_________________________________________________|
494 25 line vertical blanking period
495
496 In order to consider only full lines, we might consider the start of each
497 frame to occur 23 lines after the start of vsync.
498
499 Again, it is likely that pixel data production should only occur on scanlines
500 within a certain period on each frame. The "625/50" document indicates that
501 only a certain region is "safe" to use, suggesting a vertically centred region
502 with approximately 15 blank lines above and below the picture. However, the
503 "PAL TV timing and voltages" document suggests 28 blank lines above and below
504 the picture. This would centre the 256 lines within the 312 lines of each
505 field and thus provide a start of picture approximately 5.5 or 5 lines after
506 the end of the blanking period or 28 or 27.5 lines after the start of vsync.
507
508 To summarise:
509
510 CSYNC signal starts at cycle 0
511 CSYNC signal ends approximately 160µs (2.5 lines) later at cycle 2560
512 Start of line occurs approximately 1632µs (5.5 lines) later at cycle 28672
513
514 See: http://en.wikipedia.org/wiki/PAL
515 See: http://en.wikipedia.org/wiki/Analog_television#Structure_of_a_video_signal
516 See: The 625/50 PAL Video Signal and TV Compatible Graphics Modes
517 http://lipas.uwasa.fi/~f76998/video/modes/
518 See: PAL TV timing and voltages
519 http://www.retroleum.co.uk/electronics-articles/pal-tv-timing-and-voltages/
520 See: Line Standards
521 http://www.pembers.freeserve.co.uk/World-TV-Standards/Line-Standards.html
522 See: Horizontal Blanking Interval of 405-, 525-, 625- and 819-Line Standards
523 http://www.pembers.freeserve.co.uk/World-TV-Standards/HBI.pdf
524 See: Re: Electron Memory Contention
525 http://www.stardot.org.uk/forums/viewtopic.php?p=134109#p134109
526
527 RAM Integrated Circuits
528 -----------------------
529
530 Unicorn Electronics appears to offer 4164 RAM chips (as well as 6502 series
531 CPUs such as the 6502, 6502A, 6502B and 65C02). These 4164 devices are
532 available in 100ns (4164-100), 120ns (4164-120) and 150ns (4164-150) variants,
533 have 16 pins and address 65536 bits through a 1-bit wide channel. Similarly,
534 ByteDelight.com sell 4164 devices primarily for the ZX Spectrum.
535
536 The documentation for the Electron mentions 4164-15 RAM chips for IC4-7, and
537 the Samsung-produced KM41464 series is apparently equivalent to the Texas
538 Instruments 4164 chips presumably used in the Electron.
539
540 The TM4164EC4 series combines 4 64K x 1b units into a single package and
541 appears similar to the TM4164EA4 featured on the Electron's circuit diagram
542 (in the Advanced User Guide but not the Service Manual), and it also has 22
543 pins providing 3 additional inputs and 3 additional outputs over the 16 pins
544 of the individual 4164-15 modules, presumably allowing concurrent access to
545 the packaged memory units.
546
547 As far as currently available replacements are concerned, the NTE4164 is a
548 potential candidate: according to the Vetco Electronics entry, it is
549 supposedly a replacement for the TMS4164-15 amongst many other parts. Similar
550 parts include the NTE2164 and the NTE6664, both of which appear to have
551 largely the same performance and connection characteristics. Meanwhile, the
552 NTE21256 appears to be a 16-pin replacement with four times the capacity that
553 maintains the single data input and output pins. Using the NTE21256 as a
554 replacement for all ICs combined would be difficult because of the single bit
555 output.
556
557 Another device equivalent to the 4164-15 appears to be available under the
558 code 41662 from Jameco Electronics as the Siemens HYB 4164-2. The Jameco Web
559 site lists data sheets for other devices on the same page, but these are
560 different and actually appear to be provided under the 41574 product code (but
561 are listed under 41464-10) and appear to be replacements for the TM4164EC4:
562 the Samsung KM41464A-15 and NEC µPD41464 employ 18 pins, eliminating 4 pins by
563 employing 4 pins for both input and output.
564
565 Pins I/O pins Row access Column access
566 ---- -------- ---------- -------------
567 TM4164EC4 22 4 + 4 150ns (15) 90ns (15)
568 KM41464AP 18 4 150ns (15) 75ns (15)
569 NTE21256 16 1 + 1 150ns 75ns
570 HYB 4164-2 16 1 + 1 150ns 100ns
571 µPD41464 18 4 120ns (12) 60ns (12)
572
573 See: TM4164EC4 65,536 by 4-Bit Dynamic RAM Module
574 http://www.datasheetarchive.com/dl/Datasheets-112/DSAP0051030.pdf
575 See: Dynamic RAMS
576 http://www.unicornelectronics.com/IC/DYNAMIC.html
577 See: New old stock 8x 4164 chips
578 http://www.bytedelight.com/?product=8x-4164-chips-new-old-stock
579 See: KM4164B 64K x 1 Bit Dynamic RAM with Page Mode
580 http://images.ihscontent.net/vipimages/VipMasterIC/IC/SAMS/SAMSD020/SAMSD020-45.pdf
581 See: NTE2164 Integrated Circuit 65,536 X 1 Bit Dynamic Random Access Memory
582 http://www.vetco.net/catalog/product_info.php?products_id=2806
583 See: NTE4164 - IC-NMOS 64K DRAM 150NS
584 http://www.vetco.net/catalog/product_info.php?products_id=3680
585 See: NTE21256 - IC-256K DRAM 150NS
586 http://www.vetco.net/catalog/product_info.php?products_id=2799
587 See: NTE21256 262,144-Bit Dynamic Random Access Memory (DRAM)
588 http://www.nteinc.com/specs/21000to21999/pdf/nte21256.pdf
589 See: NTE6664 - IC-MOS 64K DRAM 150NS
590 http://www.vetco.net/catalog/product_info.php?products_id=5213
591 See: NTE6664 Integrated Circuit 64K-Bit Dynamic RAM
592 http://www.nteinc.com/specs/6600to6699/pdf/nte6664.pdf
593 See: 4164-150: MAJOR BRANDS
594 http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41662_-1
595 See: HYB 4164-1, HYB 4164-2, HYB 4164-3 65,536-Bit Dynamic Random Access Memory (RAM)
596 http://www.jameco.com/Jameco/Products/ProdDS/41662SIEMENS.pdf
597 See: KM41464A NMOS DRAM 64K x 4 Bit Dynamic RAM with Page Mode
598 http://www.jameco.com/Jameco/Products/ProdDS/41662SAM.pdf
599 See: NEC µ41464 65,536 x 4-Bit Dynamic NMOS RAM
600 http://www.jameco.com/Jameco/Products/ProdDS/41662NEC.pdf
601 See: 41464-10: MAJOR BRANDS
602 http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41574_-1
603
604 Interrupts
605 ----------
606
607 The ULA generates IRQs (maskable interrupts) according to certain conditions
608 and these conditions are controlled by location &FE00:
609
610 * Vertical sync (bottom of displayed screen)
611 * 50MHz real time clock
612 * Transmit data empty
613 * Receive data full
614 * High tone detect
615
616 The ULA is also used to clear interrupt conditions through location &FE05. Of
617 particular significance is bit 7, which must be set if an NMI (non-maskable
618 interrupt) has occurred and has thus suspended ULA access to memory, restoring
619 the normal function of the ULA.
620
621 ROM Paging
622 ----------
623
624 Accessing different ROMs involves bits 0 to 3 of &FE05. Some special ROM
625 mappings exist:
626
627 8 keyboard
628 9 keyboard (duplicate)
629 10 BASIC ROM
630 11 BASIC ROM (duplicate)
631
632 Paging in a ROM involves the following procedure:
633
634 1. Assert ROM page enable (bit 3) together with a ROM number n in bits 0 to
635 2, corresponding to ROM number 8+n, such that one of ROMs 12 to 15 is
636 selected.
637 2. Where a ROM numbered from 0 to 7 is to be selected, set bit 3 to zero
638 whilst writing the desired ROM number n in bits 0 to 2.
639
640 See: http://stardot.org.uk/forums/viewtopic.php?p=136686#p136686
641
642 Keyboard Access
643 ---------------
644
645 The keyboard pages appear to be accessed at 1MHz just like the RAM.
646
647 See: https://stardot.org.uk/forums/viewtopic.php?p=254155#p254155
648
649 Shadow/Expanded Memory
650 ----------------------
651
652 The Electron exposes all sixteen address lines and all eight data lines
653 through the expansion bus. Using such lines, it is possible to provide
654 additional memory - typically sideways ROM and RAM - on expansion cards and
655 through cartridges, although the official cartridge specification provides
656 fewer address lines and only seeks to provide access to memory in 16K units.
657
658 Various modifications and upgrades were developed to offer "turbo"
659 capabilities to the Electron, permitting the CPU to access a separate 8K of
660 RAM at 2MHz, presumably preventing access to the low 8K of RAM accessible via
661 the ULA through additional logic. However, an enhanced ULA might support
662 independent CPU access to memory over the expansion bus by allowing itself to
663 be discharged from providing access to memory, potentially for a range of
664 addresses, and for the CPU to communicate with external memory uninterrupted.
665
666 Sideways RAM/ROM and Upper Memory Access
667 ----------------------------------------
668
669 Although the ULA controls the CPU clock, effectively slowing or stopping the
670 CPU when the ULA needs to access screen memory, it is apparently able to allow
671 the CPU to access addresses of &8000 and above - the upper region of memory -
672 at 2MHz independently of any access to RAM that the ULA might be performing,
673 only blocking the CPU if it attempts to access addresses of &7FFF and below
674 during any ULA memory access - the lower region of memory - by stopping or
675 stalling its clock.
676
677 Thus, the ULA remains aware of the level of the A15 line, only inhibiting the
678 CPU clock if the line goes low, when the CPU is attempting to access the lower
679 region of memory.
680
681 Hardware Scrolling (and Enhancement)
682 ------------------------------------
683
684 On the standard ULA, &FE02 and &FE03 map to a 9 significant bits address with
685 the least significant 5 bits being zero, thus limiting the scrolling
686 resolution to 64 bytes. An enhanced ULA could support a resolution of 2 bytes
687 using the same layout of these addresses.
688
689 |--&FE02--------------| |--&FE03--------------|
690 XX XX 14 13 12 11 10 09 08 07 06 XX XX XX XX XX
691
692 XX 14 13 12 11 10 09 08 07 06 05 04 03 02 01 XX
693
694 Arguably, a resolution of 8 bytes is more useful, since the mapping of screen
695 memory to pixel locations is character oriented. A change in 8 bytes would
696 permit a horizontal scrolling resolution of 2 pixels in MODE 2, 4 pixels in
697 MODE 1 and 5, and 8 pixels in MODE 0, 3 and 6. This resolution is actually
698 observed on the BBC Micro (see 18.11.2 in the BBC Microcomputer Advanced User
699 Guide).
700
701 One argument for a 2 byte resolution is smooth vertical scrolling. A pitfall
702 of changing the screen address by 2 bytes is the change in the number of lines
703 from the initial and final character rows that need reading by the ULA, which
704 would need to maintain this state information (although this is a relatively
705 trivial change). Another pitfall is the complication that might be introduced
706 to software writing bitmaps of character height to the screen.
707
708 See: http://pastraiser.com/computers/acornelectron/acornelectron.html
709
710 Enhancement: Mode Layouts
711 -------------------------
712
713 Merely changing the screen memory mappings in order to have Archimedes-style
714 row-oriented screen addresses (instead of character-oriented addresses) could
715 be done for the existing modes, but this might not be sufficiently beneficial,
716 especially since accessing regions of the screen would involve incrementing
717 pointers by amounts that are inconvenient on an 8-bit CPU.
718
719 However, instead of using a Archimedes-style mapping, column-oriented screen
720 addresses could be more feasibly employed: incrementing the address would
721 reference the vertical screen location below the currently-referenced location
722 (just as occurs within characters using the existing ULA); instead of
723 returning to the top of the character row and referencing the next horizontal
724 location after eight bytes, the address would reference the next character row
725 and continue to reference locations downwards over the height of the screen
726 until reaching the bottom; at the bottom, the next location would be the next
727 horizontal location at the top of the screen.
728
729 In other words, the memory layout for the screen would resemble the following
730 (for MODE 2):
731
732 &3000 &3100 ... &7F00
733 &3001 &3101
734 ... ...
735 &3007
736 &3008
737 ...
738 ... ...
739 &30FF ... &7FFF
740
741 Since there are 256 pixel rows, each column of locations would be addressable
742 using the low byte of the address. Meanwhile, the high byte would be
743 incremented to address different columns. Thus, addressing screen locations
744 would become a lot more convenient and potentially much more efficient for
745 certain kinds of graphical output.
746
747 One potential complication with this simplified addressing scheme arises with
748 hardware scrolling. Vertical hardware scrolling by one pixel row (not supported
749 with the existing ULA) would be achieved by incrementing or decrementing the
750 screen start address; by one character row, it would involve adding or
751 subtracting 8. However, the ULA only supports multiples of 64 when changing the
752 screen start address. Thus, if such a scheme were to be adopted, three
753 additional bits would need to be supported in the screen start register (see
754 "Hardware Scrolling (and Enhancement)" for more details). However, horizontal
755 scrolling would be much improved even under the severe constraints of the
756 existing ULA: only adjustments of 256 to the screen start address would be
757 required to produce single-location scrolling of as few as two pixels in MODE 2
758 (four pixels in MODEs 1 and 5, eight pixels otherwise).
759
760 More disruptive is the effect of this alternative layout on software.
761 Presumably, compatibility with the BBC Micro was the primary goal of the
762 Electron's hardware design. With the character-oriented screen layout in
763 place, system software (and application software accessing the screen
764 directly) would be relying on this layout to run on the Electron with little
765 or no modification. Although it might have been possible to change the system
766 software to use this column-oriented layout instead, this would have incurred
767 a development cost and caused additional work porting things like games to the
768 Electron. Moreover, a separate branch of the software from that supporting the
769 BBC Micro and closer derivatives would then have needed maintaining.
770
771 The decision to use the character-oriented layout in the BBC Micro may have
772 been related to the choice of circuitry and to facilitate a convenient
773 hardware implementation, and by the time the Electron was planned, it was too
774 late to do anything about this somewhat unfortunate choice.
775
776 Pixel Layouts
777 -------------
778
779 The pixel layouts are as follows:
780
781 Modes Depth (bpp) Pixels (from bits)
782 ----- ----------- ------------------
783 0, 3, 4, 6 1 7 6 5 4 3 2 1 0
784 1, 5 2 73 62 51 40
785 2 4 7531 6420
786
787 Since the ULA reads a half-byte at a time, one might expect it to attempt to
788 produce pixels for every half-byte, as opposed to handling entire bytes.
789 However, the pixel layout is not conducive to producing pixels as soon as a
790 half-byte has been read for a given full-byte location: in 1bpp modes the
791 first four pixels can indeed be produced, but in 2bpp and 4bpp modes the pixel
792 data is spread across the entire byte in different ways.
793
794 An alternative arrangement might be as follows:
795
796 Modes Depth (bpp) Pixels (from bits)
797 ----- ----------- ------------------
798 0, 3, 4, 6 1 7 6 5 4 3 2 1 0
799 1, 5 2 76 54 32 10
800 2 4 7654 3210
801
802 Just as the mode layouts were presumably decided by compatibility with the BBC
803 Micro, the pixel layouts will have been maintained for similar reasons.
804 Unfortunately, this layout prevents any optimisation of the ULA for handling
805 half-byte pixel data generally.
806
807 Enhancement: The Missing MODE 4
808 -------------------------------
809
810 The Electron inherits its screen mode selection from the BBC Micro, where MODE
811 3 is a text version of MODE 0, and where MODE 6 is a text version of MODE 4.
812 Neither MODE 3 nor MODE 6 is a genuine character-based text mode like MODE 7,
813 however, and they are merely implemented by skipping two scanlines in every
814 ten after the eight required to produce a character line. Thus, such modes
815 provide a 24-row display.
816
817 In principle, nothing prevents this "text mode" effect being applied to other
818 modes. The 20-column modes are not well-suited to displaying text, which
819 leaves MODE 1 which, unlike MODEs 3 and 6, can display 4 colours rather than
820 2. Although the need for a non-monochrome 40-column text mode is addressed by
821 MODE 7 on the BBC Micro, the Electron lacks such a mode.
822
823 If the 4-colour, 24-row variant of MODE 1 were to be provided, logically it
824 would occupy MODE 4 instead of the current MODE 4:
825
826 Screen mode Size (kilobytes) Colours Rows Resolution
827 ----------- ---------------- ------- ---- ----------
828 0 20 2 32 640x256
829 1 20 4 32 320x256
830 2 20 16 32 160x256
831 3 16 2 24 640x256
832 4 (new) 16 4 24 320x256
833 4 (old) 10 2 32 320x256
834 5 10 4 32 160x256
835 6 8 2 24 320x256
836
837 Thus, for increasing mode numbers, the size of each mode would be the same or
838 less than the preceding mode.
839
840 Enhancement: Display Mode Property Control
841 ------------------------------------------
842
843 It is rather curious that the ULA supports the mode numbers directly in bits 3
844 to 5 of &FE07 since these would presumably need to be decoded in order to set
845 the fundamental properties of the display mode. These properties are as
846 follows:
847
848 * Screen data retrieval rate: number of fetches per pair of 2MHz cycles
849 * Pixel colour depth
850 * Text mode vertical spacing
851
852 From these, the following properties emerge:
853
854 Property Influences
855 -------- ----------
856 Character row size (bytes) Retrieval rate
857
858 Number of character rows Text mode setting
859
860 Display size (bytes) Retrieval rate (character row size)
861 Text mode setting (number of rows)
862
863 Pixel frequency Retrieval rate
864 Horizontal resolution (pixels) Colour depth
865
866 One can imagine a register bitfield arrangement as follows:
867
868 Field Values Formula
869 ----- ------ -------
870 Pixel depth 00: 1 bit per pixel log2(depth)
871 01: 2 bits per pixel
872 10: 4 bits per pixel
873
874 Retrieval rate 0: twice 2 - fetches per cycle pair
875 1: once
876
877 Text mode enable 0: disable/off text mode enabled
878 1: enable/on
879
880 This arrangement would require four bits. However, one bit in &FE07 is
881 seemingly inactive and might possibly be reallocated.
882
883 The resulting combination of properties would permit all of the existing modes
884 plus some additional ones, including the missing MODE 4 mentioned above. With
885 the bitfields above ordered from the most significant bits to the least
886 significant bits providing the low-level "mode" values, the following table
887 can be produced:
888
889 Screen mode Depth Rate Text Size (K) Colours Rows Resolution
890 ----------- ----- ---- ---- -------- ------- ---- ----------
891 0 (0000) 1 twice off 20 2 32 640x256 (MODE 0)
892 1 (0001) 1 twice on 16 2 24 640x256 (MODE 3)
893 2 (0010) 1 once off 10 2 32 320x256 (MODE 4)
894 3 (0011) 1 once on 8 2 24 320x256 (MODE 6)
895 4 (0100) 2 twice off 20 4 32 320x256 (MODE 1)
896 5 (0101) 2 twice on 16 4 24 320x256
897 6 (0110) 2 once off 10 4 32 160x256 (MODE 5)
898 7 (0111) 2 once on 8 4 24 160x256
899 8 (1000) 4 twice off 20 16 32 160x256 (MODE 2)
900 9 (1001) 4 twice on 16 16 24 160x256
901 10 (1010) 4 once off 10 16 32 80x256
902 11 (1011) 4 once on 8 16 24 80x256
903
904 The existing modes would be covered in a way that is incompatible with the
905 existing numbering, thus requiring a table in software, but additional text
906 modes would be provided for MODE 1, MODE 5 and MODE 2. An additional two lower
907 resolution modes would also be conceivable within this scheme, requiring the
908 stretching of 16MHz pixels by a factor of eight to yield 80 pixels per
909 scanline. The utility of such modes is questionable and such modes might not
910 be supported.
911
912 Enhancement: 2MHz RAM Access
913 ----------------------------
914
915 Given that the CPU and ULA both access RAM at 2MHz, but given that the CPU
916 when not competing with the ULA only accesses RAM every other 2MHz cycle (as
917 if the ULA still needed to access the RAM), one useful enhancement would be a
918 mechanism to let the CPU take over the ULA cycles outside the ULA's period of
919 activity comparable to the way the ULA takes over the CPU cycles in MODE 0 to
920 3.
921
922 Thus, the RAM access cycles would resemble the following in MODE 0 to 3:
923
924 Upon a transition from display cycles: UUUUCCCC (instead of UUUUC_C_)
925 On a non-display line: CCCCCCCC (instead of C_C_C_C_)
926
927 In MODE 4 to 6:
928
929 Upon a transition from display cycles: CUCUCCCC (instead of CUCUC_C_)
930 On a non-display line: CCCCCCCC (instead of C_C_C_C_)
931
932 This would improve CPU bandwidth as follows:
933
934 Standard ULA Enhanced ULA % Total Bandwidth Speedup
935 MODE 0, 1, 2 9728 bytes 19456 bytes 24% -> 49% 2
936 MODE 3 12288 bytes 24576 bytes 31% -> 62% 2
937 MODE 4, 5 19968 bytes 29696 bytes 50% -> 74% 1.5
938 MODE 6 19968 bytes 32256 bytes 50% -> 81% 1.6
939
940 (Here, the uncontended total 2MHz bandwidth for a display period would be
941 39936 bytes, being 128 cycles per line over 312 lines.)
942
943 With such an enhancement, MODE 0 to 3 experience a doubling of CPU bandwidth
944 because all access opportunities to RAM are doubled. Meanwhile, in the other
945 modes, some CPU accesses occur alongside ULA accesses and thus cannot be
946 doubled, but the CPU bandwidth increase is still significant.
947
948 Unfortunately, the mechanism for accessing the RAM is too slow to provide data
949 within the time constraints of 2MHz operation. There is no time remaining in a
950 2MHz cycle for the CPU to receive and process any retrieved data once the
951 necessary signalling has been performed.
952
953 The only way for the CPU to be able to access the RAM quickly enough would be
954 to do away with the double 4-bit access mechanism and to have a single 8-bit
955 channel to the memory. This would require twice as many 1-bit RAM chips or a
956 different kind of RAM chip, but it would also potentially simplify the ULA.
957
958 The section on 8-bit wide RAM access discusses the possibilities around
959 changing the memory architecture, also describing the possibility of ULA
960 accesses achieving two bytes per 2MHz cycle due to the doubling of the memory
961 channel, leaving every other access free for the CPU during the display period
962 in MODE 0 to 3...
963
964 Standard display period: UUUUUUUU
965 Modified display period: UCUCUCUC
966
967 ...and consolidating accesses in MODE 4 to 6:
968
969 Standard display period: UCUCUCUC
970 Modified display period: UCCCUCCC
971
972 Together with the enhancements for non-display periods, such an "Enhanced+ ULA"
973 would perform as follows:
974
975 Standard ULA Enhanced+ ULA % Total Bandwidth Speedup
976 MODE 0, 1, 2 9728 bytes 29696 bytes 24% -> 74% 3.1
977 MODE 3 12288 bytes 32256 bytes 31% -> 81% 2.6
978 MODE 4, 5 19968 bytes 34816 bytes 50% -> 87% 1.7
979 MODE 6 19968 bytes 36096 bytes 50% -> 90% 1.8
980
981 Of course, the principal enhancement would be the wider memory channel, with
982 more buffering in the ULA being its contribution to this arrangement.
983
984 Enhancement: Region Blanking
985 ----------------------------
986
987 The problem of permitting character-oriented blitting in programs whilst
988 scrolling the screen by sub-character amounts could be mitigated by permitting
989 a region of the display to be blank, such as the final lines of the display.
990 Consider the following vertical scrolling by 2 bytes that would cause an
991 initial character row of 6 lines and a final character row of 2 lines:
992
993 6 lines - initial, partial character row
994 248 lines - 31 complete rows
995 2 lines - final, partial character row
996
997 If a routine were in use that wrote 8 line bitmaps to the partial character
998 row now split in two, it would be advisable to hide one of the regions in
999 order to prevent content appearing in the wrong place on screen (such as
1000 content meant to appear at the top "leaking" onto the bottom). Blanking 6
1001 lines would be sufficient, as can be seen from the following cases.
1002
1003 Scrolling up by 2 lines:
1004
1005 6 lines - initial, partial character row
1006 240 lines - 30 complete rows
1007 4 lines - part of 1 complete row
1008 -----------------------------------------------------------------
1009 4 lines - part of 1 complete row (hidden to maintain 250 lines)
1010 2 lines - final, partial character row (hidden)
1011
1012 Scrolling down by 2 lines:
1013
1014 2 lines - initial, partial character row
1015 248 lines - 31 complete rows
1016 ----------------------------------------------------------
1017 6 lines - final, partial character row (hidden)
1018
1019 Thus, in this case, region blanking would impose a 250 line display with the
1020 bottom 6 lines blank.
1021
1022 See the description of the display suspend enhancement for a more efficient
1023 way of blanking lines than merely blanking the palette whilst allowing the CPU
1024 to perform useful work during the blanking period.
1025
1026 To control the blanking or suspending of lines at the top and bottom of the
1027 display, a memory location could be dedicated to the task: the upper 4 bits
1028 could define a blanking region of up to 16 lines at the top of the screen,
1029 whereas the lower 4 bits could define such a region at the bottom of the
1030 screen. If more lines were required, two locations could be employed, allowing
1031 the top and bottom regions to occupy the entire screen.
1032
1033 Enhancement: Screen Height Adjustment
1034 -------------------------------------
1035
1036 The height of the screen could be configurable in order to reduce screen
1037 memory consumption. This is not quite done in MODE 3 and 6 since the start of
1038 the screen appears to be rounded down to the nearest page, but by reducing the
1039 height by amounts more than a page, savings would be possible. For example:
1040
1041 Screen width Depth Height Bytes per line Saving in bytes Start address
1042 ------------ ----- ------ -------------- --------------- -------------
1043 640 1 252 80 320 &3140 -> &3100
1044 640 1 248 80 640 &3280 -> &3200
1045 320 1 240 40 640 &5A80 -> &5A00
1046 320 2 240 80 1280 &3500
1047
1048 Screen Mode Selection
1049 ---------------------
1050
1051 Bits 3, 4 and 5 of address &FE*7 control the selected screen mode. For a wider
1052 range of modes, the other bits of &FE*7 (related to sound, cassette
1053 input/output and the Caps Lock LED) would need to be reassigned and bit 0
1054 potentially being made available for use.
1055
1056 Enhancement: Palette Definition
1057 -------------------------------
1058
1059 Since all memory accesses go via the ULA, an enhanced ULA could employ more
1060 specific addresses than &FE*X to perform enhanced functions. For example, the
1061 palette control is done using &FE*8-F and merely involves selecting predefined
1062 colours, whereas an enhanced ULA could support the redefinition of all 16
1063 colours using specific ranges such as &FE18-F (colours 0 to 7) and &FE28-F
1064 (colours 8 to 15), where a single byte might provide 8 bits per pixel colour
1065 specifications similar to those used on the Archimedes.
1066
1067 The principal limitation here is actually the hardware: the Electron has only
1068 a single output line for each of the red, green and blue channels, and if
1069 those outputs are strictly digital and can only be set to a "high" and "low"
1070 value, then only the existing eight colours are possible. If a modern ULA were
1071 able to output analogue values (or values at well-defined points between the
1072 high and low values, such as the half-on value supported by the Amstrad CPC
1073 series), it would still need to be assessed whether the circuitry could
1074 successfully handle and propagate such values. Various sources indicate that
1075 only "TTL levels" are supported by the RGB output circuit, and since there are
1076 74LS08 AND logic gates involved in the RGB component outputs from the ULA, it
1077 is likely that the ULA is expected to provide only "high" or "low" values.
1078
1079 Short of adding extra outputs from the ULA (either additional red, green and
1080 blue outputs or a combined intensity output), another approach might involve
1081 some kind of modulation where an output value might be encoded in multiple
1082 pulses at a higher frequency than the pixel frequency. However, this would
1083 demand additional circuitry outside the ULA, and component RGB monitors would
1084 probably not be able to take advantage of this feature; only UHF and composite
1085 video devices (the latter with the composite video colour support enabled on
1086 the Electron's circuit board) would potentially benefit.
1087
1088 Flashing Colours
1089 ----------------
1090
1091 According to the Advanced User Guide, "The cursor and flashing colours are
1092 entirely generated in software: This means that all of the logical to physical
1093 colour map must be changed to cause colours to flash." This appears to suggest
1094 that the palette registers must be updated upon the flash counter - read and
1095 written by OSBYTE &C1 (193) - reaching zero and that some way of changing the
1096 colour pairs to be any combination of colours might be possible, instead of
1097 having colour complements as pairs.
1098
1099 It is conceivable that the interrupt code responsible does the simple thing
1100 and merely inverts the current values for any logical colours (LC) for which
1101 the associated physical colour (as supplied as the second parameter to the VDU
1102 19 call) has the top bit of its four bit value set. These top bits are not
1103 recorded in the palette registers but are presumably recorded separately and
1104 used to build bitmaps as follows:
1105
1106 LC 2 colour 4 colour 16 colour 4-bit value for inversion
1107 -- -------- -------- --------- -------------------------
1108 0 00010001 00010001 00010001 1, 1, 1
1109 1 01000100 00100010 00010001 4, 2, 1
1110 2 01000100 00100010 4, 2
1111 3 10001000 00100010 8, 2
1112 4 00010001 1
1113 5 00010001 1
1114 6 00100010 2
1115 7 00100010 2
1116 8 01000100 4
1117 9 01000100 4
1118 10 10001000 8
1119 11 10001000 8
1120 12 01000100 4
1121 13 01000100 4
1122 14 10001000 8
1123 15 10001000 8
1124
1125 Inversion value calculation:
1126
1127 2 colour formula: 1 << (colour * 2)
1128 4 colour formula: 1 << colour
1129 16 colour formula: 1 << ((colour & 2) + ((colour & 8) * 2))
1130
1131 For example, where logical colour 0 has been mapped to a physical colour in
1132 the range 8 to 15, a bitmap of 00010001 would be chosen as its contribution to
1133 the inversion operation. (The lower three bits of the physical colour would be
1134 used to set the underlying colour information affected by the inversion
1135 operation.)
1136
1137 An operation in the interrupt code would then combine the bitmaps for all
1138 logical colours in 2 and 4 colour modes, with the 16 colour bitmaps being
1139 combined for groups of logical colours as follows:
1140
1141 Logical colours
1142 ---------------
1143 0, 2, 8, 10
1144 4, 6, 12, 14
1145 5, 7, 13, 15
1146 1, 3, 9, 11
1147
1148 These combined bitmaps would be EORed with the existing palette register
1149 values in order to perform the value inversion necessary to produce the
1150 flashing effect.
1151
1152 Thus, in the VDU 19 operation, the appropriate inversion value would be
1153 calculated for the logical colour, and this value would then be combined with
1154 other inversion values in a dedicated memory location corresponding to the
1155 colour's group as indicated above. Meanwhile, the palette channel values would
1156 be derived from the lower three bits of the specified physical colour and
1157 combined with other palette data in dedicated memory locations corresponding
1158 to the palette registers.
1159
1160 Interestingly, although flashing colours on the BBC Micro are controlled by
1161 toggling bit 0 of the &FE20 control register location for the Video ULA, the
1162 actual colour inversion is done in hardware.
1163
1164 Enhancement: Palette Definition Lists
1165 -------------------------------------
1166
1167 It can be useful to redefine the palette in order to change the colours
1168 available for a particular region of the screen, particularly in modes where
1169 the choice of colours is constrained, and if an increased colour depth were
1170 available, palette redefinition would be useful to give the illusion of more
1171 than 16 colours in MODE 2. Traditionally, palette redefinition has been done
1172 by using interrupt-driven timers, but a more efficient approach would involve
1173 presenting lists of palette definitions to the ULA so that it can change the
1174 palette at a particular display line.
1175
1176 One might define a palette redefinition list in a region of memory and then
1177 communicate its contents to the ULA by writing the address and length of the
1178 list, along with the display line at which the palette is to be changed, to
1179 ULA registers such that the ULA buffers the list and performs the redefinition
1180 at the appropriate time. Throughput/bandwidth considerations might impose
1181 restrictions on the practical length of such a list, however.
1182
1183 A simple form of palette definition might be useful in text modes. Within the
1184 blank region between lines, the foreground palette could be changed to apply
1185 to the next line. Palette values could be read from a table in RAM, perhaps
1186 preceding the screen data, with 24 2-byte entries providing palette
1187 redefinition support in 2- and 4-colour modes.
1188
1189 Enhancement: Display Synchronisation Interrupts
1190 -----------------------------------------------
1191
1192 When completing each scanline of the display, the ULA could trigger an
1193 interrupt. Since this might impact system performance substantially, the
1194 feature would probably need to be configurable, and it might be sufficient to
1195 have an interrupt only after a certain number of display lines instead.
1196 Permitting the CPU to take action after eight lines would allow palette
1197 switching and other effects to occur on a character row basis.
1198
1199 The ULA provides an interrupt at the end of the display period, presumably so
1200 that software can schedule updates to the screen, avoid flickering or tearing,
1201 and so on. However, some applications might benefit from an interrupt at, or
1202 just before, the start of the display period so that palette modifications or
1203 similar effects could be scheduled.
1204
1205 Enhancement: Palette-Free Modes
1206 -------------------------------
1207
1208 Palette-free modes might be defined where bit values directly correspond to
1209 the red, green and blue channels, although this would mostly make sense only
1210 for modes with depths greater than the standard 4 bits per pixel, and such
1211 modes would require more memory than MODE 2 if they were to have an acceptable
1212 resolution.
1213
1214 Enhancement: Display Suspend
1215 ----------------------------
1216
1217 Especially when writing to the screen memory, it could be beneficial to be
1218 able to suspend the ULA's access to the memory, instead producing blank values
1219 for all screen pixels until a program is ready to reveal the screen. This is
1220 different from palette blanking since with a blank palette, the ULA is still
1221 reading screen memory and translating its contents into pixel values that end
1222 up being blank.
1223
1224 This function is reminiscent of a capability of the ZX81, albeit necessary on
1225 that hardware to reduce the load on the system CPU which was responsible for
1226 producing the video output. By allowing display suspend on the Electron, the
1227 performance benefit would be derived from giving the CPU full access to the
1228 memory bandwidth.
1229
1230 Note that since the CPU is only able to access RAM at 1MHz, there is no
1231 possibility to improve performance beyond that achieved in MODE 4, 5 or 6
1232 normally. However, if faster RAM access were to be made possible (see the
1233 discussion of 8-bit wide RAM access), the CPU could benefit from freeing up
1234 the ULA's access slots entirely.
1235
1236 The region blanking feature mentioned above could be implemented using this
1237 enhancement instead of employing palette blanking for the affected lines of
1238 the display.
1239
1240 Enhancement: Memory Filling
1241 ---------------------------
1242
1243 A capability that could be given to an enhanced ULA is that of permitting the
1244 ULA to write to screen memory as well being able to read from it. Although
1245 such a capability would probably not be useful in conjunction with the
1246 existing read operations when producing a screen display, and insufficient
1247 bandwidth would exist to do so in high-bandwidth screen modes anyway, the
1248 capability could be offered during a display suspend period (as described
1249 above), permitting a more efficient mechanism to rapidly fill memory with a
1250 predetermined value.
1251
1252 This capability could also support block filling, where the limits of the
1253 filled memory would be defined by the position and size of a screen area,
1254 although this would demand the provision of additional registers in the ULA to
1255 retain the details of such areas and additional logic to control the fill
1256 operation.
1257
1258 Enhancement: Region Filling
1259 ---------------------------
1260
1261 An alternative to memory writing might involve indicating regions using
1262 additional registers or memory where the ULA fills regions of the screen with
1263 content instead of reading from memory. Unlike hardware sprites which should
1264 realistically provide varied content, region filling could employ single
1265 colours or patterns, and one advantage of doing so would be that the ULA need
1266 not access memory at all within a particular region.
1267
1268 Regions would be defined on a row-by-row basis. Instead of reading memory and
1269 blitting a direct representation to the screen, the ULA would read region
1270 definitions containing a start column, region width and colour details. There
1271 might be a certain number of definitions allowed per row, or the ULA might
1272 just traverse an ordered list of such definitions with each one indicating the
1273 row, start column, region width and colour details.
1274
1275 One could even compress this information further by requiring only the row,
1276 start column and colour details with each subsequent definition terminating
1277 the effect of the previous one. However, one would also need to consider the
1278 convenience of preparing such definitions and whether efficient access to
1279 definitions for a particular row might be desirable. It might also be
1280 desirable to avoid having to prepare definitions for "empty" areas of the
1281 screen, effectively making the definition of the screen contents employ
1282 run-length encoding and employ only colour plus length information.
1283
1284 One application of region filling is that of simple 2D and 3D shape rendering.
1285 Although it is entirely possible to plot such shapes to the screen and have
1286 the ULA blit the memory contents to the screen, such operations consume
1287 bandwidth both in the initial plotting and in the final transfer to the
1288 screen. Region filling would reduce such bandwidth usage substantially.
1289
1290 This way of representing screen images would make certain kinds of images
1291 unfeasible to represent - consider alternating single pixel values which could
1292 easily occur in some character bitmaps - even if an internal queue of regions
1293 were to be supported such that the ULA could read ahead and buffer such
1294 "bandwidth intensive" areas. Thus, the ULA might be better served providing
1295 this feature for certain areas of the display only as some kind of special
1296 graphics window.
1297
1298 Enhancement: Hardware Sprites
1299 -----------------------------
1300
1301 An enhanced ULA might provide hardware sprites, but this would be done in an
1302 way that is incompatible with the standard ULA, since no &FE*X locations are
1303 available for allocation. To keep the facility simple, hardware sprites would
1304 have a standard byte width and height.
1305
1306 The specification of sprites could involve the reservation of 16 locations
1307 (for example, &FE20-F) specifying a fixed number of eight sprites, with each
1308 location pair referring to the sprite data. By limiting the ULA to dealing
1309 with a fixed number of sprites, the work required inside the ULA would be
1310 reduced since it would avoid having to deal with arbitrary numbers of sprites.
1311
1312 The principal limitation on providing hardware sprites is that of having to
1313 obtain sprite data, given that the ULA is usually required to retrieve screen
1314 data, and given the lack of memory bandwidth available to retrieve sprite data
1315 (particularly from multiple sprites supposedly at the same position) and
1316 screen data simultaneously. Although the ULA could potentially read sprite
1317 data and screen data in alternate memory accesses in screen modes where the
1318 bandwidth is not already fully utilised, this would result in a degradation of
1319 performance.
1320
1321 Enhancement: Additional Screen Mode Configurations
1322 --------------------------------------------------
1323
1324 Alternative screen mode configurations could be supported. The ULA has to
1325 produce 640 pixel values across the screen, with pixel doubling or quadrupling
1326 employed to fill the screen width:
1327
1328 Screen width Columns Scaling Depth Bytes
1329 ------------ ------- ------- ----- -----
1330 640 80 x1 1 80
1331 320 40 x2 1, 2 40, 80
1332 160 20 x4 2, 4 40, 80
1333
1334 It must also use at most 80 byte-sized memory accesses to provide the
1335 information for the display. Given that characters must occupy an 8x8 pixel
1336 array, if a configuration featuring anything other than 20, 40 or 80 character
1337 columns is to be supported, compromises must be made such as the introduction
1338 of blank pixels either between characters (such as occurs between rows in MODE
1339 3 and 6) or at the end of a scanline (such as occurs at the end of the frame
1340 in MODE 3 and 6). Consider the following configuration:
1341
1342 Screen width Columns Scaling Depth Bytes Blank
1343 ------------ ------- ------- ----- ------ -----
1344 208 26 x3 1, 2 26, 52 16
1345
1346 Here, if the ULA can triple pixels, a 26 column mode with either 2 or 4
1347 colours could be provided, with 16 blank pixel values (out of a total of 640)
1348 generated either at the start or end (or split between the start and end) of
1349 each scanline.
1350
1351 Enhancement: Character Attributes
1352 ---------------------------------
1353
1354 The BBC Micro MODE 7 employs something resembling character attributes to
1355 support teletext displays, but depends on circuitry providing a character
1356 generator. The ZX Spectrum, on the other hand, provides character attributes
1357 as a means of colouring bitmapped graphics. Although such a feature is very
1358 limiting as the sole means of providing multicolour graphics, in situations
1359 where the choice is between low resolution multicolour graphics or high
1360 resolution monochrome graphics, character attributes provide a potentially
1361 useful compromise.
1362
1363 For each byte read, the ULA must deliver 8 pixel values (out of a total of
1364 640) to the video output, doing so by either emptying its pixel buffer on a
1365 pixel per cycle basis, or by multiplying pixels and thus holding them for more
1366 than one cycle. For example for a screen mode having 640 pixels in width:
1367
1368 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1369 Reads: B B
1370 Pixels: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
1371
1372 And for a screen mode having 320 pixels in width:
1373
1374 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1375 Reads: B
1376 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
1377
1378 However, in modes where less than 80 bytes are required to generate the pixel
1379 values, an enhanced ULA might be able to read additional bytes between those
1380 providing the bitmapped graphics data:
1381
1382 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1383 Reads: B A
1384 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
1385
1386 These additional bytes could provide colour information for the bitmapped data
1387 in the following character column (of 8 pixels). Since it would be desirable
1388 to apply attribute data to the first column, the initial 8 cycles might be
1389 configured to not produce pixel values.
1390
1391 For an entire character, attribute data need only be read for the first row of
1392 pixels for a character. The subsequent rows would have attribute information
1393 applied to them, although this would require the attribute data to be stored
1394 in some kind of buffer. Thus, the following access pattern would be observed:
1395
1396 Reads: A B _ B _ B _ B _ B _ B _ B _ B ...
1397
1398 In modes 3 and 6, the blank display lines could be used to retrieve attribute
1399 data:
1400
1401 Reads (blank): A _ A _ A _ A _ A _ A _ A _ A _ ...
1402 Reads (active): B _ B _ B _ B _ B _ B _ B _ B _ ...
1403 Reads (active): B _ B _ B _ B _ B _ B _ B _ B _ ...
1404 ...
1405
1406 See below for a discussion of using this for character data as well.
1407
1408 A whole byte used for colour information for a whole character would result in
1409 a choice of 256 colours, and this might be somewhat excessive. By only reading
1410 attribute bytes at every other opportunity, a choice of 16 colours could be
1411 applied individually to two characters.
1412
1413 Cycle: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
1414 Reads: B A B -
1415 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
1416
1417 Further reductions in attribute data access, offering 4 colours for every
1418 character in a four character block, for example, might also be worth
1419 considering.
1420
1421 Consider the following configurations for screen modes with a colour depth of
1422 1 bit per pixel for bitmap information:
1423
1424 Screen width Columns Scaling Bytes (B) Bytes (A) Colours Screen start
1425 ------------ ------- ------- --------- --------- ------- ------------
1426 320 40 x2 40 40 256 &5300
1427 320 40 x2 40 20 16 &5580 -> &5500
1428 320 40 x2 40 10 4 &56C0 -> &5600
1429 208 26 x3 26 26 256 &62C0 -> &6200
1430 208 26 x3 26 13 16 &6460 -> &6400
1431
1432 Enhancement: Text-Only Modes using Character and Attribute Data
1433 ---------------------------------------------------------------
1434
1435 In modes 3 and 6, the blank display lines could be used to retrieve character
1436 and attribute data instead of trying to insert it between bitmap data accesses,
1437 but this data would then need to be retained:
1438
1439 Reads: A C A C A C A C A C A C A C A C ...
1440 Reads: B _ B _ B _ B _ B _ B _ B _ B _ ...
1441
1442 Only attribute (A) and character (C) reads would require screen memory
1443 storage. Bitmap data reads (B) would involve either accesses to memory to
1444 obtain character definition details or could, at the cost of special storage
1445 in the ULA, involve accesses within the ULA that would then free up the RAM.
1446 However, the CPU would not benefit from having any extra access slots due to
1447 the limitations of the RAM access mechanism.
1448
1449 A scheme without caching might be possible. The same line of memory addresses
1450 might be visited over and over again for eight display lines, with an index
1451 into the bitmap data being incremented from zero to seven. The access patterns
1452 would look like this:
1453
1454 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 0)
1455 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 1)
1456 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 2)
1457 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 3)
1458 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 4)
1459 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 5)
1460 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 6)
1461 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 7)
1462
1463 The bandwidth requirements would be the sum of the accesses to read the
1464 character values (repeatedly) and those to read the bitmap data to reproduce
1465 the characters on screen.
1466
1467 Enhancement: MODE 7 Emulation using Character Attributes
1468 --------------------------------------------------------
1469
1470 If the scheme of applying attributes to character regions were employed to
1471 emulate MODE 7, in conjunction with the MODE 6 display technique, the
1472 following configuration would be required:
1473
1474 Screen width Columns Rows Bytes (B) Bytes (A) Colours Screen start
1475 ------------ ------- ---- --------- --------- ------- ------------
1476 320 40 25 40 20 16 &5ECC -> &5E00
1477 320 40 25 40 10 4 &5FC6 -> &5F00
1478
1479 Although this requires much more memory than MODE 7 (8500 bytes versus MODE
1480 7's 1000 bytes), it does not need much more memory than MODE 6, and it would
1481 at least make a limited 40-column multicolour mode available as a substitute
1482 for MODE 7.
1483
1484 Using the text-only enhancement with caching of data or with repeated reads of
1485 the same character data line for eight display lines, the storage requirements
1486 would be diminished substantially:
1487
1488 Screen width Columns Rows Bytes (C) Bytes (A) Colours Screen start
1489 ------------ ------- ---- --------- --------- ------- ------------
1490 320 40 25 40 20 16 &7A94 -> &7A00
1491 320 40 25 40 10 4 &7B1E -> &7B00
1492 320 40 25 40 5 2 &7B9B -> &7B00
1493 320 40 25 40 0 (2) &7C18 -> &7C00
1494 640 80 25 80 40 16 &7448 -> &7400
1495 640 80 25 80 20 4 &763C -> &7600
1496 640 80 25 80 10 2 &7736 -> &7700
1497 640 80 25 80 0 (2) &7830 -> &7800
1498
1499 Note that the colours describe the locally defined attributes for each
1500 character. When no attribute information is provided, the colours are defined
1501 globally.
1502
1503 Enhancement: Character Generator Support and Vertical Scaling
1504 -------------------------------------------------------------
1505
1506 When generating a picture, the ULA traverses screen memory, obtaining 40 or 80
1507 bytes of pixel data for each scanline. It then proceeds to the next row of
1508 pixel data for each successive scanline, with the exception of the text modes
1509 where scanlines may be blank (for which the row address does not advance).
1510 This arrangement provides a conventional bitmapped graphics display.
1511
1512 However, the ULA could instead facilitate the use of character generators. The
1513 principles involved can be demonstrated by the Jafa Mode 7 Mark 2 Display Unit
1514 expansion for the Electron which feeds the pixel data from a MODE 4 screen to
1515 a SAA5050 character generator to create a MODE 7 display. The solution adopted
1516 involves the replication of 40 bytes of character data across as many pixel
1517 rows as is necessary for the character generator to receive the appropriate
1518 character data for all scanlines in any given character row. If only a single
1519 40-byte row of character data were to be present for the first scanline of a
1520 character row, the character generator would only produce the first scanline
1521 (or the uppermost pixels of the characters) correctly, with the rest of the
1522 character shapes being ill-defined.
1523
1524 Here, the ULA could facilitate the use of memory-efficient character mode
1525 representations (such as MODE 7) by holding the row address for a number of
1526 scanlines, thus providing the same row of screen data for those scanlines,
1527 then advancing to the next row. Visualised in terms of pixel data, it would be
1528 like providing a display with a very low vertical resolution. Indeed, being
1529 able to reduce the vertical resolution of a display mode by a factor of eight
1530 or ten would be equivalent to the above character generation technique in
1531 terms of the ULA's screen reading activities.
1532
1533 By combining this vertical scaling or scanline replication with a circuit
1534 switchable between bitmapped graphics output and character graphics output,
1535 MODE 7 support could be made available, potentially as a hardware option
1536 separate from the ULA.
1537
1538 Enhancement: Compressed Character Data
1539 --------------------------------------
1540
1541 Another observation about text-only modes is that they only need to store a
1542 restricted set of bitmapped data values. Encoding this set of values in a
1543 smaller unit of storage than a byte could possibly help to reduce the amount
1544 of storage and bandwidth required to reproduce the characters on the display.
1545
1546 Enhancement: High Resolution Graphics
1547 -------------------------------------
1548
1549 Screen modes with higher resolutions and larger colour depths might be
1550 possible, but this would in most cases involve the allocation of more screen
1551 memory, and the ULA would probably then be obliged to page in such memory for
1552 the CPU to be able to sensibly access it all.
1553
1554 Enhancement: Genlock Support
1555 ----------------------------
1556
1557 The ULA generates a video signal in conjunction with circuitry producing the
1558 output features necessary for the correct display of the screen image.
1559 However, it appears that the ULA drives the video synchronisation mechanism
1560 instead of reacting to an existing signal. Genlock support might be possible
1561 if the ULA were made to be responsive to such external signals, resetting its
1562 address generators upon receiving synchronisation events.
1563
1564 Enhancement: Improved Sound
1565 ---------------------------
1566
1567 The standard ULA reserves &FE*6 for sound generation and cassette input/output
1568 (with bits 1 and 2 of &FE*7 being used to select either sound generation or
1569 cassette I/O), thus making it impossible to support multiple channels within
1570 the given framework. The BBC Micro ULA employs &FE40-&FE4F for sound control,
1571 and an enhanced ULA could adopt this interface.
1572
1573 The BBC Micro uses the SN76489 chip to produce sound, and the entire
1574 functionality of this chip could be emulated for enhanced sound, with a subset
1575 of the functionality exposed via the &FE*6 interface.
1576
1577 See: http://en.wikipedia.org/wiki/Texas_Instruments_SN76489
1578 See: http://www.smspower.org/Development/SN76489
1579
1580 Enhancement: Waveform Upload
1581 ----------------------------
1582
1583 As with a hardware sprite function, waveforms could be uploaded or referenced
1584 using locations as registers referencing memory regions.
1585
1586 Enhancement: Sound Input/Output
1587 -------------------------------
1588
1589 Since the ULA already controls audio input/output for cassette-based data, it
1590 would have been interesting to entertain the idea of sampling and output of
1591 sounds through the cassette interface. However, a significant amount of
1592 circuitry is employed to process the input signal for use by the ULA and to
1593 process the output signal for recording.
1594
1595 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw_03.htm#3.11
1596
1597 Enhancement: BBC ULA Compatibility
1598 ----------------------------------
1599
1600 Although some new ULA functions could be defined in a way that is also
1601 compatible with the BBC Micro, the BBC ULA is itself incompatible with the
1602 Electron ULA: &FE00-7 is reserved for the video controller in the BBC memory
1603 map, but controls various functions specific to the 6845 video controller;
1604 &FE08-F is reserved for the serial controller. It therefore becomes possible
1605 to disregard compatibility where compatibility is already disregarded for a
1606 particular area of functionality.
1607
1608 &FE20-F maps to video ULA functionality on the BBC Micro which provides
1609 control over the palette (using address &FE21, compared to &FE07-F on the
1610 Electron) and other system-specific functions. Since the location usage is
1611 generally incompatible, this region could be reused for other purposes.
1612
1613 Enhancement: Increased RAM, ULA and CPU Performance
1614 ---------------------------------------------------
1615
1616 More modern implementations of the hardware might feature faster RAM coupled
1617 with an increased ULA clock frequency in order to increase the bandwidth
1618 available to the ULA and to the CPU in situations where the ULA is not needed
1619 to perform work. A ULA employing a 32MHz clock would be able to complete the
1620 retrieval of a byte from RAM in only 250ns and thus be able to enable the CPU
1621 to access the RAM for the following 250ns even in display modes requiring the
1622 retrieval of a byte for the display every 500ns. The CPU could, subject to
1623 timing issues, run at 2MHz even in MODE 0, 1 and 2.
1624
1625 A scheme such as that described above would have a similar effect to the
1626 scheme employed in the BBC Micro, although the latter made use of RAM with a
1627 wider bandwidth in order to complete memory transfers within 250ns and thus
1628 permit the CPU to run continuously at 2MHz.
1629
1630 Higher bandwidth could potentially be used to implement exotic features such
1631 as RAM-resident hardware sprites or indeed any feature demanding RAM access
1632 concurrent with the production of the display image.
1633
1634 Enhancement: Multiple CPU Stacks and Zero Pages
1635 -----------------------------------------------
1636
1637 The 6502 maintains a stack for subroutine calls and register storage in page
1638 &01. Although the stack register can be manipulated using the TSX and TXS
1639 instructions, thereby permitting the maintenance of multiple stack regions and
1640 thus the potential coexistence of multiple programs each using a separate
1641 region, only programs that make little use of the stack (perhaps avoiding
1642 deeply-nested subroutine invocations and significant register storage) would
1643 be able to coexist without overwriting each other's stacks.
1644
1645 One way that this issue could be alleviated would involve the provision of a
1646 facility to redirect accesses to page &01 to other areas of memory. The ULA
1647 would provide a register that defines a physical page for the use of the CPU's
1648 "logical" page &01, and upon any access to page &01 by the CPU, the ULA would
1649 change the asserted address lines to redirect the access to the appropriate
1650 physical region.
1651
1652 By providing an 8-bit register, mapping to the most significant byte (MSB) of
1653 a 16-bit address, the ULA could then replace any MSB equal to &01 with the
1654 register value before the access is made. Where multiple programs coexist,
1655 upon switching programs, the register would be updated to point the ULA to the
1656 appropriate stack location, thus providing a simple memory management unit
1657 (MMU) capability.
1658
1659 In a similar fashion, zero page accesses could also be redirected so that code
1660 could run from sideways RAM and have zero page operations redirected to "upper
1661 memory" - for example, to page &BE (with stack accesses redirected to page
1662 &BF, perhaps) - thereby permitting most CPU operations to occur without
1663 inadvertent accesses to "lower memory" (the RAM) which would risk stalling the
1664 CPU as it contends with the ULA for memory access.
1665
1666 Such facilities could also be provided by a separate circuit between the CPU
1667 and ULA in a fashion similar to that employed by a "turbo" board, but unlike
1668 such boards, no additional RAM would be provided: all memory accesses would
1669 occur as normal through the ULA, albeit redirected when configured
1670 appropriately.
1671
1672 ULA Pin Functions
1673 -----------------
1674
1675 The functions of the ULA pins are described in the Electron Service Manual. Of
1676 interest to video processing are the following:
1677
1678 CSYNC (low during horizontal or vertical synchronisation periods, high
1679 otherwise)
1680
1681 HS (low during horizontal synchronisation periods, high otherwise)
1682
1683 RED, GREEN, BLUE (pixel colour outputs)
1684
1685 CLOCK IN (a 16MHz clock input, 4V peak to peak)
1686
1687 PHI OUT (a 1MHz, 2MHz and stopped clock signal for the CPU)
1688
1689 More general memory access pins:
1690
1691 RAM0...RAM3 (data lines to/from the RAM)
1692
1693 RA0...RA7 (address lines for sending both row and column addresses to the RAM)
1694
1695 RAS (row address strobe setting the row address on a negative edge - see the
1696 timing notes)
1697
1698 CAS (column address strobe setting the column address on a negative edge -
1699 see the timing notes)
1700
1701 WE (sets write enable with logic 0, read with logic 1)
1702
1703 ROM (select data access from ROM)
1704
1705 CPU-oriented memory access pins:
1706
1707 A0...A15 (CPU address lines)
1708
1709 PD0...PD7 (CPU data lines)
1710
1711 R/W (indicates CPU write with logic 0, CPU read with logic 1)
1712
1713 Interrupt-related pins:
1714
1715 NMI (CPU request for uninterrupted 1MHz access to memory)
1716
1717 IRQ (signal event to CPU)
1718
1719 POR (power-on reset, resetting the ULA on a positive edge and asserting the
1720 CPU's RST pin)
1721
1722 RST (master reset for the CPU signalled on power-up and by the Break key)
1723
1724 Keyboard-related pins:
1725
1726 KBD0...KBD3 (keyboard inputs)
1727
1728 CAPS LOCK (control status LED)
1729
1730 Sound-related pins:
1731
1732 SOUND O/P (sound output using internal oscillator)
1733
1734 Cassette-related pins:
1735
1736 CAS IN (cassette circuit input, between 0.5V to 2V peak to peak)
1737
1738 CAS OUT (pseudo-sinusoidal output, 1.8V peak to peak)
1739
1740 CAS RC (detect high tone)
1741
1742 CAS MO (motor relay output)
1743
1744 ÷13 IN (~1200 baud clock input)
1745
1746 ULA Socket
1747 ----------
1748
1749 The socket used for the ULA is a 3M/TexTool 268-5400 68-pin socket.
1750
1751 References
1752 ----------
1753
1754 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw.htm
1755
1756 About this Document
1757 -------------------
1758
1759 The most recent version of this document and accompanying distribution should
1760 be available from the following location:
1761
1762 http://hgweb.boddie.org.uk/ULA
1763
1764 Copyright and licence information can be found in the docs directory of this
1765 distribution - see docs/COPYING.txt for more information.