1 Timing
2 ------
3
4 According to the above (15.3.2 in the AUG), there are 312 scanlines, 256 of
5 which are used to generate pixel data. At 50Hz, this means that 128 cycles are
6 used to produce pixel data (2000000 / 50 = 40000; 40000 / 312 ~= 128). This is
7 consistent with the observation that each scanline requires at most 80 bytes
8 of data, and that the ULA is apparently busy for 40 out of 64 microseconds in
9 each scanline.
10
11 See: Acorn Electron Advanced User Guide
12 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
13
14 Access to RAM involves accessing four 64Kb dynamic RAM devices (IC4 to IC7,
15 each providing two bits of each byte) using two cycles within the 500ns period
16 of the 2MHz clock to complete each access operation.
17
18 See: Acorn Electron Service Manual
19
20 Hardware Scrolling
21 ------------------
22
23 On the standard ULA, &FE02 and &FE03 map to a 9 significant bits address with
24 the least significant 5 bits being zero, thus limiting the scrolling
25 resolution to 64 bytes. An enhanced ULA could support a resolution of 2 bytes
26 using the same layout of these addresses.
27
28 |--&FE02--------------| |--&FE03--------------|
29 XX XX 14 13 12 11 10 09 08 07 06 XX XX XX XX XX
30
31 XX 14 13 12 11 10 09 08 07 06 05 04 03 02 01 XX
32
33 Arguably, a resolution of 8 bytes is more useful, since the mapping of screen
34 memory to pixel locations is character oriented. A change in 8 bytes would
35 permit a horizontal scrolling resolution of 2 pixels in MODE 2, 4 pixels in
36 MODE 1 and 5, and 8 pixels in MODE 0, 3 and 6. This resolution is actually
37 observed on the BBC Micro (see 18.11.2 in the BBC Microcomputer Advanced User
38 Guide).
39
40 One argument for a 2 byte resolution is smooth vertical scrolling. A pitfall
41 of changing the screen address by 2 bytes is the change in the number of lines
42 from the initial and final character rows that need reading by the ULA, which
43 would need to maintain this state information (although this is a relatively
44 trivial change). Another pitfall is the complication that might be introduced
45 to software writing bitmaps of character height to the screen.
46
47 Region Blanking
48 ---------------
49
50 The problem of permitting character-oriented blitting in programs whilst
51 scrolling the screen by sub-character amounts could be mitigated by permitting
52 a region of the display to be blank, such as the final lines of the display.
53 Consider the following vertical scrolling by 2 bytes that would cause an
54 initial character row of 6 lines and a final character row of 2 lines:
55
56 6 lines - initial, partial character row
57 248 lines - 31 complete rows
58 2 lines - final, partial character row
59
60 If a routine were in use that wrote 8 line bitmaps to the partial character
61 row now split in two, it would be advisable to hide one of the regions in
62 order to prevent content appearing in the wrong place on screen (such as
63 content meant to appear at the top "leaking" onto the bottom). Blanking 6
64 lines would be sufficient, as can be seen from the following cases.
65
66 Scrolling up by 2 lines:
67
68 6 lines - initial, partial character row
69 240 lines - 30 complete rows
70 4 lines - part of 1 complete row
71 -----------------------------------------------------------------
72 4 lines - part of 1 complete row (hidden to maintain 250 lines)
73 2 lines - final, partial character row (hidden)
74
75 Scrolling down by 2 lines:
76
77 2 lines - initial, partial character row
78 248 lines - 31 complete rows
79 ----------------------------------------------------------
80 6 lines - final, partial character row (hidden)
81
82 Thus, in this case, region blanking would impose a 250 line display with the
83 bottom 6 lines blank.
84
85 Screen Height Adjustment
86 ------------------------
87
88 The height of the screen could be configurable in order to reduce screen
89 memory consumption. This is not quite done in MODE 3 and 6 since the start of
90 the screen appears to be rounded down to the nearest page, but by reducing the
91 height by amounts more than a page, savings would be possible. For example:
92
93 Screen width Depth Height Bytes per line Saving in bytes Start address
94 ------------ ----- ------ -------------- --------------- -------------
95 640 1 252 80 320 &3140 -> &3100
96 640 1 248 80 640 &3280 -> &3200
97 320 1 240 40 640 &5A80 -> &5A00
98 320 2 240 80 1280 &3500
99
100 Palette Definition
101 ------------------
102
103 Since all memory accesses go via the ULA, an enhanced ULA could employ more
104 specific addresses than &FE*X to perform enhanced functions. For example, the
105 palette control is done using &FE*8-F and merely involves selecting predefined
106 colours, whereas an enhanced ULA could support the redefinition of all 16
107 colours using specific ranges such as &FE18-F (colours 0 to 7) and &FE28-F
108 (colours 8 to 15), where a single byte might provide 8 bits per pixel colour
109 specifications similar to those used on the Archimedes.
110
111 The principal limitation here is actually the hardware: the Electron has only
112 a single output line for each of the red, green and blue channels, and if
113 those outputs are strictly digital and can only be set to a "high" and "low"
114 value, then only the existing eight colours are possible. If a modern ULA were
115 able to output analogue values, it would still need to be assessed whether the
116 circuitry could successfully handle and propagate such values.
117
118 Palette Definition Lists
119 ------------------------
120
121 It can be useful to redefine the palette in order to change the colours
122 available for a particular region of the screen, particularly in modes where
123 the choice of colours is constrained, and if an increased colour depth were
124 available, palette redefinition would be useful to give the illusion of more
125 than 16 colours in MODE 2. Traditionally, palette redefinition has been done
126 by using interrupt-driven timers, but a more efficient approach would involve
127 presenting lists of palette definitions to the ULA so that it can change the
128 palette at a particular display line.
129
130 One might define a palette redefinition list in a region of memory and then
131 communicate its contents to the ULA by writing the address and length of the
132 list, along with the display line at which the palette is to be changed, to
133 ULA registers such that the ULA buffers the list and performs the redefinition
134 at the appropriate time. Throughput/bandwidth considerations might impose
135 restrictions on the practical length of such a list, however.
136
137 Palette-Free Modes
138 ------------------
139
140 Palette-free modes might be defined where bit values directly correspond to
141 the red, green and blue channels, although this would mostly make sense only
142 for modes with depths greater than the standard 4 bits per pixel, and such
143 modes would require more memory than MODE 2 if they were to have an acceptable
144 resolution.
145
146 Display Suspend
147 ---------------
148
149 Especially when writing to the screen memory, it could be beneficial to be
150 able to suspend the ULA's access to the memory, instead producing blank values
151 for all screen pixels until a program is ready to reveal the screen. This is
152 different from palette blanking since with a blank palette, the ULA is still
153 reading screen memory and translating its contents into pixel values that end
154 up being blank.
155
156 This function is reminiscent of a capability of the ZX81, albeit necessary on
157 that hardware to reduce the load on the system CPU which was responsible for
158 producing the video output.
159
160 Hardware Sprites
161 ----------------
162
163 An enhanced ULA might provide hardware sprites, but this would be done in an
164 way that is incompatible with the standard ULA, since no &FE*X locations are
165 available for allocation. To keep the facility simple, hardware sprites would
166 have a standard byte width and height.
167
168 The specification of sprites could involve the reservation of 16 locations
169 (for example, &FE20-F) specifying a fixed number of eight sprites, with each
170 location pair referring to the sprite data. By limiting the ULA to dealing
171 with a fixed number of sprites, the work required inside the ULA would be
172 reduced since it would avoid having to deal with arbitrary numbers of sprites.
173
174 The principal limitation on providing hardware sprites is that of having to
175 obtain sprite data, given that the ULA is usually required to retrieve screen
176 data, and given the lack of memory bandwidth available to retrieve sprite data
177 (particularly from multiple sprites supposedly at the same position) and
178 screen data simultaneously. Although the ULA could potentially read sprite
179 data and screen data in alternate memory accesses in screen modes where the
180 bandwidth is not already fully utilised, this would result in a degradation of
181 performance.
182
183 Additional Screen Mode Configurations
184 -------------------------------------
185
186 Alternative screen mode configurations could be supported. The ULA has to
187 produce 640 pixel values across the screen, with pixel doubling or quadrupling
188 employed to fill the screen width:
189
190 Screen width Columns Scaling Depth Bytes
191 ------------ ------- ------- ----- -----
192 640 80 x1 1 80
193 320 40 x2 1, 2 40, 80
194 160 20 x4 2, 4 40, 80
195
196 It must also use at most 80 byte-sized memory accesses to provide the
197 information for the display. Given that characters must occupy an 8x8 pixel
198 array, if a configuration featuring anything other than 20, 40 or 80 character
199 columns is to be supported, compromises must be made such as the introduction
200 of blank pixels either between characters (such as occurs between rows in MODE
201 3 and 6) or at the end of a scanline (such as occurs at the end of the frame
202 in MODE 3 and 6). Consider the following configuration:
203
204 Screen width Columns Scaling Depth Bytes Blank
205 ------------ ------- ------- ----- ------ -----
206 208 26 x3 1, 2 26, 52 16
207
208 Here, if the ULA can triple pixels, a 26 column mode with either 2 or 4
209 colours could be provided, with 16 blank pixel values (out of a total of 640)
210 generated either at the start or end (or split between the start and end) of
211 each scanline.
212
213 Character Attributes
214 --------------------
215
216 The BBC Micro MODE 7 employs something resembling character attributes to
217 support teletext displays, but depends on circuitry providing a character
218 generator. The ZX Spectrum, on the other hand, provides character attributes
219 as a means of colouring bitmapped graphics. Although such a feature is very
220 limiting as the sole means of providing multicolour graphics, in situations
221 where the choice is between low resolution multicolour graphics or high
222 resolution monochrome graphics, character attributes provide a potentially
223 useful compromise.
224
225 For each byte read, the ULA must deliver 8 pixel values (out of a total of
226 640) to the video output, doing so by either emptying its pixel buffer on a
227 pixel per cycle basis, or by multiplying pixels and thus holding them for more
228 than one cycle. For example for a screen mode having 640 pixels in width:
229
230 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
231 Reads: B B
232 Pixels: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
233
234 And for a screen mode having 320 pixels in width:
235
236 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
237 Reads: B
238 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
239
240 However, in modes where less than 80 bytes are required to generate the pixel
241 values, an enhanced ULA might be able to read additional bytes between those
242 providing the bitmapped graphics data:
243
244 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
245 Reads: B A
246 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
247
248 These additional bytes could provide colour information for the bitmapped data
249 in the following character column (of 8 pixels). Since it would be desirable
250 to apply attribute data to the first column, the initial 8 cycles might be
251 configured to not produce pixel values.
252
253 For an entire character, attribute data need only be read for the first row of
254 pixels for a character. The subsequent rows would have attribute information
255 applied to them, although this would require the attribute data to be stored
256 in some kind of buffer. Thus, the following access pattern would be observed:
257
258 Cycle: A B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ...
259
260 A whole byte used for colour information for a whole character would result in
261 a choice of 256 colours, and this might be somewhat excessive. By only reading
262 attribute bytes at every other opportunity, a choice of 16 colours could be
263 applied individually to two characters.
264
265 Cycle: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
266 Reads: B A B -
267 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
268
269 Further reductions in attribute data access, offering 4 colours for every
270 character in a four character block, for example, might also be worth
271 considering.
272
273 Consider the following configurations for screen modes with a colour depth of
274 1 bit per pixel for bitmap information:
275
276 Screen width Columns Scaling Bytes (B) Bytes (A) Colours Screen start
277 ------------ ------- ------- --------- --------- ------- ------------
278 320 40 x2 40 40 256 &5300
279 320 40 x2 40 20 16 &5580 -> &5500
280 320 40 x2 40 10 4 &56C0 -> &5600
281 208 26 x3 26 26 256 &62C0 -> &6200
282 208 26 x3 26 13 16 &6460 -> &6400
283
284 MODE 7 Emulation using Character Attributes
285 -------------------------------------------
286
287 If the scheme of applying attributes to character regions were employed to
288 emulate MODE 7, in conjunction with the MODE 6 display technique, the
289 following configuration would be required:
290
291 Screen width Columns Rows Bytes (B) Bytes (A) Colours Screen start
292 ------------ ------- ---- --------- --------- ------- ------------
293 320 40 25 40 20 16 &5ECC -> &5E00
294 320 40 25 40 10 4 &5FC6 -> &5F00
295
296 Although this requires much more memory than MODE 7 (8500 bytes versus MODE
297 7's 1000 bytes), it does not need much more memory than MODE 6, and it would
298 at least make a limited 40-column multicolour mode available as a substitute
299 for MODE 7.
300
301 Enhanced Graphics and Mode Layouts
302 ----------------------------------
303
304 Screen modes with different screen memory mappings, higher resolutions and
305 larger colour depths might be possible, but this would in most cases involve
306 the allocation of more screen memory, and the ULA would probably then be
307 obliged to page in such memory for the CPU to be able to sensibly access it
308 all. Merely changing the memory mappings in order to have Archimedes-style
309 row-oriented screen addresses (instead of character-oriented addresses) could
310 be done for the existing modes, but this might not be sufficiently beneficial,
311 especially since accessing regions of the screen would involve incrementing
312 pointers by amounts that are inconvenient on an 8-bit CPU.
313
314 Enhanced Sound
315 --------------
316
317 The standard ULA reserves &FE*6 for sound generation and cassette
318 input/output, thus making it impossible to support multiple channels within
319 the given framework. The BBC Micro ULA employs &FE40-&FE4F for sound control,
320 and an enhanced ULA could adopt this interface.
321
322 The BBC Micro uses the SN76489 chip to produce sound, and the entire
323 functionality of this chip could be emulated for enhanced sound, with a subset
324 of the functionality exposed via the &FE*6 interface.
325
326 See: http://en.wikipedia.org/wiki/Texas_Instruments_SN76489
327
328 Waveform Upload
329 ---------------
330
331 As with a hardware sprite function, waveforms could be uploaded or referenced
332 using locations as registers referencing memory regions.
333
334 BBC ULA Compatibility
335 ---------------------
336
337 Although some new ULA functions could be defined in a way that is also
338 compatible with the BBC Micro, the BBC ULA is itself incompatible with the
339 Electron ULA: &FE00-7 is reserved for the video controller in the BBC memory
340 map, but controls various functions specific to the 6845 video controller;
341 &FE08-F is reserved for the serial controller. It therefore becomes possible
342 to disregard compatibility where compatibility is already disregarded for a
343 particular area of functionality.
344
345 &FE20-F maps to video ULA functionality on the BBC Micro which provides
346 control over the palette (using address &FE21, compared to &FE07-F on the
347 Electron) and other system-specific functions. Since the location usage is
348 generally incompatible, this region could be reused for other purposes.
349
350 ULA Pin Functions
351 -----------------
352
353 The functions of the ULA pins are described in the Electron Service Manual. Of
354 interest to video processing are the following:
355
356 CSYNC (low during horizontal or vertical synchronisation periods, high
357 otherwise)
358
359 HS (low during horizontal synchronisation periods, high otherwise)
360
361 RED, GREEN, BLUE (pixel colour outputs)
362
363 CLOCK IN (a 16MHz clock input, 4V peak to peak)
364
365 PHI OUT (a 1MHz, 2MHz and stopped clock signal for the CPU)
366
367 More general memory access pins:
368
369 RAM0...RAM3 (data lines to/from the RAM)
370
371 RA0...RA7 (address lines for sending both row and column addresses to the RAM)
372
373 RAS (row address strobe setting the row address on a negative edge)
374
375 CAS (column address strobe setting the column address on a negative edge)
376
377 WE (sets write enable with logic 0, read with logic 1)
378
379 ROM (select data access from ROM)
380
381 CPU-oriented memory access pins:
382
383 A0...A15 (CPU address lines)
384
385 PD0...PD7 (CPU data lines)
386
387 R/W (indicates CPU write with logic 0, CPU read with logic 1)
388
389 Interrupt-related pins:
390
391 NMI (CPU request for uninterrupted 1MHz access to memory)
392
393 IRQ (signal event to CPU)
394
395 POR (power-on reset, resetting the ULA on a positive edge and asserting the
396 CPU's RST pin)
397
398 RST (master reset for the CPU signalled on power-up and by the Break key)
399
400 Keyboard-related pins:
401
402 KBD0...KBD3 (keyboard inputs)
403
404 CAPS LOCK (control status LED)
405
406 Sound-related pins:
407
408 SOUND O/P (sound output using internal oscillator)
409
410 Cassette-related pins:
411
412 CAS IN (cassette circuit input, between 0.5V to 2V peak to peak)
413
414 CAS OUT (pseudo-sinusoidal output, 1.8V peak to peak)
415
416 CAS RC (detect high tone)
417
418 CAS MO (motor relay output)
419
420 ÷13 IN (~1200 baud clock input)