1 Timing
2 ------
3
4 According to the above (15.3.2 in the AUG), there are 312 scanlines, 256 of
5 which are used to generate pixel data. At 50Hz, this means that 128 cycles are
6 used to produce pixel data (2000000 / 50 = 40000; 40000 / 312 ~= 128). This is
7 consistent with the observation that each scanline requires at most 80 bytes
8 of data, and that the ULA is apparently busy for 40 out of 64 microseconds in
9 each scanline.
10
11 See: Acorn Electron Advanced User Guide
12 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
13
14 Access to RAM involves accessing four 64Kb dynamic RAM devices (IC4 to IC7,
15 each providing two bits of each byte) using two cycles within the 500ns period
16 of the 2MHz clock to complete each access operation. Since the CPU and ULA
17 have to take turns in accessing the RAM in MODE 4, 5 and 6, the CPU must
18 effectively run at 1MHz (since every other 500ns period involves the ULA
19 accessing RAM). The CPU is driven by an external clock (IC8) whose 16MHz
20 frequency is divided by the ULA (IC1) depending on the screen mode in use.
21
22 See: Acorn Electron Service Manual
23
24 Hardware Scrolling
25 ------------------
26
27 On the standard ULA, &FE02 and &FE03 map to a 9 significant bits address with
28 the least significant 5 bits being zero, thus limiting the scrolling
29 resolution to 64 bytes. An enhanced ULA could support a resolution of 2 bytes
30 using the same layout of these addresses.
31
32 |--&FE02--------------| |--&FE03--------------|
33 XX XX 14 13 12 11 10 09 08 07 06 XX XX XX XX XX
34
35 XX 14 13 12 11 10 09 08 07 06 05 04 03 02 01 XX
36
37 Arguably, a resolution of 8 bytes is more useful, since the mapping of screen
38 memory to pixel locations is character oriented. A change in 8 bytes would
39 permit a horizontal scrolling resolution of 2 pixels in MODE 2, 4 pixels in
40 MODE 1 and 5, and 8 pixels in MODE 0, 3 and 6. This resolution is actually
41 observed on the BBC Micro (see 18.11.2 in the BBC Microcomputer Advanced User
42 Guide).
43
44 One argument for a 2 byte resolution is smooth vertical scrolling. A pitfall
45 of changing the screen address by 2 bytes is the change in the number of lines
46 from the initial and final character rows that need reading by the ULA, which
47 would need to maintain this state information (although this is a relatively
48 trivial change). Another pitfall is the complication that might be introduced
49 to software writing bitmaps of character height to the screen.
50
51 Region Blanking
52 ---------------
53
54 The problem of permitting character-oriented blitting in programs whilst
55 scrolling the screen by sub-character amounts could be mitigated by permitting
56 a region of the display to be blank, such as the final lines of the display.
57 Consider the following vertical scrolling by 2 bytes that would cause an
58 initial character row of 6 lines and a final character row of 2 lines:
59
60 6 lines - initial, partial character row
61 248 lines - 31 complete rows
62 2 lines - final, partial character row
63
64 If a routine were in use that wrote 8 line bitmaps to the partial character
65 row now split in two, it would be advisable to hide one of the regions in
66 order to prevent content appearing in the wrong place on screen (such as
67 content meant to appear at the top "leaking" onto the bottom). Blanking 6
68 lines would be sufficient, as can be seen from the following cases.
69
70 Scrolling up by 2 lines:
71
72 6 lines - initial, partial character row
73 240 lines - 30 complete rows
74 4 lines - part of 1 complete row
75 -----------------------------------------------------------------
76 4 lines - part of 1 complete row (hidden to maintain 250 lines)
77 2 lines - final, partial character row (hidden)
78
79 Scrolling down by 2 lines:
80
81 2 lines - initial, partial character row
82 248 lines - 31 complete rows
83 ----------------------------------------------------------
84 6 lines - final, partial character row (hidden)
85
86 Thus, in this case, region blanking would impose a 250 line display with the
87 bottom 6 lines blank.
88
89 Screen Height Adjustment
90 ------------------------
91
92 The height of the screen could be configurable in order to reduce screen
93 memory consumption. This is not quite done in MODE 3 and 6 since the start of
94 the screen appears to be rounded down to the nearest page, but by reducing the
95 height by amounts more than a page, savings would be possible. For example:
96
97 Screen width Depth Height Bytes per line Saving in bytes Start address
98 ------------ ----- ------ -------------- --------------- -------------
99 640 1 252 80 320 &3140 -> &3100
100 640 1 248 80 640 &3280 -> &3200
101 320 1 240 40 640 &5A80 -> &5A00
102 320 2 240 80 1280 &3500
103
104 Palette Definition
105 ------------------
106
107 Since all memory accesses go via the ULA, an enhanced ULA could employ more
108 specific addresses than &FE*X to perform enhanced functions. For example, the
109 palette control is done using &FE*8-F and merely involves selecting predefined
110 colours, whereas an enhanced ULA could support the redefinition of all 16
111 colours using specific ranges such as &FE18-F (colours 0 to 7) and &FE28-F
112 (colours 8 to 15), where a single byte might provide 8 bits per pixel colour
113 specifications similar to those used on the Archimedes.
114
115 The principal limitation here is actually the hardware: the Electron has only
116 a single output line for each of the red, green and blue channels, and if
117 those outputs are strictly digital and can only be set to a "high" and "low"
118 value, then only the existing eight colours are possible. If a modern ULA were
119 able to output analogue values, it would still need to be assessed whether the
120 circuitry could successfully handle and propagate such values.
121
122 Palette Definition Lists
123 ------------------------
124
125 It can be useful to redefine the palette in order to change the colours
126 available for a particular region of the screen, particularly in modes where
127 the choice of colours is constrained, and if an increased colour depth were
128 available, palette redefinition would be useful to give the illusion of more
129 than 16 colours in MODE 2. Traditionally, palette redefinition has been done
130 by using interrupt-driven timers, but a more efficient approach would involve
131 presenting lists of palette definitions to the ULA so that it can change the
132 palette at a particular display line.
133
134 One might define a palette redefinition list in a region of memory and then
135 communicate its contents to the ULA by writing the address and length of the
136 list, along with the display line at which the palette is to be changed, to
137 ULA registers such that the ULA buffers the list and performs the redefinition
138 at the appropriate time. Throughput/bandwidth considerations might impose
139 restrictions on the practical length of such a list, however.
140
141 Palette-Free Modes
142 ------------------
143
144 Palette-free modes might be defined where bit values directly correspond to
145 the red, green and blue channels, although this would mostly make sense only
146 for modes with depths greater than the standard 4 bits per pixel, and such
147 modes would require more memory than MODE 2 if they were to have an acceptable
148 resolution.
149
150 Display Suspend
151 ---------------
152
153 Especially when writing to the screen memory, it could be beneficial to be
154 able to suspend the ULA's access to the memory, instead producing blank values
155 for all screen pixels until a program is ready to reveal the screen. This is
156 different from palette blanking since with a blank palette, the ULA is still
157 reading screen memory and translating its contents into pixel values that end
158 up being blank.
159
160 This function is reminiscent of a capability of the ZX81, albeit necessary on
161 that hardware to reduce the load on the system CPU which was responsible for
162 producing the video output.
163
164 Hardware Sprites
165 ----------------
166
167 An enhanced ULA might provide hardware sprites, but this would be done in an
168 way that is incompatible with the standard ULA, since no &FE*X locations are
169 available for allocation. To keep the facility simple, hardware sprites would
170 have a standard byte width and height.
171
172 The specification of sprites could involve the reservation of 16 locations
173 (for example, &FE20-F) specifying a fixed number of eight sprites, with each
174 location pair referring to the sprite data. By limiting the ULA to dealing
175 with a fixed number of sprites, the work required inside the ULA would be
176 reduced since it would avoid having to deal with arbitrary numbers of sprites.
177
178 The principal limitation on providing hardware sprites is that of having to
179 obtain sprite data, given that the ULA is usually required to retrieve screen
180 data, and given the lack of memory bandwidth available to retrieve sprite data
181 (particularly from multiple sprites supposedly at the same position) and
182 screen data simultaneously. Although the ULA could potentially read sprite
183 data and screen data in alternate memory accesses in screen modes where the
184 bandwidth is not already fully utilised, this would result in a degradation of
185 performance.
186
187 Additional Screen Mode Configurations
188 -------------------------------------
189
190 Alternative screen mode configurations could be supported. The ULA has to
191 produce 640 pixel values across the screen, with pixel doubling or quadrupling
192 employed to fill the screen width:
193
194 Screen width Columns Scaling Depth Bytes
195 ------------ ------- ------- ----- -----
196 640 80 x1 1 80
197 320 40 x2 1, 2 40, 80
198 160 20 x4 2, 4 40, 80
199
200 It must also use at most 80 byte-sized memory accesses to provide the
201 information for the display. Given that characters must occupy an 8x8 pixel
202 array, if a configuration featuring anything other than 20, 40 or 80 character
203 columns is to be supported, compromises must be made such as the introduction
204 of blank pixels either between characters (such as occurs between rows in MODE
205 3 and 6) or at the end of a scanline (such as occurs at the end of the frame
206 in MODE 3 and 6). Consider the following configuration:
207
208 Screen width Columns Scaling Depth Bytes Blank
209 ------------ ------- ------- ----- ------ -----
210 208 26 x3 1, 2 26, 52 16
211
212 Here, if the ULA can triple pixels, a 26 column mode with either 2 or 4
213 colours could be provided, with 16 blank pixel values (out of a total of 640)
214 generated either at the start or end (or split between the start and end) of
215 each scanline.
216
217 Character Attributes
218 --------------------
219
220 The BBC Micro MODE 7 employs something resembling character attributes to
221 support teletext displays, but depends on circuitry providing a character
222 generator. The ZX Spectrum, on the other hand, provides character attributes
223 as a means of colouring bitmapped graphics. Although such a feature is very
224 limiting as the sole means of providing multicolour graphics, in situations
225 where the choice is between low resolution multicolour graphics or high
226 resolution monochrome graphics, character attributes provide a potentially
227 useful compromise.
228
229 For each byte read, the ULA must deliver 8 pixel values (out of a total of
230 640) to the video output, doing so by either emptying its pixel buffer on a
231 pixel per cycle basis, or by multiplying pixels and thus holding them for more
232 than one cycle. For example for a screen mode having 640 pixels in width:
233
234 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
235 Reads: B B
236 Pixels: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
237
238 And for a screen mode having 320 pixels in width:
239
240 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
241 Reads: B
242 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
243
244 However, in modes where less than 80 bytes are required to generate the pixel
245 values, an enhanced ULA might be able to read additional bytes between those
246 providing the bitmapped graphics data:
247
248 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
249 Reads: B A
250 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
251
252 These additional bytes could provide colour information for the bitmapped data
253 in the following character column (of 8 pixels). Since it would be desirable
254 to apply attribute data to the first column, the initial 8 cycles might be
255 configured to not produce pixel values.
256
257 For an entire character, attribute data need only be read for the first row of
258 pixels for a character. The subsequent rows would have attribute information
259 applied to them, although this would require the attribute data to be stored
260 in some kind of buffer. Thus, the following access pattern would be observed:
261
262 Cycle: A B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ...
263
264 A whole byte used for colour information for a whole character would result in
265 a choice of 256 colours, and this might be somewhat excessive. By only reading
266 attribute bytes at every other opportunity, a choice of 16 colours could be
267 applied individually to two characters.
268
269 Cycle: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
270 Reads: B A B -
271 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
272
273 Further reductions in attribute data access, offering 4 colours for every
274 character in a four character block, for example, might also be worth
275 considering.
276
277 Consider the following configurations for screen modes with a colour depth of
278 1 bit per pixel for bitmap information:
279
280 Screen width Columns Scaling Bytes (B) Bytes (A) Colours Screen start
281 ------------ ------- ------- --------- --------- ------- ------------
282 320 40 x2 40 40 256 &5300
283 320 40 x2 40 20 16 &5580 -> &5500
284 320 40 x2 40 10 4 &56C0 -> &5600
285 208 26 x3 26 26 256 &62C0 -> &6200
286 208 26 x3 26 13 16 &6460 -> &6400
287
288 MODE 7 Emulation using Character Attributes
289 -------------------------------------------
290
291 If the scheme of applying attributes to character regions were employed to
292 emulate MODE 7, in conjunction with the MODE 6 display technique, the
293 following configuration would be required:
294
295 Screen width Columns Rows Bytes (B) Bytes (A) Colours Screen start
296 ------------ ------- ---- --------- --------- ------- ------------
297 320 40 25 40 20 16 &5ECC -> &5E00
298 320 40 25 40 10 4 &5FC6 -> &5F00
299
300 Although this requires much more memory than MODE 7 (8500 bytes versus MODE
301 7's 1000 bytes), it does not need much more memory than MODE 6, and it would
302 at least make a limited 40-column multicolour mode available as a substitute
303 for MODE 7.
304
305 Enhanced Graphics and Mode Layouts
306 ----------------------------------
307
308 Screen modes with different screen memory mappings, higher resolutions and
309 larger colour depths might be possible, but this would in most cases involve
310 the allocation of more screen memory, and the ULA would probably then be
311 obliged to page in such memory for the CPU to be able to sensibly access it
312 all. Merely changing the memory mappings in order to have Archimedes-style
313 row-oriented screen addresses (instead of character-oriented addresses) could
314 be done for the existing modes, but this might not be sufficiently beneficial,
315 especially since accessing regions of the screen would involve incrementing
316 pointers by amounts that are inconvenient on an 8-bit CPU.
317
318 Enhanced Sound
319 --------------
320
321 The standard ULA reserves &FE*6 for sound generation and cassette
322 input/output, thus making it impossible to support multiple channels within
323 the given framework. The BBC Micro ULA employs &FE40-&FE4F for sound control,
324 and an enhanced ULA could adopt this interface.
325
326 The BBC Micro uses the SN76489 chip to produce sound, and the entire
327 functionality of this chip could be emulated for enhanced sound, with a subset
328 of the functionality exposed via the &FE*6 interface.
329
330 See: http://en.wikipedia.org/wiki/Texas_Instruments_SN76489
331
332 Waveform Upload
333 ---------------
334
335 As with a hardware sprite function, waveforms could be uploaded or referenced
336 using locations as registers referencing memory regions.
337
338 BBC ULA Compatibility
339 ---------------------
340
341 Although some new ULA functions could be defined in a way that is also
342 compatible with the BBC Micro, the BBC ULA is itself incompatible with the
343 Electron ULA: &FE00-7 is reserved for the video controller in the BBC memory
344 map, but controls various functions specific to the 6845 video controller;
345 &FE08-F is reserved for the serial controller. It therefore becomes possible
346 to disregard compatibility where compatibility is already disregarded for a
347 particular area of functionality.
348
349 &FE20-F maps to video ULA functionality on the BBC Micro which provides
350 control over the palette (using address &FE21, compared to &FE07-F on the
351 Electron) and other system-specific functions. Since the location usage is
352 generally incompatible, this region could be reused for other purposes.
353
354 ULA Pin Functions
355 -----------------
356
357 The functions of the ULA pins are described in the Electron Service Manual. Of
358 interest to video processing are the following:
359
360 CSYNC (low during horizontal or vertical synchronisation periods, high
361 otherwise)
362
363 HS (low during horizontal synchronisation periods, high otherwise)
364
365 RED, GREEN, BLUE (pixel colour outputs)
366
367 CLOCK IN (a 16MHz clock input, 4V peak to peak)
368
369 PHI OUT (a 1MHz, 2MHz and stopped clock signal for the CPU)
370
371 More general memory access pins:
372
373 RAM0...RAM3 (data lines to/from the RAM)
374
375 RA0...RA7 (address lines for sending both row and column addresses to the RAM)
376
377 RAS (row address strobe setting the row address on a negative edge)
378
379 CAS (column address strobe setting the column address on a negative edge)
380
381 WE (sets write enable with logic 0, read with logic 1)
382
383 ROM (select data access from ROM)
384
385 CPU-oriented memory access pins:
386
387 A0...A15 (CPU address lines)
388
389 PD0...PD7 (CPU data lines)
390
391 R/W (indicates CPU write with logic 0, CPU read with logic 1)
392
393 Interrupt-related pins:
394
395 NMI (CPU request for uninterrupted 1MHz access to memory)
396
397 IRQ (signal event to CPU)
398
399 POR (power-on reset, resetting the ULA on a positive edge and asserting the
400 CPU's RST pin)
401
402 RST (master reset for the CPU signalled on power-up and by the Break key)
403
404 Keyboard-related pins:
405
406 KBD0...KBD3 (keyboard inputs)
407
408 CAPS LOCK (control status LED)
409
410 Sound-related pins:
411
412 SOUND O/P (sound output using internal oscillator)
413
414 Cassette-related pins:
415
416 CAS IN (cassette circuit input, between 0.5V to 2V peak to peak)
417
418 CAS OUT (pseudo-sinusoidal output, 1.8V peak to peak)
419
420 CAS RC (detect high tone)
421
422 CAS MO (motor relay output)
423
424 ÷13 IN (~1200 baud clock input)