1 Principal Design and Feature Constraints
2 ----------------------------------------
3
4 The features of the ULA are limited by the amount of time and resources that
5 can be allocated to each activity necessary to support such features given the
6 fundamental obligations of the unit. Maintaining a screen display based on the
7 contents of RAM itself requires the ULA to have exclusive access to such
8 hardware resources for a significant period of time. Whilst other elements of
9 the ULA can in principle run in parallel with this activity, they cannot also
10 access the RAM. Consequently, other features that might use the RAM must
11 accept a reduced allocation of that resource in comparison to a hypothetical
12 architecture where concurrent RAM access is possible.
13
14 Thus, the principal constraint for many features is bandwidth. The duration of
15 access to hardware resources is one aspect of this; the rate at which such
16 resources can be accessed is another. For example, the RAM is not fast enough
17 to support access more frequently than one byte per 2MHz cycle, and for screen
18 modes involving 80 bytes of screen data per scanline, there are no free cycles
19 for anything other than the production of pixel output during the active
20 scanline periods.
21
22 Timing
23 ------
24
25 According to 15.3.2 in the Advanced User Guide, there are 312 scanlines, 256
26 of which are used to generate pixel data. At 50Hz, this means that 128 cycles
27 are spent on each scanline (2000000 cycles / 50 = 40000 cycles; 40000 cycles /
28 312 ~= 128 cycles). This is consistent with the observation that each scanline
29 requires at most 80 bytes of data, and that the ULA is apparently busy for 40
30 out of 64 microseconds in each scanline.
31
32 Access to RAM involves accessing four 64Kb dynamic RAM devices (IC4 to IC7,
33 each providing two bits of each byte) using two cycles within the 500ns period
34 of the 2MHz clock to complete each access operation. Since the CPU and ULA
35 have to take turns in accessing the RAM in MODE 4, 5 and 6, the CPU must
36 effectively run at 1MHz (since every other 500ns period involves the ULA
37 accessing RAM). The CPU is driven by an external clock (IC8) whose 16MHz
38 frequency is divided by the ULA (IC1) depending on the screen mode in use.
39
40 Each 16MHz cycle is approximately 62.5ns. To access the memory, the following
41 patterns corresponding to 16MHz cycles are required:
42
43 Time (ns): 0-------------- 500------------ ...
44 2 MHz cycle: 0 1 ...
45 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
46 ~RAS: 0 1 0 1 ...
47 ~CAS: 0 1 0 1 0 1 0 1 ...
48 A B B A B B ...
49 F S F S ...
50 a b b a b b ...
51
52 Here, "A" indicates the row and column addresses being latched into the RAM
53 (on a negative edge for ~RAS and ~CAS respectively), and "B" indicates the
54 second column address being latched into the RAM. Presumably, the first and
55 second half-bytes can be read at "F" and "S" respectively, and the row and
56 column addresses must be made available at "a" and "b" respectively at the
57 latest.
58
59 Note that the Service Manual refers to the negative edge of RAS and CAS, but
60 the datasheet for the similar TM4164EC4 product shows latching on the negative
61 edge of ~RAS and ~CAS. It is possible that the Service Manual also intended to
62 communicate the latter behaviour. In the TM4164EC4 datasheet, it appears that
63 "page mode" provides the appropriate behaviour for that particular product.
64
65 See: Acorn Electron Advanced User Guide
66 See: Acorn Electron Service Manual
67 http://acorn.chriswhy.co.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf
68 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
69
70 Video Timing
71 ------------
72
73 According to 8.7 in the Service Manual, and the PAL Wikipedia page,
74 approximately 4.7µs is used for the sync pulse, 5.7µs for the "back porch"
75 (including the "colour burst"), and 1.65µs for the "front porch", totalling
76 12.05µs and thus leaving 51.95µs for the active video signal for each
77 scanline. As the Service Manual suggests in the oscilloscope traces, the
78 display information is transmitted more or less centred within the active
79 video period since the ULA will only be providing pixel data for 40µs in each
80 scanline.
81
82 Each 62.5ns cycle happens to correspond to 64µs divided by 1024, meaning that
83 each scanline can be divided into 1024 cycles, although only 640 at most are
84 actively used to provide pixel data. Pixel data production should only occur
85 within a certain period on each scanline, approximately 262 cycles after the
86 start of hsync:
87
88 active video period = 51.95µs
89 pixel data period = 40µs
90 total silent period = 51.95µs - 40µs = 11.95µs
91 silent periods (before and after) = 11.95µs / 2 = 5.975µs
92 hsync and back porch period = 4.7µs + 5.7µs = 10.4µs
93 time before pixel data period = 10.4µs + 5.975µs = 16.375µs
94 pixel data period start cycle = 16.375µs / 62.5ns = 262
95
96 By choosing a number divisible by 8, the RAM access mechanism can be
97 synchronised with the pixel production. Thus, 264 is a more appropriate start
98 cycle.
99
100 The "vertical blanking period", meaning the period before picture information
101 in each field is 25 lines out of 312 (strictly 312.5) and thus lasts for
102 1.6ms. Of this, 2.5 lines occur before the vsync (field sync) which also lasts
103 for 2.5 lines. Thus, the first visible scanline on the first field of a frame
104 occurs half way through the 23rd scanline period measured from the start of
105 vsync:
106
107 10 20 23
108 Line in frame: 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8
109 Line from 1: 0 22 3
110 Line on screen: .:::::VVVVV::::: 12233445566
111 |_________________________________________________|
112 25 line vertical blanking period
113
114 In the second field of a frame, the first visible scanline coincides with the
115 24th scanline period measured from the start of line 313 in the frame:
116
117 310 336
118 Line in frame: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
119 Line from 313: 0 23
120 Line on screen: 88:::::VVVVV:::: 11223344
121 288 | |
122 |_________________________________________________|
123 25 line vertical blanking period
124
125 In order to consider only full lines, we might consider the start of each
126 frame to occur 23 lines after the start of vsync.
127
128 Again, it is likely that pixel data production should only occur on scanlines
129 within a certain period on each frame. The "625/50" document indicates that
130 only a certain region is "safe" to use, suggesting a vertically centred region
131 with approximately 15 blank lines above and below the picture. Thus, the start
132 of the picture could be chosen as 38 lines after the start of vsync.
133
134 See: http://en.wikipedia.org/wiki/PAL
135 See: http://en.wikipedia.org/wiki/Analog_television#Structure_of_a_video_signal
136 See: The 625/50 PAL Video Signal and TV Compatible Graphics Modes
137 http://lipas.uwasa.fi/~f76998/video/modes/
138 See: PAL TV timing and voltages
139 http://www.retroleum.co.uk/electronics-articles/pal-tv-timing-and-voltages/
140 See: Line Standards
141 http://www.pembers.freeserve.co.uk/World-TV-Standards/Line-Standards.html
142
143 RAM Integrated Circuits
144 -----------------------
145
146 The documentation for the Electron mentions 4164-15 RAM chips for IC4-7, and
147 the Samsung-produced KM4164 series is apparently equivalent to the Texas
148 Instruments 4164 chips presumably used in the Electron.
149
150 The TM4164EC4 series combines 4 64K x 1b units into a single package and
151 appears similar to the TM4164EA4 featured on the Electron's circuit diagram
152 (in the Advanced User Guide but not the Service Manual), and it also has 22
153 pins providing 3 additional inputs and 3 additional outputs over the 16 pins
154 of the individual 4164-15 modules, presumably allowing concurrent access to
155 the packaged memory units.
156
157 As far as currently available replacements are concerned, the NTE4164 is a
158 potential candidate: according to the Vetco Electronics entry, it is
159 supposedly a replacement for the TMS4164-15 amongst many other parts. Similar
160 parts include the NTE2164 and the NTE6664, both of which appear to have
161 largely the same performance and connection characteristics. Meanwhile, the
162 NTE21256 appears to be a 16-pin replacement that with four times the capacity
163 that maintains the single data input and output pins. Using the NTE21256 as a
164 replacement for all ICs combined would be difficult because of the single bit
165 output.
166
167 Another device equivalent to the 4164-15 appears to be available under the
168 code 41662 from Jameco Electronics as the Siemens HYB 4164-2. The Jameco Web
169 site lists data sheets for other devices on the same page, but these are
170 different and actually appear to be provided under the 41574 product code (but
171 are listed under 41464-10) and appear to be replacements for the TM4164EC4:
172 the Samsung KM41464A-15 and NEC µPD41464 employ 18 pins, eliminating 4 pins by
173 employing 4 pins for both input and output.
174
175 See: TM4164EC4 65,536 by 4-Bit Dynamic RAM Module
176 http://www.datasheetarchive.com/dl/Datasheets-112/DSAP0051030.pdf
177 See: KM4164B 64K x 1 Bit Dynamic RAM with Page Mode
178 http://images.ihscontent.net/vipimages/VipMasterIC/IC/SAMS/SAMSD020/SAMSD020-45.pdf
179 See: NTE2164 Integrated Circuit 65,536 X 1 Bit Dynamic Random Access Memory
180 http://www.vetco.net/catalog/product_info.php?products_id=2806
181 See: NTE4164 - IC-NMOS 64K DRAM 150NS
182 http://www.vetco.net/catalog/product_info.php?products_id=3680
183 See: NTE21256 - IC-256K DRAM 150NS
184 http://www.vetco.net/catalog/product_info.php?products_id=2799
185 See: NTE21256 262,144-Bit Dynamic Random Access Memory (DRAM)
186 http://www.nteinc.com/specs/21000to21999/pdf/nte21256.pdf
187 See: NTE6664 - IC-MOS 64K DRAM 150NS
188 http://www.vetco.net/catalog/product_info.php?products_id=5213
189 See: NTE6664 Integrated Circuit 64K-Bit Dynamic RAM
190 http://www.nteinc.com/specs/6600to6699/pdf/nte6664.pdf
191 See: 4164-150: MAJOR BRANDS
192 http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41662_-1
193 See: HYB 4164-1, HYB 4164-2, HYB 4164-3 65,536-Bit Dynamic Random Access Memory (RAM)
194 http://www.jameco.com/Jameco/Products/ProdDS/41662SIEMENS.pdf
195 See: KM41464A NMOS DRAM 64K x 4 Bit Dynamic RAM with Page Mode
196 http://www.jameco.com/Jameco/Products/ProdDS/41662SAM.pdf
197 See: NEC µ41464 65,536 x 4-Bit Dynamic NMOS RAM
198 http://www.jameco.com/Jameco/Products/ProdDS/41662NEC.pdf
199 See: 41464-10: MAJOR BRANDS
200 http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41574_-1
201
202 Interrupts
203 ----------
204
205 The ULA generates IRQs (maskable interrupts) according to certain conditions
206 and these conditions are controlled by location &FE00:
207
208 * Vertical sync (bottom of displayed screen)
209 * 50MHz real time clock
210 * Transmit data empty
211 * Receive data full
212 * High tone detect
213
214 The ULA is also used to clear interrupt conditions through location &FE05. Of
215 particular significance is bit 7, which must be set if an NMI (non-maskable
216 interrupt) has occurred and has thus suspended ULA access to memory, restoring
217 the normal function of the ULA.
218
219 ROM Paging
220 ----------
221
222 Accessing different ROMs involves bits 0 to 3 of &FE05. Some special ROM
223 mappings exist:
224
225 8 keyboard
226 9 keyboard (duplicate)
227 10 BASIC ROM
228 11 BASIC ROM (duplicate)
229
230 Paging in a ROM involves the following procedure:
231
232 1. Assert ROM page enable (bit 3) together with a ROM number n in bits 0 to
233 2, corresponding to ROM number 8+n, such that one of ROMs 12 to 15 is
234 selected.
235 2. Where a ROM numbered from 0 to 7 is to be selected, set bit 3 to zero
236 whilst writing the desired ROM number n in bits 0 to 2.
237
238 Shadow/Expanded Memory
239 ----------------------
240
241 The Electron exposes all sixteen address lines and all eight data lines
242 through the expansion bus. Using such lines, it is possible to provide
243 additional memory - typically sideways ROM and RAM - on expansion cards and
244 through cartridges, although the official cartridge specification provides
245 fewer address lines and only seeks to provide access to memory in 16K units.
246
247 Various modifications and upgrades were developed to offer "turbo"
248 capabilities to the Electron, permitting the CPU to access a separate 8K of
249 RAM at 2MHz, presumably preventing access to the low 8K of RAM accessible via
250 the ULA through additional logic. However, an enhanced ULA might support
251 independent CPU access to memory over the expansion bus by allowing itself to
252 be discharged from providing access to memory, potentially for a range of
253 addresses, and for the CPU to communicate with external memory uninterrupted.
254
255 Hardware Scrolling
256 ------------------
257
258 On the standard ULA, &FE02 and &FE03 map to a 9 significant bits address with
259 the least significant 5 bits being zero, thus limiting the scrolling
260 resolution to 64 bytes. An enhanced ULA could support a resolution of 2 bytes
261 using the same layout of these addresses.
262
263 |--&FE02--------------| |--&FE03--------------|
264 XX XX 14 13 12 11 10 09 08 07 06 XX XX XX XX XX
265
266 XX 14 13 12 11 10 09 08 07 06 05 04 03 02 01 XX
267
268 Arguably, a resolution of 8 bytes is more useful, since the mapping of screen
269 memory to pixel locations is character oriented. A change in 8 bytes would
270 permit a horizontal scrolling resolution of 2 pixels in MODE 2, 4 pixels in
271 MODE 1 and 5, and 8 pixels in MODE 0, 3 and 6. This resolution is actually
272 observed on the BBC Micro (see 18.11.2 in the BBC Microcomputer Advanced User
273 Guide).
274
275 One argument for a 2 byte resolution is smooth vertical scrolling. A pitfall
276 of changing the screen address by 2 bytes is the change in the number of lines
277 from the initial and final character rows that need reading by the ULA, which
278 would need to maintain this state information (although this is a relatively
279 trivial change). Another pitfall is the complication that might be introduced
280 to software writing bitmaps of character height to the screen.
281
282 Enhancement: Region Blanking
283 ----------------------------
284
285 The problem of permitting character-oriented blitting in programs whilst
286 scrolling the screen by sub-character amounts could be mitigated by permitting
287 a region of the display to be blank, such as the final lines of the display.
288 Consider the following vertical scrolling by 2 bytes that would cause an
289 initial character row of 6 lines and a final character row of 2 lines:
290
291 6 lines - initial, partial character row
292 248 lines - 31 complete rows
293 2 lines - final, partial character row
294
295 If a routine were in use that wrote 8 line bitmaps to the partial character
296 row now split in two, it would be advisable to hide one of the regions in
297 order to prevent content appearing in the wrong place on screen (such as
298 content meant to appear at the top "leaking" onto the bottom). Blanking 6
299 lines would be sufficient, as can be seen from the following cases.
300
301 Scrolling up by 2 lines:
302
303 6 lines - initial, partial character row
304 240 lines - 30 complete rows
305 4 lines - part of 1 complete row
306 -----------------------------------------------------------------
307 4 lines - part of 1 complete row (hidden to maintain 250 lines)
308 2 lines - final, partial character row (hidden)
309
310 Scrolling down by 2 lines:
311
312 2 lines - initial, partial character row
313 248 lines - 31 complete rows
314 ----------------------------------------------------------
315 6 lines - final, partial character row (hidden)
316
317 Thus, in this case, region blanking would impose a 250 line display with the
318 bottom 6 lines blank.
319
320 See the description of the display suspend enhancement for a more efficient
321 way of blanking lines whilst allowing the CPU to perform useful work during
322 the blanking period.
323
324 Enhancement: Screen Height Adjustment
325 -------------------------------------
326
327 The height of the screen could be configurable in order to reduce screen
328 memory consumption. This is not quite done in MODE 3 and 6 since the start of
329 the screen appears to be rounded down to the nearest page, but by reducing the
330 height by amounts more than a page, savings would be possible. For example:
331
332 Screen width Depth Height Bytes per line Saving in bytes Start address
333 ------------ ----- ------ -------------- --------------- -------------
334 640 1 252 80 320 &3140 -> &3100
335 640 1 248 80 640 &3280 -> &3200
336 320 1 240 40 640 &5A80 -> &5A00
337 320 2 240 80 1280 &3500
338
339 Screen Mode Selection
340 ---------------------
341
342 Bits 3, 4 and 5 of address &FE*7 control the selected screen mode. For a wider
343 range of modes, the other bits of &FE*7 (related to sound, cassette
344 input/output and the Caps Lock LED) would need to be reassigned and bit 0
345 potentially being made available for use.
346
347 Palette Definition
348 ------------------
349
350 Since all memory accesses go via the ULA, an enhanced ULA could employ more
351 specific addresses than &FE*X to perform enhanced functions. For example, the
352 palette control is done using &FE*8-F and merely involves selecting predefined
353 colours, whereas an enhanced ULA could support the redefinition of all 16
354 colours using specific ranges such as &FE18-F (colours 0 to 7) and &FE28-F
355 (colours 8 to 15), where a single byte might provide 8 bits per pixel colour
356 specifications similar to those used on the Archimedes.
357
358 The principal limitation here is actually the hardware: the Electron has only
359 a single output line for each of the red, green and blue channels, and if
360 those outputs are strictly digital and can only be set to a "high" and "low"
361 value, then only the existing eight colours are possible. If a modern ULA were
362 able to output analogue values, it would still need to be assessed whether the
363 circuitry could successfully handle and propagate such values. Various sources
364 indicate that only "TTL levels" are supported by the RGB output circuit, and
365 since there are 74LS08 AND logic gates involved in the RGB component outputs
366 from the ULA, it is likely that the ULA is expected to provide only "high" or
367 "low" values.
368
369 Flashing Colours
370 ----------------
371
372 According to the Advanced User Guide, "The cursor and flashing colours are
373 entirely generated in software: This means that all of the logical to physical
374 colour map must be changed to cause colours to flash." This appears to suggest
375 that the palette registers must be updated upon the flash counter - read and
376 written by OSBYTE &C1 (193) - reaching zero and that some way of changing the
377 colour pairs to be any combination of colours might be possible, instead of
378 having colour complements as pairs.
379
380 It is conceivable that the interrupt code responsible does the simple thing
381 and merely inverts the current values for any logical colours (LC) for which
382 the associated physical colour (as supplied as the second parameter to the VDU
383 19 call) has the top bit of its four bit value set. These top bits are not
384 recorded in the palette registers but are presumably recorded separately and
385 used to build bitmaps as follows:
386
387 LC 2 colour 4 colour 16 colour 4-bit value for inversion
388 -- -------- -------- --------- -------------------------
389 0 00010001 00010001 00010001 1, 1, 1
390 1 01000100 00100010 00010001 4, 2, 1
391 2 01000100 00100010 4, 2
392 3 10001000 00100010 8, 2
393 4 00010001 1
394 5 00010001 1
395 6 00100010 2
396 7 00100010 2
397 8 01000100 4
398 9 01000100 4
399 10 10001000 8
400 11 10001000 8
401 12 01000100 4
402 13 01000100 4
403 14 10001000 8
404 15 10001000 8
405
406 Inversion value calculation:
407
408 2 colour formula: 1 << (colour * 2)
409 4 colour formula: 1 << colour
410 16 colour formula: 1 << ((colour & 2) + ((colour & 8) * 2))
411
412 For example, where logical colour 0 has been mapped to a physical colour in
413 the range 8 to 15, a bitmap of 00010001 would be chosen as its contribution to
414 the inversion operation. (The lower three bits of the physical colour would be
415 used to set the underlying colour information affected by the inversion
416 operation.)
417
418 An operation in the interrupt code would then combine the bitmaps for all
419 logical colours in 2 and 4 colour modes, with the 16 colour bitmaps being
420 combined for groups of logical colours as follows:
421
422 Logical colours
423 ---------------
424 0, 2, 8, 10
425 4, 6, 12, 14
426 5, 7, 13, 15
427 1, 3, 9, 11
428
429 These combined bitmaps would be EORed with the existing palette register
430 values in order to perform the value inversion necessary to produce the
431 flashing effect.
432
433 Thus, in the VDU 19 operation, the appropriate inversion value would be
434 calculated for the logical colour, and this value would then be combined with
435 other inversion values in a dedicated memory location corresponding to the
436 colour's group as indicated above. Meanwhile, the palette channel values would
437 be derived from the lower three bits of the specified physical colour and
438 combined with other palette data in dedicated memory locations corresponding
439 to the palette registers.
440
441 Enhancement: Palette Definition Lists
442 -------------------------------------
443
444 It can be useful to redefine the palette in order to change the colours
445 available for a particular region of the screen, particularly in modes where
446 the choice of colours is constrained, and if an increased colour depth were
447 available, palette redefinition would be useful to give the illusion of more
448 than 16 colours in MODE 2. Traditionally, palette redefinition has been done
449 by using interrupt-driven timers, but a more efficient approach would involve
450 presenting lists of palette definitions to the ULA so that it can change the
451 palette at a particular display line.
452
453 One might define a palette redefinition list in a region of memory and then
454 communicate its contents to the ULA by writing the address and length of the
455 list, along with the display line at which the palette is to be changed, to
456 ULA registers such that the ULA buffers the list and performs the redefinition
457 at the appropriate time. Throughput/bandwidth considerations might impose
458 restrictions on the practical length of such a list, however.
459
460 Enhancement: Palette-Free Modes
461 -------------------------------
462
463 Palette-free modes might be defined where bit values directly correspond to
464 the red, green and blue channels, although this would mostly make sense only
465 for modes with depths greater than the standard 4 bits per pixel, and such
466 modes would require more memory than MODE 2 if they were to have an acceptable
467 resolution.
468
469 Enhancement: Display Suspend
470 ----------------------------
471
472 Especially when writing to the screen memory, it could be beneficial to be
473 able to suspend the ULA's access to the memory, instead producing blank values
474 for all screen pixels until a program is ready to reveal the screen. This is
475 different from palette blanking since with a blank palette, the ULA is still
476 reading screen memory and translating its contents into pixel values that end
477 up being blank.
478
479 This function is reminiscent of a capability of the ZX81, albeit necessary on
480 that hardware to reduce the load on the system CPU which was responsible for
481 producing the video output.
482
483 Enhancement: Hardware Sprites
484 -----------------------------
485
486 An enhanced ULA might provide hardware sprites, but this would be done in an
487 way that is incompatible with the standard ULA, since no &FE*X locations are
488 available for allocation. To keep the facility simple, hardware sprites would
489 have a standard byte width and height.
490
491 The specification of sprites could involve the reservation of 16 locations
492 (for example, &FE20-F) specifying a fixed number of eight sprites, with each
493 location pair referring to the sprite data. By limiting the ULA to dealing
494 with a fixed number of sprites, the work required inside the ULA would be
495 reduced since it would avoid having to deal with arbitrary numbers of sprites.
496
497 The principal limitation on providing hardware sprites is that of having to
498 obtain sprite data, given that the ULA is usually required to retrieve screen
499 data, and given the lack of memory bandwidth available to retrieve sprite data
500 (particularly from multiple sprites supposedly at the same position) and
501 screen data simultaneously. Although the ULA could potentially read sprite
502 data and screen data in alternate memory accesses in screen modes where the
503 bandwidth is not already fully utilised, this would result in a degradation of
504 performance.
505
506 Enhancement: Additional Screen Mode Configurations
507 --------------------------------------------------
508
509 Alternative screen mode configurations could be supported. The ULA has to
510 produce 640 pixel values across the screen, with pixel doubling or quadrupling
511 employed to fill the screen width:
512
513 Screen width Columns Scaling Depth Bytes
514 ------------ ------- ------- ----- -----
515 640 80 x1 1 80
516 320 40 x2 1, 2 40, 80
517 160 20 x4 2, 4 40, 80
518
519 It must also use at most 80 byte-sized memory accesses to provide the
520 information for the display. Given that characters must occupy an 8x8 pixel
521 array, if a configuration featuring anything other than 20, 40 or 80 character
522 columns is to be supported, compromises must be made such as the introduction
523 of blank pixels either between characters (such as occurs between rows in MODE
524 3 and 6) or at the end of a scanline (such as occurs at the end of the frame
525 in MODE 3 and 6). Consider the following configuration:
526
527 Screen width Columns Scaling Depth Bytes Blank
528 ------------ ------- ------- ----- ------ -----
529 208 26 x3 1, 2 26, 52 16
530
531 Here, if the ULA can triple pixels, a 26 column mode with either 2 or 4
532 colours could be provided, with 16 blank pixel values (out of a total of 640)
533 generated either at the start or end (or split between the start and end) of
534 each scanline.
535
536 Enhancement: Character Attributes
537 ---------------------------------
538
539 The BBC Micro MODE 7 employs something resembling character attributes to
540 support teletext displays, but depends on circuitry providing a character
541 generator. The ZX Spectrum, on the other hand, provides character attributes
542 as a means of colouring bitmapped graphics. Although such a feature is very
543 limiting as the sole means of providing multicolour graphics, in situations
544 where the choice is between low resolution multicolour graphics or high
545 resolution monochrome graphics, character attributes provide a potentially
546 useful compromise.
547
548 For each byte read, the ULA must deliver 8 pixel values (out of a total of
549 640) to the video output, doing so by either emptying its pixel buffer on a
550 pixel per cycle basis, or by multiplying pixels and thus holding them for more
551 than one cycle. For example for a screen mode having 640 pixels in width:
552
553 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
554 Reads: B B
555 Pixels: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
556
557 And for a screen mode having 320 pixels in width:
558
559 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
560 Reads: B
561 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
562
563 However, in modes where less than 80 bytes are required to generate the pixel
564 values, an enhanced ULA might be able to read additional bytes between those
565 providing the bitmapped graphics data:
566
567 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
568 Reads: B A
569 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
570
571 These additional bytes could provide colour information for the bitmapped data
572 in the following character column (of 8 pixels). Since it would be desirable
573 to apply attribute data to the first column, the initial 8 cycles might be
574 configured to not produce pixel values.
575
576 For an entire character, attribute data need only be read for the first row of
577 pixels for a character. The subsequent rows would have attribute information
578 applied to them, although this would require the attribute data to be stored
579 in some kind of buffer. Thus, the following access pattern would be observed:
580
581 Cycle: A B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ...
582
583 A whole byte used for colour information for a whole character would result in
584 a choice of 256 colours, and this might be somewhat excessive. By only reading
585 attribute bytes at every other opportunity, a choice of 16 colours could be
586 applied individually to two characters.
587
588 Cycle: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
589 Reads: B A B -
590 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
591
592 Further reductions in attribute data access, offering 4 colours for every
593 character in a four character block, for example, might also be worth
594 considering.
595
596 Consider the following configurations for screen modes with a colour depth of
597 1 bit per pixel for bitmap information:
598
599 Screen width Columns Scaling Bytes (B) Bytes (A) Colours Screen start
600 ------------ ------- ------- --------- --------- ------- ------------
601 320 40 x2 40 40 256 &5300
602 320 40 x2 40 20 16 &5580 -> &5500
603 320 40 x2 40 10 4 &56C0 -> &5600
604 208 26 x3 26 26 256 &62C0 -> &6200
605 208 26 x3 26 13 16 &6460 -> &6400
606
607 Enhancement: MODE 7 Emulation using Character Attributes
608 --------------------------------------------------------
609
610 If the scheme of applying attributes to character regions were employed to
611 emulate MODE 7, in conjunction with the MODE 6 display technique, the
612 following configuration would be required:
613
614 Screen width Columns Rows Bytes (B) Bytes (A) Colours Screen start
615 ------------ ------- ---- --------- --------- ------- ------------
616 320 40 25 40 20 16 &5ECC -> &5E00
617 320 40 25 40 10 4 &5FC6 -> &5F00
618
619 Although this requires much more memory than MODE 7 (8500 bytes versus MODE
620 7's 1000 bytes), it does not need much more memory than MODE 6, and it would
621 at least make a limited 40-column multicolour mode available as a substitute
622 for MODE 7.
623
624 Enhancement: High Resolution Graphics and Mode Layouts
625 ------------------------------------------------------
626
627 Screen modes with different screen memory mappings, higher resolutions and
628 larger colour depths might be possible, but this would in most cases involve
629 the allocation of more screen memory, and the ULA would probably then be
630 obliged to page in such memory for the CPU to be able to sensibly access it
631 all. Merely changing the memory mappings in order to have Archimedes-style
632 row-oriented screen addresses (instead of character-oriented addresses) could
633 be done for the existing modes, but this might not be sufficiently beneficial,
634 especially since accessing regions of the screen would involve incrementing
635 pointers by amounts that are inconvenient on an 8-bit CPU.
636
637 Enhancement: Genlock Support
638 ----------------------------
639
640 The ULA generates a video signal in conjunction with circuitry producing the
641 output features necessary for the correct display of the screen image.
642 However, it appears that the ULA drives the video synchronisation mechanism
643 instead of reacting to an existing signal. Genlock support might be possible
644 if the ULA were made to be responsive to such external signals, resetting its
645 address generators upon receiving synchronisation events.
646
647 Enhancement: Improved Sound
648 ---------------------------
649
650 The standard ULA reserves &FE*6 for sound generation and cassette input/output
651 (with bits 1 and 2 of &FE*7 being used to select either sound generation or
652 cassette I/O), thus making it impossible to support multiple channels within
653 the given framework. The BBC Micro ULA employs &FE40-&FE4F for sound control,
654 and an enhanced ULA could adopt this interface.
655
656 The BBC Micro uses the SN76489 chip to produce sound, and the entire
657 functionality of this chip could be emulated for enhanced sound, with a subset
658 of the functionality exposed via the &FE*6 interface.
659
660 See: http://en.wikipedia.org/wiki/Texas_Instruments_SN76489
661
662 Enhancement: Waveform Upload
663 ----------------------------
664
665 As with a hardware sprite function, waveforms could be uploaded or referenced
666 using locations as registers referencing memory regions.
667
668 Enhancement: Sound Input/Output
669 -------------------------------
670
671 Since the ULA already controls audio input/output for cassette-based data, it
672 would have been interesting to entertain the idea of sampling and output of
673 sounds through the cassette interface. However, a significant amount of
674 circuitry is employed to process the input signal for use by the ULA and to
675 process the output signal for recording.
676
677 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw_03.htm#3.11
678
679 Enhancement: BBC ULA Compatibility
680 ----------------------------------
681
682 Although some new ULA functions could be defined in a way that is also
683 compatible with the BBC Micro, the BBC ULA is itself incompatible with the
684 Electron ULA: &FE00-7 is reserved for the video controller in the BBC memory
685 map, but controls various functions specific to the 6845 video controller;
686 &FE08-F is reserved for the serial controller. It therefore becomes possible
687 to disregard compatibility where compatibility is already disregarded for a
688 particular area of functionality.
689
690 &FE20-F maps to video ULA functionality on the BBC Micro which provides
691 control over the palette (using address &FE21, compared to &FE07-F on the
692 Electron) and other system-specific functions. Since the location usage is
693 generally incompatible, this region could be reused for other purposes.
694
695 Enhancement: Increased RAM, ULA and CPU Performance
696 ---------------------------------------------------
697
698 More modern implementations of the hardware might feature faster RAM coupled
699 with an increased ULA clock frequency in order to increase the bandwidth
700 available to the ULA and to the CPU in situations where the ULA is not needed
701 to perform work. A ULA employing a 32MHz clock would be able to complete the
702 retrieval of a byte from RAM in only 250ns and thus be able to enable the CPU
703 to access the RAM for the following 250ns even in display modes requiring the
704 retrieval of a byte for the display every 500ns. The CPU could, subject to
705 timing issues, run at 2MHz even in MODE 0, 1 and 2.
706
707 A scheme such as that described above would have a similar effect to the
708 scheme employed in the BBC Micro, although the latter made use of RAM with a
709 wider bandwidth in order to complete memory transfers within 250ns and thus
710 permit the CPU to run continuously at 2MHz.
711
712 Higher bandwidth could potentially be used to implement exotic features such
713 as RAM-resident hardware sprites or indeed any feature demanding RAM access
714 concurrent with the production of the display image.
715
716 ULA Pin Functions
717 -----------------
718
719 The functions of the ULA pins are described in the Electron Service Manual. Of
720 interest to video processing are the following:
721
722 CSYNC (low during horizontal or vertical synchronisation periods, high
723 otherwise)
724
725 HS (low during horizontal synchronisation periods, high otherwise)
726
727 RED, GREEN, BLUE (pixel colour outputs)
728
729 CLOCK IN (a 16MHz clock input, 4V peak to peak)
730
731 PHI OUT (a 1MHz, 2MHz and stopped clock signal for the CPU)
732
733 More general memory access pins:
734
735 RAM0...RAM3 (data lines to/from the RAM)
736
737 RA0...RA7 (address lines for sending both row and column addresses to the RAM)
738
739 RAS (row address strobe setting the row address on a negative edge - see the
740 timing notes)
741
742 CAS (column address strobe setting the column address on a negative edge -
743 see the timing notes)
744
745 WE (sets write enable with logic 0, read with logic 1)
746
747 ROM (select data access from ROM)
748
749 CPU-oriented memory access pins:
750
751 A0...A15 (CPU address lines)
752
753 PD0...PD7 (CPU data lines)
754
755 R/W (indicates CPU write with logic 0, CPU read with logic 1)
756
757 Interrupt-related pins:
758
759 NMI (CPU request for uninterrupted 1MHz access to memory)
760
761 IRQ (signal event to CPU)
762
763 POR (power-on reset, resetting the ULA on a positive edge and asserting the
764 CPU's RST pin)
765
766 RST (master reset for the CPU signalled on power-up and by the Break key)
767
768 Keyboard-related pins:
769
770 KBD0...KBD3 (keyboard inputs)
771
772 CAPS LOCK (control status LED)
773
774 Sound-related pins:
775
776 SOUND O/P (sound output using internal oscillator)
777
778 Cassette-related pins:
779
780 CAS IN (cassette circuit input, between 0.5V to 2V peak to peak)
781
782 CAS OUT (pseudo-sinusoidal output, 1.8V peak to peak)
783
784 CAS RC (detect high tone)
785
786 CAS MO (motor relay output)
787
788 ÷13 IN (~1200 baud clock input)
789
790 References
791 ----------
792
793 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw.htm