1 Timing
2 ------
3
4 According to the above (15.3.2 in the AUG), there are 312 scanlines, 256 of
5 which are used to generate pixel data. At 50Hz, this means that 128 cycles are
6 used to produce pixel data (2000000 / 50 = 40000; 40000 / 312 ~= 128). This is
7 consistent with the observation that each scanline requires at most 80 bytes
8 of data, and that the ULA is apparently busy for 40 out of 64 microseconds in
9 each scanline.
10
11 See: Acorn Electron Advanced User Guide
12 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
13
14 Access to RAM involves accessing four 64Kb dynamic RAM devices (IC4 to IC7,
15 each providing two bits of each byte) using two cycles within the 500ns period
16 of the 2MHz clock to complete each access operation.
17
18 See: Acorn Electron Service Manual
19
20 Hardware Scrolling
21 ------------------
22
23 On the standard ULA, &FE02 and &FE03 map to a 9 significant bits address with
24 the least significant 5 bits being zero, thus limiting the scrolling
25 resolution to 64 bytes. An enhanced ULA could support a resolution of 2 bytes
26 using the same layout of these addresses.
27
28 |--&FE02--------------| |--&FE03--------------|
29 XX XX 14 13 12 11 10 09 08 07 06 XX XX XX XX XX
30
31 XX 14 13 12 11 10 09 08 07 06 05 04 03 02 01 XX
32
33 Arguably, a resolution of 8 bytes is more useful, since the mapping of screen
34 memory to pixel locations is character oriented. A change in 8 bytes would
35 permit a horizontal scrolling resolution of 2 pixels in MODE 2, 4 pixels in
36 MODE 1 and 5, and 8 pixels in MODE 0, 3 and 6. This resolution is actually
37 observed on the BBC Micro (see 18.11.2 in the BBC Microcomputer Advanced User
38 Guide).
39
40 One argument for a 2 byte resolution is smooth vertical scrolling. A pitfall
41 of changing the screen address by 2 bytes is the change in the number of lines
42 from the initial and final character rows that need reading by the ULA, which
43 would need to maintain this state information (although this is a relatively
44 trivial change). Another pitfall is the complication that might be introduced
45 to software writing bitmaps of character height to the screen.
46
47 Region Blanking
48 ---------------
49
50 The problem of permitting character-oriented blitting in programs whilst
51 scrolling the screen by sub-character amounts could be mitigated by permitting
52 a region of the display to be blank, such as the final lines of the display.
53 Consider the following vertical scrolling by 2 bytes that would cause an
54 initial character row of 6 lines and a final character row of 2 lines:
55
56 6 lines - initial, partial character row
57 248 lines - 31 complete rows
58 2 lines - final, partial character row
59
60 If a routine were in use that wrote 8 line bitmaps to the partial character
61 row now split in two, it would be advisable to hide one of the regions in
62 order to prevent content appearing in the wrong place on screen (such as
63 content meant to appear at the top "leaking" onto the bottom). Blanking 6
64 lines would be sufficient, as can be seen from the following cases.
65
66 Scrolling up by 2 lines:
67
68 6 lines - initial, partial character row
69 240 lines - 30 complete rows
70 4 lines - part of 1 complete row
71 -----------------------------------------------------------------
72 4 lines - part of 1 complete row (hidden to maintain 250 lines)
73 2 lines - final, partial character row (hidden)
74
75 Scrolling down by 2 lines:
76
77 2 lines - initial, partial character row
78 248 lines - 31 complete rows
79 ----------------------------------------------------------
80 6 lines - final, partial character row (hidden)
81
82 Thus, in this case, region blanking would impose a 250 line display with the
83 bottom 6 lines blank.
84
85 Screen Height Adjustment
86 ------------------------
87
88 The height of the screen could be configurable in order to reduce screen
89 memory consumption. This is not quite done in MODE 3 and 6 since the start of
90 the screen appears to be rounded down to the nearest page, but by reducing the
91 height by amounts more than a page, savings would be possible. For example:
92
93 Screen width Depth Height Bytes per line Saving in bytes Start address
94 ------------ ----- ------ -------------- --------------- -------------
95 640 1 252 80 320 &3140 -> &3100
96 640 1 248 80 640 &3280 -> &3200
97 320 1 240 40 640 &5A80 -> &5A00
98 320 2 240 80 1280 &3500
99
100 Palette Definition
101 ------------------
102
103 Since all memory accesses go via the ULA, an enhanced ULA could employ more
104 specific addresses than &FE*X to perform enhanced functions. For example, the
105 palette control is done using &FE*8-F and merely involves selecting predefined
106 colours, whereas an enhanced ULA could support the redefinition of all 16
107 colours using specific ranges such as &FE18-F (colours 0 to 7) and &FE28-F
108 (colours 8 to 15), where a single byte might provide 8 bits per pixel colour
109 specifications similar to those used on the Archimedes.
110
111 The principal limitation here is actually the hardware: the Electron has only
112 a single output line for each of the red, green and blue channels, and if
113 those outputs are strictly digital and can only be set to a "high" and "low"
114 value, then only the existing eight colours are possible. If a modern ULA were
115 able to output analogue values, it would still need to be assessed whether the
116 circuitry could successfully handle and propagate such values.
117
118 Palette Definition Lists
119 ------------------------
120
121 It can be useful to redefine the palette in order to change the colours
122 available for a particular region of the screen, particularly in modes where
123 the choice of colours is constrained, and if an increased colour depth were
124 available, palette redefinition would be useful to give the illusion of more
125 than 16 colours in MODE 2. Traditionally, palette redefinition has been done
126 by using interrupt-driven timers, but a more efficient approach would involve
127 presenting lists of palette definitions to the ULA so that it can change the
128 palette at a particular display line.
129
130 One might define a palette redefinition list in a region of memory and then
131 communicate its contents to the ULA by writing the address and length of the
132 list, along with the display line at which the palette is to be changed, to
133 ULA registers such that the ULA buffers the list and performs the redefinition
134 at the appropriate time. Throughput/bandwidth considerations might impose
135 restrictions on the practical length of such a list, however.
136
137 Palette-Free Modes
138 ------------------
139
140 Palette-free modes might be defined where bit values directly correspond to
141 the red, green and blue channels, although this would mostly make sense only
142 for modes with depths greater than the standard 4 bits per pixel, and such
143 modes would require more memory than MODE 2 if they were to have an acceptable
144 resolution.
145
146 Display Suspend
147 ---------------
148
149 Especially when writing to the screen memory, it could be beneficial to be
150 able to suspend the ULA's access to the memory, instead producing blank values
151 for all screen pixels until a program is ready to reveal the screen. This is
152 different from palette blanking since with a blank palette, the ULA is still
153 reading screen memory and translating its contents into pixel values that end
154 up being blank.
155
156 This function is reminiscent of a capability of the ZX81, albeit necessary on
157 that hardware to reduce the load on the system CPU which was responsible for
158 producing the video output.
159
160 Hardware Sprites and Colour Planes
161 ----------------------------------
162
163 An enhanced ULA might provide hardware sprites, but this would be done in an
164 way that is incompatible with the standard ULA, since no &FE*X locations are
165 available for allocation. In a special ULA mode, one might allocate a pair of
166 locations (for example, &FE20 and &FE21) as a pair of registers referencing a
167 region of memory from which a sprite might be found and potentially copied
168 into internal RAM, with other locations (for example, &FE22 and &FE23)
169 providing the size of the region. Alternatively, one might write the region
170 location and size through a single ULA location, with the ULA being put into a
171 particular state after each write. For example: read LSB of region, read MSB
172 of region, read size, read height.
173
174 Providing hardware sprites can be awkward without having some kind of working
175 area, since the ULA would need to remember where each sprite is to be plotted
176 and then deduce which sprites would be contributing to any given pixel. An
177 alternative is to use memory into which the sprites would be plotted, and this
178 memory would be combined with the main screen memory, taking a particular
179 colour as the "colourkey" which is to be considered transparent, and only
180 overwriting the main screen pixels with pixel values for other colours.
181
182 Additional Screen Mode Configurations
183 -------------------------------------
184
185 Alternative screen mode configurations could be supported. The ULA has to
186 produce 640 pixel values across the screen, with pixel doubling or quadrupling
187 employed to fill the screen width:
188
189 Screen width Columns Scaling Depth Bytes
190 ------------ ------- ------- ----- -----
191 640 80 x1 1 80
192 320 40 x2 1, 2 40, 80
193 160 20 x4 2, 4 40, 80
194
195 It must also use at most 80 byte-sized memory accesses to provide the
196 information for the display. Given that characters must occupy an 8x8 pixel
197 array, if a configuration featuring anything other than 20, 40 or 80 character
198 columns is to be supported, compromises must be made such as the introduction
199 of blank pixels either between characters (such as occurs between rows in MODE
200 3 and 6) or at the end of a scanline (such as occurs at the end of the frame
201 in MODE 3 and 6). Consider the following configuration:
202
203 Screen width Columns Scaling Depth Bytes Blank
204 ------------ ------- ------- ----- ------ -----
205 208 26 x3 1, 2 26, 52 16
206
207 Here, if the ULA can triple pixels, a 26 column mode with either 2 or 4
208 colours could be provided, with 16 blank pixel values (out of a total of 640)
209 generated either at the start or end (or split between the start and end) of
210 each scanline.
211
212 Character Attributes
213 --------------------
214
215 The BBC Micro MODE 7 employs something resembling character attributes to
216 support teletext displays, but depends on circuitry providing a character
217 generator. The ZX Spectrum, on the other hand, provides character attributes
218 as a means of colouring bitmapped graphics. Although such a feature is very
219 limiting as the sole means of providing multicolour graphics, in situations
220 where the choice is between low resolution multicolour graphics or high
221 resolution monochrome graphics, character attributes provide a potentially
222 useful compromise.
223
224 For each byte read, the ULA must deliver 8 pixel values (out of a total of
225 640) to the video output, doing so by either emptying its pixel buffer on a
226 pixel per cycle basis, or by multiplying pixels and thus holding them for more
227 than one cycle. For example for a screen mode having 640 pixels in width:
228
229 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
230 Reads: B B
231 Pixels: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
232
233 And for a screen mode having 320 pixels in width:
234
235 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
236 Reads: B
237 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
238
239 However, in modes where less than 80 bytes are required to generate the pixel
240 values, an enhanced ULA might be able to read additional bytes between those
241 providing the bitmapped graphics data:
242
243 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
244 Reads: B A
245 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
246
247 These additional bytes could provide colour information for the bitmapped data
248 in the following character column (of 8 pixels). Since it would be desirable
249 to apply attribute data to the first column, the initial 8 cycles might be
250 configured to not produce pixel values.
251
252 A whole byte used for colour information for a whole character would result in
253 a choice of 256 colours, and this might be somewhat excessive. By only reading
254 attribute bytes at every other opportunity, a choice of 16 colours could be
255 applied individually to two characters.
256
257 Cycle: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
258 Reads: B A B -
259 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
260
261 Consider the following configurations for screen modes with a colour depth of
262 1 bit per pixel for bitmap information:
263
264 Screen width Columns Scaling Bytes (B) Bytes (A) Colours
265 ------------ ------- ------- --------- --------- -------
266 320 40 x2 40 40 256
267 320 40 x2 40 20 16
268 208 26 x3 26 26 256
269 208 26 x3 26 13 16
270
271 Here, a mode resembling MODE 4 would occupy the same amount of space as MODE 1
272 if 40 attribute (A) bytes were read in addition to the 40 bitmap (B) bytes.
273 This would offer limited benefit over the mode with the higher colour depth,
274 especially if palette definition lists were also available. However, if only
275 20 attribute bytes were read, the screen memory would be only 150% of the
276 original.
277
278 Similarly, if an additional configuration pixel-tripled mode were to require
279 as many attribute bytes as bitmap bytes, it would occupy as much space as its
280 equivalent with twice the colour depth. However, by requiring only 13
281 attribute bytes for every 26 bitmap bytes, it would actually be more efficient
282 than MODE 6 (a screen start address of &6600 versus MODE 6's &6000).
283
284 MODE 7 Emulation
285 ----------------
286
287 If the scheme of applying attributes to character regions were employed to
288 emulate MODE 7, in conjunction with the MODE 6 display technique, the
289 following configuration would be required:
290
291 Screen width Columns Rows Bytes (B) Bytes (A) Colours Screen start
292 ------------ ------- ---- --------- --------- ------- ------------
293 320 40 25 40 20 16 &5120 -> &5100
294
295 Although this requires much more memory than MODE 7 (12000 bytes versus
296 MODE 7's 1000 bytes) and more memory than even MODE 6, it would at least make
297 a limited 40-column multicolour mode available as a substitute for MODE 7.
298
299 Enhanced Graphics and Mode Layouts
300 ----------------------------------
301
302 Screen modes with different screen memory mappings, higher resolutions and
303 larger colour depths might be possible, but this would in most cases involve
304 the allocation of more screen memory, and the ULA would probably then be
305 obliged to page in such memory for the CPU to be able to sensibly access it
306 all. Merely changing the memory mappings in order to have Archimedes-style
307 row-oriented screen addresses (instead of character-oriented addresses) could
308 be done for the existing modes, but this might not be sufficiently beneficial,
309 especially since accessing regions of the screen would involve incrementing
310 pointers by amounts that are inconvenient on an 8-bit CPU.
311
312 Enhanced Sound
313 --------------
314
315 The standard ULA reserves &FE*6 for sound generation and cassette
316 input/output, thus making it impossible to support multiple channels within
317 the given framework. The BBC Micro ULA employs &FE40-&FE4F for sound control,
318 and an enhanced ULA could adopt this interface.
319
320 The BBC Micro uses the SN76489 chip to produce sound, and the entire
321 functionality of this chip could be emulated for enhanced sound, with a subset
322 of the functionality exposed via the &FE*6 interface.
323
324 See: http://en.wikipedia.org/wiki/Texas_Instruments_SN76489
325
326 Waveform Upload
327 ---------------
328
329 As with a hardware sprite function, waveforms could be uploaded or referenced
330 using locations as registers referencing memory regions.
331
332 BBC ULA Compatibility
333 ---------------------
334
335 Although some new ULA functions could be defined in a way that is also
336 compatible with the BBC Micro, the BBC ULA is itself incompatible with the
337 Electron ULA: &FE00-7 is reserved for the video controller in the BBC memory
338 map, but controls various functions specific to the 6845 video controller;
339 &FE08-F is reserved for the serial controller. It therefore becomes possible
340 to disregard compatibility where compatibility is already disregarded for a
341 particular area of functionality.
342
343 &FE20-F maps to video ULA functionality on the BBC Micro which provides
344 control over the palette (using address &FE21, compared to &FE07-F on the
345 Electron) and other system-specific functions. Since the location usage is
346 generally incompatible, this region could be reused for other purposes.
347
348 ULA Pin Functions
349 -----------------
350
351 The functions of the ULA pins are described in the Electron Service Manual. Of
352 interest to video processing are the following:
353
354 CSYNC (low during horizontal or vertical synchronisation periods, high
355 otherwise)
356
357 HS (low during horizontal synchronisation periods, high otherwise)
358
359 RED, GREEN, BLUE (pixel colour outputs)
360
361 CLOCK IN (a 16MHz clock input, 4V peak to peak)
362
363 PHI OUT (a 1MHz, 2MHz and stopped clock signal for the CPU)
364
365 More general memory access pins:
366
367 RAM0...RAM3 (data lines to/from the RAM)
368
369 RA0...RA7 (address lines for sending both row and column addresses to the RAM)
370
371 RAS (row address strobe setting the row address on a negative edge)
372
373 CAS (column address strobe setting the column address on a negative edge)
374
375 WE (sets write enable with logic 0, read with logic 1)
376
377 ROM (select data access from ROM)
378
379 CPU-oriented memory access pins:
380
381 A0...A15 (CPU address lines)
382
383 PD0...PD7 (CPU data lines)
384
385 R/W (indicates CPU write with logic 0, CPU read with logic 1)
386
387 Interrupt-related pins:
388
389 NMI (CPU request for uninterrupted 1MHz access to memory)
390
391 IRQ (signal event to CPU)
392
393 POR (power-on reset, resetting the ULA on a positive edge and asserting the
394 CPU's RST pin)
395
396 RST (master reset for the CPU signalled on power-up and by the Break key)
397
398 Keyboard-related pins:
399
400 KBD0...KBD3 (keyboard inputs)
401
402 CAPS LOCK (control status LED)
403
404 Sound-related pins:
405
406 SOUND O/P (sound output using internal oscillator)
407
408 Cassette-related pins:
409
410 CAS IN (cassette circuit input, between 0.5V to 2V peak to peak)
411
412 CAS OUT (pseudo-sinusoidal output, 1.8V peak to peak)
413
414 CAS RC (detect high tone)
415
416 CAS MO (motor relay output)
417
418 ÷13 IN (~1200 baud clock input)