ULA

ULA.txt

144:3c3aecd24476
3 weeks ago Paul Boddie Added planar graphics display remarks.
     1 The Acorn Electron ULA
     2 ======================
     3 
     4 Principal Design and Feature Constraints
     5 ----------------------------------------
     6 
     7 The features of the ULA are limited in sophistication by the amount of time
     8 and resources that can be allocated to each activity supporting the
     9 fundamental features and obligations of the unit. Maintaining a screen display
    10 based on the contents of RAM itself requires the ULA to have exclusive access
    11 to various hardware resources for a significant period of time.
    12 
    13 Whilst other elements of the ULA can in principle run in parallel with the
    14 display refresh activity, they cannot also access the RAM at the same time.
    15 Consequently, other features that might use the RAM must accept a reduced
    16 allocation of that resource in comparison to a hypothetical architecture where
    17 concurrent RAM access is possible at all times.
    18 
    19 Thus, the principal constraint for many features is bandwidth. The duration of
    20 access to hardware resources is one aspect of this; the rate at which such
    21 resources can be accessed is another. For example, the RAM is not fast enough
    22 to support access more frequently than one byte per 2MHz cycle, and for screen
    23 modes involving 80 bytes of screen data per scanline, there are no free cycles
    24 for anything other than the production of pixel output during the active
    25 scanline periods.
    26 
    27 Another constraint is imposed by the method of RAM access provided by the ULA.
    28 The ULA is able to access RAM by fetching 4 bits at a time and thus managing
    29 to transfer 8 bits within a single 2MHz cycle, this being sufficient to
    30 provide display data for the most demanding screen modes. However, this
    31 mechanism's timing requirements are beyond the capabilities of the CPU when
    32 running at 2MHz.
    33 
    34 Consequently, the CPU will only ever be able to access RAM via the ULA at
    35 1MHz, even when the ULA is not accessing the RAM. Fortunately, when needing to
    36 refresh the display, the ULA is still able to make use of the idle part of
    37 each 1MHz cycle (or, rather, the idle 2MHz cycle unused by the CPU) to itself
    38 access the RAM at a rate of 1 byte per 1MHz cycle (or 1 byte every other 2MHz
    39 cycle), thus supporting the less demanding screen modes.
    40 
    41 Timing
    42 ------
    43 
    44 According to 15.3.2 in the Advanced User Guide, there are 312 scanlines, 256
    45 of which are used to generate pixel data. At 50Hz, this means that 128 cycles
    46 are spent on each scanline (2000000 cycles / 50 = 40000 cycles; 40000 cycles /
    47 312 ~= 128 cycles). This is consistent with the observation that each scanline
    48 requires at most 80 bytes of data, and that the ULA is apparently busy for 40
    49 out of 64 microseconds in each scanline.
    50 
    51 (In fact, since the ULA is seeking to provide an image for an interlaced
    52 625-line display, there are in fact two "fields" involved, one providing 312
    53 scanlines and one providing 313 scanlines. See below for a description of the
    54 video system.)
    55 
    56 Access to RAM involves accessing four 64Kb dynamic RAM devices (IC4 to IC7,
    57 each providing two bits of each byte) using two cycles within the 500ns period
    58 of the 2MHz clock to complete each access operation. Since the CPU and ULA
    59 have to take turns in accessing the RAM in MODE 4, 5 and 6, the CPU must
    60 effectively run at 1MHz (since every other 500ns period involves the ULA
    61 accessing RAM) during transfers of screen data.
    62 
    63 The CPU is driven by an external clock (IC8) whose 16MHz frequency is divided
    64 by the ULA (IC1) depending on the screen mode in use. Each 16MHz cycle is
    65 approximately 62.5ns. To access the memory, the following patterns
    66 corresponding to 16MHz cycles are required:
    67 
    68      Time (ns):  0-------------- 500------------- ...
    69    2 MHz cycle:  0               1                ...
    70   16 MHz cycle:  0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7  ...
    71                  /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ ...
    72           ~RAS:  /---\___________/---\___________ ...
    73           ~CAS:  /-----\___/-\___/-----\___/-\___ ...
    74 Address events:      A B     C       A B     C    ...
    75    Data events:        ...F  ...S      ...F  ...S ...
    76            ~WE:        W               W          ...
    77 
    78       ~RAS ops:  1   0           1   0            ...
    79       ~CAS ops:  1     0   1 0   1     0   1 0    ...
    80 
    81    Address ops:     a.b.    c.      a.b.    c.    ...
    82       Data ops:  s         f     s         f      ...
    83 
    84        PHI OUT:  ----\_______/------------------- ...
    85      CPU (RAM):      .....L  ....D                ...
    86            RnW:      .....R                       ...
    87 
    88        PHI OUT:  ----\_______/-------\_______/--- ...
    89      CPU (ROM):  D   .....L  ....D   .....L  .... ...
    90            RnW:      .....R          .....R       ...
    91 
    92 ~RAS must be high for 100ns, ~CAS must be high for 50ns.
    93 ~RAS must be low for 150ns, ~CAS must be low for 90ns.
    94 Data is available 150ns after ~RAS goes low, 90ns after ~CAS goes low.
    95 
    96 Here, "A" and "B" respectively indicate the row and first column addresses
    97 being latched into the RAM (on a negative edge for ~RAS and ~CAS
    98 respectively), and "C" indicates the second column address being latched into
    99 the RAM. Presumably, the first and second half-bytes can be read at "F" and
   100 "S" respectively, and the row and column addresses must be made available at
   101 "a" and "b" (and "c") respectively at the latest. The TM4164EC4 datasheet
   102 suggests that the addresses can be made available as the ~RAS and ~CAS levels
   103 are brought low. Data can be read at "f" and "s" for the first and second
   104 half-bytes respectively.
   105 
   106 The TM4164EC4-15 has a row address access time of 150ns (maximum) and a column
   107 address access time of 90ns (maximum), which appears to mean that ~RAS must be
   108 held low for at least 150ns and that ~CAS must be held low for at least 90ns
   109 before data becomes available. 150ns is 2.4 cycles (at 16MHz) and 90ns is 1.44
   110 cycles. Thus, "A" to "F" is 2.5 cycles, "B" to "F" is 1.5 cycles, "C" to "S"
   111 is 1.5 cycles.
   112 
   113 Note that the Service Manual refers to the negative edge of RAS and CAS, but
   114 the datasheet for the similar TM4164EC4 product shows latching on the negative
   115 edge of ~RAS and ~CAS. It is possible that the Service Manual also intended to
   116 communicate the latter behaviour. In the TM4164EC4 datasheet, it appears that
   117 "page mode" provides the appropriate behaviour for that particular product.
   118 
   119 The CPU, when accessing the RAM alone, apparently does not make use of the
   120 vacated "slot" that the ULA would otherwise use (when interleaving accesses in
   121 MODE 4, 5 and 6). It only employs a full 2MHz access frequency to memory when
   122 accessing ROM (and potentially sideways RAM). The principal limitation is the
   123 amount of time needed between issuing an address and receiving an entire byte
   124 from the RAM, which is approximately 7 cycles (at 16MHz): much longer than the
   125 4 cycles that would be required for 2MHz operation.
   126 
   127 Write operations expose some uncertainty about the relationship between the
   128 ULA's RAM access schedule and the PHI OUT clock. The Service Manual shows PHI
   129 IN (which should be the ULA's PHI OUT signal) as being synchronised with ~RAS.
   130 Since the CPU makes its address available potentially as late as 140ns after
   131 its PHI2 clock goes low (this clock being broadly similar to PHI OUT), it
   132 would make no sense to expect the ULA to be able perform a memory access
   133 immediately. What seems more likely is that the CPU makes data available, and
   134 this is written during the next 2MHz cycle.
   135 
   136 For the CPU, "L" indicates the point at which an address is taken from the CPU
   137 address bus, following a negative edge of PHI OUT, with "D" being the point at
   138 which data may be asserted for writing, following a positive edge of PHI OUT.
   139 Here, PHI OUT is driven at 1MHz. Given that ~WE needs to be driven low for
   140 writing or high for reading, and thus propagates RnW from the CPU, this would
   141 need to be done before data would be retrieved and, according to the TM4164EC4
   142 datasheet, even as late as the column address is presented and ~CAS brought
   143 low.
   144 
   145 It must be concluded that where accesses are interleaved between the CPU and
   146 ULA, the CPU access begins concurrently with the ULA access, with the CPU
   147 address and data retained by the ULA, and after the ULA access, the rest of
   148 the CPU transaction occurs in the following 2MHz cycle.
   149 
   150 See: Acorn Electron Advanced User Guide
   151 See: Acorn Electron Service Manual
   152      http://chrisacorns.computinghistory.org.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf
   153 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
   154 See: http://stardot.org.uk/forums/viewtopic.php?p=120438#p120438
   155 See: One of the Most Popular 65,536-Bit (64K) Dynamic RAMs The TMS 4164
   156      http://smithsonianchips.si.edu/augarten/p64.htm
   157 See: https://www.mups.co.uk/project/hardware/acorn_electron/
   158 See: Rockwell R650X and R651X Microprocessors (CPU)
   159 See: http://wilsonminesco.com/6502primer/
   160 
   161 A Note on 8-Bit Wide RAM Access
   162 -------------------------------
   163 
   164 It is worth considering the timing when 8 bits of data can be obtained at once
   165 from the RAM chips:
   166 
   167      Time (ns):  0-------------- 500------------- ...
   168    2 MHz cycle:  0               1                ...
   169    8 MHz cycle:  0   1   2   3   0   1   2   3    ...
   170                  /-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_ ...
   171           ~RAS:  /---\___________/---\___________ ...
   172           ~CAS:  /-------\_______/-------\_______ ...
   173 Address events:      A   B           A   B        ...
   174    Data events:          ...E            ...E     ...
   175            ~WE:          W               W        ...
   176 
   177       ~RAS ops:  1   0           1   0            ...
   178       ~CAS ops:  1       0       1       0        ...
   179 
   180    Address ops:     a.  b.          a.  b.        ...
   181       Data ops:            f     s         f      ...
   182 
   183        PHI OUT:  ----\_______/-------\_______/--- ...
   184            CPU:  D   .....L  ....D   .....L  .... ...
   185            RnW:      .....R          .....R        ...
   186 
   187 Here, "E" indicates the availability of an entire byte.
   188 
   189 Since only one fetch is required per 2MHz cycle, instead of two fetches for
   190 the 4-bit wide RAM arrangement, it seems likely that longer 8MHz cycles could
   191 be used to coordinate the necessary signalling.
   192 
   193 Another conceivable simplification from using an 8-bit wide RAM access channel
   194 with a single access within each 2MHz cycle is the possibility of allowing the
   195 CPU to signal directly to the RAM instead of having the ULA perform the access
   196 signalling on the CPU's behalf. Note that it is this more leisurely signalling
   197 that would allow the CPU to conduct accesses at 2MHz: the "compressed"
   198 signalling being beyond the capabilities of the CPU.
   199 
   200 Note that 16MHz cycles would still be needed for the pixel clock in MODE 0,
   201 which needs to output eight pixels per 2MHz cycle, producing 640 monochrome
   202 pixels per 80-byte line.
   203 
   204 An obvious consideration with regard to 8-bit wide access is whether the ULA
   205 could still conduct the "compressed" signalling for its own RAM accesses:
   206 
   207      Time (ns):  0-------------- 500------------- ...
   208    2 MHz cycle:  0               1                ...
   209   16 MHz cycle:  0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7  ...
   210                  /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ ...
   211           ~RAS:  /---\___________/---\___________ ...
   212           ~CAS:  /-----\___/-\___/-----\___/-\___ ...
   213 Address events:      A B     C       A B     C    ...
   214    Data events:        ...1  ...2      ...1  ...2 ...
   215            ~WE:        W               W          ...
   216 
   217       ~RAS ops:  1   0           1   0            ...
   218       ~CAS ops:  1     0   1 0   1     0   1 0    ...
   219 
   220    Address ops:     a.b.    c       a.b.    c     ...
   221       Data ops:  s         f     s         f      ...
   222 
   223        PHI OUT:  ----\_______/-------\_______/--- ...
   224            CPU:  D   .....L  ....D   .....L  .... ...
   225            RnW:      .....R          .....R        ...
   226 
   227 Here, "1" and "2" in the data events correspond to whole byte accesses,
   228 effectively upgrading the half-byte "F" and "S" events in the existing ULA
   229 arrangement.
   230 
   231 Although the provision of access for the CPU would adhere to the relevant
   232 timing constraints, providing only one byte per 2MHz cycle, the ULA could
   233 obtain two bytes per cycle. This would then free up bandwidth for the CPU in
   234 screen modes where the ULA would normally be dominant (MODE 0 to 3), albeit at
   235 the cost of extra buffering. Such buffering could also be done for modes where
   236 the bandwidth is shared (MODE 4 to 6), consolidating pairs of ULA accesses into
   237 single cycles and freeing up an extra cycle for CPU accesses.
   238 
   239 A further consideration is whether the CPU and ULA could access the memory on
   240 interleaved 4MHz cycles, thus replicating the arrangement used by the CPU and
   241 Video ULA on the BBC Micro. One potential obstacle is that the apparent 4MHz
   242 access rate employed by the ULA does not involve the complete process for
   243 accessing the RAM: upon setting up the address and issuing the ~RAS signal,
   244 the ULA is able to make a pair of column accesses on the same "row" of memory,
   245 effectively achieving an average access rate of 4MHz in an 8-bit
   246 configuration.
   247 
   248 However, if arbitrary pairs of column accesses were to be attempted, as would
   249 be required by CPU and ULA interleaving, the ~RAS signal would need to be
   250 re-issued with different addresses being set up. This would expand the time to
   251 access a memory location to beyond the period of a 4MHz cycle, making it
   252 impossible to employ interleaved accesses at such a rate.
   253 
   254 In conclusion, a strict interleaving strategy is not possible, but by using
   255 pixel data buffering and employing two ULA accesses per 2MHz cycle to obtain
   256 two bytes in that cycle, each adjacent 2MHz cycle can be given to the CPU,
   257 thus achieving an effective throughput during display update periods of 3
   258 bytes for every pair of cycles (2 bytes for the ULA, 1 byte for the CPU), and
   259 thus 1.5 bytes per cycle, giving an illusion of 3MHz access to RAM.
   260 
   261 Some other considerations apply to introducing 8-bit wide access. The ULA
   262 employs four pins for data transfer to and from the memory devices (RAM0..3),
   263 and obviously another four pins would be needed in an 8-bit wide scheme.
   264 However, there may have been a physical limitation on the number of pins
   265 permissible on a ULA package or the device's socket. This would necessitate
   266 the reassignment of pins, although few are readily available for such
   267 reassignment.
   268 
   269 One approach might involve connecting the RAM devices to the CPU data bus,
   270 with each line connecting to a different RAM chip. The signalling of the RAM
   271 would remain under the control of the ULA, thus preventing the RAM devices
   272 from interfering with other memory transfer operations, with the ROM
   273 signalling also remaining under the ULA's control. One potential disadvantage
   274 of this scheme would involve the elimination of the separate data paths
   275 between the CPU and ROM and between the ULA and RAM.
   276 
   277 Another approach might involve reclaiming the keyboard input pins (KBD0..3) as
   278 data pins for ULA access to RAM. This would necessitate the reorganisation of
   279 the keyboard interface, perhaps integrating the keyboard matrix more directly
   280 as a kind of ROM device. A bus transceiver could be used to isolate the
   281 keyboard inputs, with a pin being used to control the transceiver, since the
   282 keyboard data lines are pulled high. In effect, the transceiver would act as a
   283 kind of output enable for the keyboard.
   284 
   285 To make the matrix appear within the sideways ROM region of the memory map,
   286 A15 would need to be set to a high value and A14 to a low value. Signals A13
   287 to A0 would then be brought low to select the appropriate column, with the
   288 individual key states being made available via data lines, perhaps D3 to D0.
   289 This mostly retains the existing addressing arrangement and scanning
   290 mechanism. Internally, the ULA would continue to enable access to the keyboard
   291 through the ROM paging mechanism, but instead of integrating separate data
   292 pins into the CPU's data path, it would integrate the keyboard inputs using
   293 the transceiver.
   294 
   295 Enhancement: Keyboard Matrix Scanning
   296 -------------------------------------
   297 
   298 The keyboard scanning mechanism is presumably designed to be as inexpensive as
   299 possible, being driven by software and avoiding extra logic, but at the
   300 expense of occupying large regions of the memory map when paged in. A more
   301 efficient mapping of the keyboard columns could possibly be done using
   302 decoders such as the 74xx138 part which permits the decoding of three inputs
   303 to select one of eight outputs. Using two of these parts, six address lines
   304 would be dedicated to the keyboard columns as follows:
   305 
   306   A5...A3 select up to eight columns via one decoder
   307   A2...A0 select up to eight columns via another decoder
   308 
   309 In this arrangement, only one of the two ranges of pins would be used at any
   310 given time. If the ULA were to require a certain combination of the remaining
   311 address bits, a region as small as 64 bytes could be dedicated to the
   312 keyboard.
   313 
   314 A more efficient arrangement could be used by introducing logic that allows
   315 the decoders to work together to address the keyboard:
   316 
   317   A2...A0 select up to eight columns via both decoders
   318   A3 would enable one decoder if low and the other decoder if high
   319 
   320 With ULA constraints on the remaining address bits, a 16-byte region could be
   321 used to represent the keyboard.
   322 
   323 A further refinement might involve combining the existing columns into groups
   324 of eight keys. This would reduce the number of columns to seven, requiring
   325 only three address lines, with all eight data lines being used to read the
   326 matrix.
   327 
   328 On the BBC Micro, the system 6522 VIA is used to monitor and read from the
   329 keyboard. The memory locations involved with this chip are located in the
   330 region from &FE40 to &FE7F inclusive, although the memory is allocated in a
   331 way that is appropriate to operate that chip, as opposed to merely exposing
   332 the keyboard matrix.
   333 
   334 Enhancement: Hardware Device Selection
   335 --------------------------------------
   336 
   337 An alternative to the existing, rather cumbersome, sideways ROM mapping of the
   338 keyboard might involve making it accessible via a hardware-related memory page
   339 like page FE. With ULA addresses confined to FE0x, and with the ULA itself
   340 having to trap accesses to page FE, the page selection signal might be brought
   341 out of the ULA instead of any dedicated signal for the keyboard. Various
   342 address lines corresponding to A7 through A4, or a subset of these, could be
   343 fed into a decoder to permit the selection of other devices, with the keyboard
   344 being one of these.
   345 
   346 Meanwhile, a more efficient keyboard mapping using the above matrix
   347 enhancement would permit the different keyboard columns to appear as a group
   348 of sixteen or eight bytes. Thus:
   349 
   350   A15...A8 select page FE
   351    A7...A4 select a device or peripheral
   352    A3...A0 select a register or keyboard column
   353 
   354 Conceivably, devices such as sound generators could be mapped to device
   355 regions.
   356 
   357 CPU Clock Notes
   358 ---------------
   359 
   360 "The 6502 receives an external square-wave clock input signal on pin 37, which
   361 is usually labeled PHI0. [...] This clock input is processed within the 6502
   362 to form two clock outputs: PHI1 and PHI2 (pins 3 and 39, respectively). PHI2
   363 is essentially a copy of PHI0; more specifically, PHI2 is PHI0 after it's been
   364 through two inverters and a push-pull amplifier. The same network of
   365 transistors within the 6502 which generates PHI2 is also tied to PHI1, and
   366 generates PHI1 as the inverse of PHI0. The reason why PHI1 and PHI2 are made
   367 available to external devices is so that they know when they can access the
   368 CPU. When PHI1 is high, this means that external devices can read from the
   369 address bus or data bus; when PHI2 is high, this means that external devices
   370 can write to the data bus."
   371 
   372 See: http://lateblt.livejournal.com/88105.html
   373 
   374 "The 6502 has a synchronous memory bus where the master clock is divided into
   375 two phases (Phase 1 and Phase 2). The address is always generated during Phase
   376 1 and all memory accesses take place during Phase 2."
   377 
   378 See: http://www.jmargolin.com/vgens/vgens.htm
   379 
   380 Thus, the inverse of PHI OUT provides the "other phase" of the clock. "During
   381 Phase 1" means when PHI0 - really PHI2 - is high and "during Phase 2" means
   382 when PHI1 is high.
   383 
   384 Bandwidth Figures
   385 -----------------
   386 
   387 Using an observation of 128 2MHz cycles per scanline, 256 active lines and 312
   388 total lines, with 80 cycles occurring in the active periods of display
   389 scanlines, the following bandwidth calculations can be performed:
   390 
   391 Total theoretical maximum:
   392        128 cycles * 312 lines
   393      = 39936 bytes
   394 
   395 MODE 0, 1, 2:
   396 ULA:    80 cycles * 256 lines
   397      = 20480 bytes
   398 CPU:    48 cycles / 2 * 256 lines
   399      + 128 cycles / 2 * (312 - 256) lines
   400      = 9728 bytes
   401 
   402 MODE 3:
   403 ULA:    80 cycles * 24 rows * 8 lines
   404      = 15360 bytes
   405 CPU:    48 cycles / 2 * 24 rows * 8 lines
   406      + 128 cycles / 2 * (312 - (24 rows * 8 lines))
   407      = 12288 bytes
   408 
   409 MODE 4, 5:
   410 ULA:    40 cycles * 256 lines
   411      = 10240 bytes
   412 CPU:   (40 cycles + 48 cycles / 2) * 256 lines
   413      + 128 cycles / 2 * (312 - 256) lines
   414      = 19968 bytes
   415 
   416 MODE 6:
   417 ULA:    40 cycles * 24 rows * 8 lines
   418      = 7680 bytes
   419 CPU:   (40 cycles + 48 cycles / 2) * 24 rows * 8 lines
   420      + 128 cycles / 2 * (312 - (24 rows * 8 lines))
   421      = 19968 bytes
   422 
   423 Here, the division of 2 for CPU accesses is performed to indicate that the CPU
   424 only uses every other access opportunity even in uncontended periods. See the
   425 2MHz RAM Access enhancement below for bandwidth calculations that consider
   426 this limitation removed.
   427 
   428 A summary of the bandwidth figures is as follows (with extra timing details
   429 described below):
   430 
   431                 Standard ULA    % Total   Slowdown  BBC-10s BBC-34s
   432 MODE 0, 1, 2    9728 bytes      24%       4.11      43s     105s
   433 MODE 3          12288 bytes     31%       3.25      34s
   434 MODE 4, 5       19968 bytes     50%       2         20s
   435 MODE 6          19968 bytes     50%       2         20s     50s
   436 
   437 The review of the Electron in Practical Computing (October 1983) provides a
   438 concise overview of the RAM access limitations and gives timing comparisons
   439 between modes and BBC Micro performance. In the above, "BBC-10s" is the
   440 measured or stated time given for a program taking 10 seconds on the BBC
   441 Micro, whereas "BBC-34s" is the apparently measured time given for the
   442 "Persian" program taking 34 seconds to complete on the BBC Micro, with a
   443 "quick" mode presumably switching to MODE 6 using the ULA directly in order to
   444 reduce display bandwidth usage while the program draws to the screen.
   445 Evidently, the measured slowdown is slightly lower than the theoretical
   446 slowdown, most likely due to the running time not being entirely dominated by
   447 RAM access performance characteristics.
   448 
   449 Video Timing
   450 ------------
   451 
   452 According to 8.7 in the Service Manual, and the PAL Wikipedia page,
   453 approximately 4.7µs is used for the sync pulse, 5.7µs for the "back porch"
   454 (including the "colour burst"), and 1.65µs for the "front porch", totalling
   455 12.05µs and thus leaving 51.95µs for the active video signal for each
   456 scanline. As the Service Manual suggests in the oscilloscope traces, the
   457 display information is transmitted more or less centred within the active
   458 video period since the ULA will only be providing pixel data for 40µs in each
   459 scanline.
   460 
   461 Each 62.5ns cycle happens to correspond to 64µs divided by 1024, meaning that
   462 each scanline can be divided into 1024 cycles, although only 640 at most are
   463 actively used to provide pixel data. Pixel data production should only occur
   464 within a certain period on each scanline, approximately 262 cycles after the
   465 start of hsync:
   466 
   467   active video period = 51.95µs
   468   pixel data period = 40µs
   469   total silent period = 51.95µs - 40µs = 11.95µs
   470   silent periods (before and after) = 11.95µs / 2 = 5.975µs
   471   hsync and back porch period = 4.7µs + 5.7µs = 10.4µs
   472   time before pixel data period = 10.4µs + 5.975µs = 16.375µs
   473   pixel data period start cycle = 16.375µs / 62.5ns = 262
   474 
   475 By choosing a number divisible by 8, the RAM access mechanism can be
   476 synchronised with the pixel production. Thus, 256 is a more appropriate start
   477 cycle, where the HS (horizontal sync) signal corresponding to the 4µs sync
   478 pulse (or "normal sync" pulse as described by the "PAL TV timing and voltages"
   479 document) occurs at cycle 0.
   480 
   481 To summarise:
   482 
   483   HS signal starts at cycle 0 on each horizontal scanline
   484   HS signal ends approximately 4µs later at cycle 64
   485   Pixel data starts approximately 12µs later at cycle 256
   486 
   487 "Re: Electron Memory Contention" provides measurements that appear consistent
   488 with these calculations.
   489 
   490 The "vertical blanking period", meaning the period before picture information
   491 in each field is 25 lines out of 312 (or 313) and thus lasts for 1.6ms. Of
   492 this, 2.5 lines occur before the vsync (field sync) which also lasts for 2.5
   493 lines. Thus, the first visible scanline on the first field of a frame occurs
   494 half way through the 23rd scanline period measured from the start of vsync
   495 (indicated by "V" in the diagrams below):
   496 
   497                                         10                  20    23
   498   Line in frame:       1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8
   499     Line from 1:       0                                          22 3
   500  Line on screen: .:::::VVVVV:::::                                   12233445566
   501                   |_________________________________________________|
   502                            25 line vertical blanking period
   503 
   504 In the second field of a frame, the first visible scanline coincides with the
   505 24th scanline period measured from the start of line 313 in the frame:
   506 
   507                310                                                 336
   508   Line in frame: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
   509   Line from 313:       0                                            23 4
   510  Line on screen: 88:::::VVVVV::::                                    11223344
   511                288 |                                                 |
   512                    |_________________________________________________|
   513                             25 line vertical blanking period
   514 
   515 In order to consider only full lines, we might consider the start of each
   516 frame to occur 23 lines after the start of vsync.
   517 
   518 Again, it is likely that pixel data production should only occur on scanlines
   519 within a certain period on each frame. The "625/50" document indicates that
   520 only a certain region is "safe" to use, suggesting a vertically centred region
   521 with approximately 15 blank lines above and below the picture. However, the
   522 "PAL TV timing and voltages" document suggests 28 blank lines above and below
   523 the picture. This would centre the 256 lines within the 312 lines of each
   524 field and thus provide a start of picture approximately 5.5 or 5 lines after
   525 the end of the blanking period or 28 or 27.5 lines after the start of vsync.
   526 
   527 To summarise:
   528 
   529   CSYNC signal starts at cycle 0
   530   CSYNC signal ends approximately 160µs (2.5 lines) later at cycle 2560
   531   Start of line occurs approximately 1632µs (5.5 lines) later at cycle 28672
   532 
   533 See: http://en.wikipedia.org/wiki/PAL
   534 See: http://en.wikipedia.org/wiki/Analog_television#Structure_of_a_video_signal
   535 See: The 625/50 PAL Video Signal and TV Compatible Graphics Modes
   536      http://lipas.uwasa.fi/~f76998/video/modes/
   537 See: PAL TV timing and voltages
   538      http://www.retroleum.co.uk/electronics-articles/pal-tv-timing-and-voltages/
   539 See: Line Standards
   540      http://www.pembers.freeserve.co.uk/World-TV-Standards/Line-Standards.html
   541 See: Horizontal Blanking Interval of 405-, 525-, 625- and 819-Line Standards
   542      http://www.pembers.freeserve.co.uk/World-TV-Standards/HBI.pdf
   543 See: Re: Electron Memory Contention
   544      http://www.stardot.org.uk/forums/viewtopic.php?p=134109#p134109
   545 
   546 RAM Integrated Circuits
   547 -----------------------
   548 
   549 Unicorn Electronics appears to offer 4164 RAM chips (as well as 6502 series
   550 CPUs such as the 6502, 6502A, 6502B and 65C02). These 4164 devices are
   551 available in 100ns (4164-100), 120ns (4164-120) and 150ns (4164-150) variants,
   552 have 16 pins and address 65536 bits through a 1-bit wide channel. Similarly,
   553 ByteDelight.com sell 4164 devices primarily for the ZX Spectrum.
   554 
   555 The documentation for the Electron mentions 4164-15 RAM chips for IC4-7, and
   556 the Samsung-produced KM41464 series is apparently equivalent to the Texas
   557 Instruments 4164 chips presumably used in the Electron.
   558 
   559 The TM4164EC4 series combines 4 64K x 1b units into a single package and
   560 appears similar to the TM4164EA4 featured on the Electron's circuit diagram
   561 (in the Advanced User Guide but not the Service Manual), and it also has 22
   562 pins providing 3 additional inputs and 3 additional outputs over the 16 pins
   563 of the individual 4164-15 modules, presumably allowing concurrent access to
   564 the packaged memory units.
   565 
   566 As far as currently available replacements are concerned, the NTE4164 is a
   567 potential candidate: according to the Vetco Electronics entry, it is
   568 supposedly a replacement for the TMS4164-15 amongst many other parts. Similar
   569 parts include the NTE2164 and the NTE6664, both of which appear to have
   570 largely the same performance and connection characteristics. Meanwhile, the
   571 NTE21256 appears to be a 16-pin replacement with four times the capacity that
   572 maintains the single data input and output pins. Using the NTE21256 as a
   573 replacement for all ICs combined would be difficult because of the single bit
   574 output.
   575 
   576 Another device equivalent to the 4164-15 appears to be available under the
   577 code 41662 from Jameco Electronics as the Siemens HYB 4164-2. The Jameco Web
   578 site lists data sheets for other devices on the same page, but these are
   579 different and actually appear to be provided under the 41574 product code (but
   580 are listed under 41464-10) and appear to be replacements for the TM4164EC4:
   581 the Samsung KM41464A-15 and NEC µPD41464 employ 18 pins, eliminating 4 pins by
   582 employing 4 pins for both input and output.
   583 
   584             Pins    I/O pins    Row access  Column access
   585             ----    --------    ----------  -------------
   586 TM4164EC4   22      4 + 4       150ns (15)  90ns (15)
   587 KM41464AP   18      4           150ns (15)  75ns (15)
   588 NTE21256    16      1 + 1       150ns       75ns
   589 HYB 4164-2  16      1 + 1       150ns       100ns
   590 µPD41464    18      4           120ns (12)  60ns (12)
   591 
   592 See: TM4164EC4 65,536 by 4-Bit Dynamic RAM Module
   593      https://www.rocelec.com/part/REITM4164EC4-15L
   594 See: Dynamic RAMS
   595      http://www.unicornelectronics.com/IC/DYNAMIC.html
   596 See: New old stock 8x 4164 chips
   597      http://www.bytedelight.com/?product=8x-4164-chips-new-old-stock
   598 See: KM4164B 64K x 1 Bit Dynamic RAM with Page Mode
   599      http://images.ihscontent.net/vipimages/VipMasterIC/IC/SAMS/SAMSD020/SAMSD020-45.pdf
   600 See: NTE2164 Integrated Circuit 65,536 X 1 Bit Dynamic Random Access Memory
   601      http://www.vetco.net/catalog/product_info.php?products_id=2806
   602 See: NTE4164 - IC-NMOS 64K DRAM 150NS
   603      http://www.vetco.net/catalog/product_info.php?products_id=3680
   604 See: NTE21256 - IC-256K DRAM 150NS
   605      http://www.vetco.net/catalog/product_info.php?products_id=2799
   606 See: NTE21256 262,144-Bit Dynamic Random Access Memory (DRAM)
   607      http://www.nteinc.com/specs/21000to21999/pdf/nte21256.pdf
   608 See: NTE6664 - IC-MOS 64K DRAM 150NS
   609      http://www.vetco.net/catalog/product_info.php?products_id=5213
   610 See: NTE6664 Integrated Circuit 64K-Bit Dynamic RAM
   611      http://www.nteinc.com/specs/6600to6699/pdf/nte6664.pdf
   612 See: 4164-150: MAJOR BRANDS
   613      http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41662_-1
   614 See: HYB 4164-1, HYB 4164-2, HYB 4164-3 65,536-Bit Dynamic Random Access Memory (RAM)
   615      http://www.jameco.com/Jameco/Products/ProdDS/41662SIEMENS.pdf
   616 See: KM41464A NMOS DRAM 64K x 4 Bit Dynamic RAM with Page Mode
   617      http://www.jameco.com/Jameco/Products/ProdDS/41662SAM.pdf
   618 See: NEC µ41464 65,536 x 4-Bit Dynamic NMOS RAM
   619      http://www.jameco.com/Jameco/Products/ProdDS/41662NEC.pdf
   620 See: 41464-10: MAJOR BRANDS
   621      http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41574_-1
   622 
   623 Interrupts
   624 ----------
   625 
   626 The ULA generates IRQs (maskable interrupts) according to certain conditions
   627 and these conditions are controlled by location &FE00:
   628 
   629   * Vertical sync (bottom of displayed screen)
   630   * 50MHz real time clock
   631   * Transmit data empty
   632   * Receive data full
   633   * High tone detect
   634 
   635 The ULA is also used to clear interrupt conditions through location &FE05. Of
   636 particular significance is bit 7, which must be set if an NMI (non-maskable
   637 interrupt) has occurred and has thus suspended ULA access to memory, restoring
   638 the normal function of the ULA.
   639 
   640 ROM Paging
   641 ----------
   642 
   643 Accessing different ROMs involves bits 0 to 3 of &FE05. Some special ROM
   644 mappings exist:
   645 
   646    8    keyboard
   647    9    keyboard (duplicate)
   648   10    BASIC ROM
   649   11    BASIC ROM (duplicate)
   650 
   651 Paging in a ROM involves the following procedure:
   652 
   653  1. Assert ROM page enable (bit 3) together with a ROM number n in bits 0 to
   654     2, corresponding to ROM number 8+n, such that one of ROMs 12 to 15 is
   655     selected.
   656  2. Where a ROM numbered from 0 to 7 is to be selected, set bit 3 to zero
   657     whilst writing the desired ROM number n in bits 0 to 2.
   658 
   659 See: http://stardot.org.uk/forums/viewtopic.php?p=136686#p136686
   660 
   661 Keyboard Access
   662 ---------------
   663 
   664 The keyboard pages appear to be accessed at 1MHz just like the RAM.
   665 
   666 See: https://stardot.org.uk/forums/viewtopic.php?p=254155#p254155
   667 
   668 Shadow/Expanded Memory
   669 ----------------------
   670 
   671 The Electron exposes all sixteen address lines and all eight data lines
   672 through the expansion bus. Using such lines, it is possible to provide
   673 additional memory - typically sideways ROM and RAM - on expansion cards and
   674 through cartridges, although the official cartridge specification provides
   675 fewer address lines and only seeks to provide access to memory in 16K units.
   676 
   677 Various modifications and upgrades were developed to offer "turbo"
   678 capabilities to the Electron, permitting the CPU to access a separate 8K of
   679 RAM at 2MHz, presumably preventing access to the low 8K of RAM accessible via
   680 the ULA through additional logic. However, an enhanced ULA might support
   681 independent CPU access to memory over the expansion bus by allowing itself to
   682 be discharged from providing access to memory, potentially for a range of
   683 addresses, and for the CPU to communicate with external memory uninterrupted.
   684 
   685 Sideways RAM/ROM and Upper Memory Access
   686 ----------------------------------------
   687 
   688 Although the ULA controls the CPU clock, effectively slowing or stopping the
   689 CPU when the ULA needs to access screen memory, it is apparently able to allow
   690 the CPU to access addresses of &8000 and above - the upper region of memory -
   691 at 2MHz independently of any access to RAM that the ULA might be performing,
   692 only blocking the CPU if it attempts to access addresses of &7FFF and below
   693 during any ULA memory access - the lower region of memory - by stopping or
   694 stalling its clock.
   695 
   696 Thus, the ULA remains aware of the level of the A15 line, only inhibiting the
   697 CPU clock if the line goes low, when the CPU is attempting to access the lower
   698 region of memory.
   699 
   700 Hardware Scrolling (and Enhancement)
   701 ------------------------------------
   702 
   703 On the standard ULA, &FE02 and &FE03 map to a 9 significant bits address with
   704 the least significant 5 bits being zero, thus limiting the scrolling
   705 resolution to 64 bytes. An enhanced ULA could support a resolution of 2 bytes
   706 using the same layout of these addresses.
   707 
   708 |--&FE02--------------| |--&FE03--------------|
   709 XX XX 14 13 12 11 10 09 08 07 06 XX XX XX XX XX
   710 
   711    XX 14 13 12 11 10 09 08 07 06 05 04 03 02 01 XX
   712 
   713 Arguably, a resolution of 8 bytes is more useful, since the mapping of screen
   714 memory to pixel locations is character oriented. A change in 8 bytes would
   715 permit a horizontal scrolling resolution of 2 pixels in MODE 2, 4 pixels in
   716 MODE 1 and 5, and 8 pixels in MODE 0, 3 and 6. This resolution is actually
   717 observed on the BBC Micro (see 18.11.2 in the BBC Microcomputer Advanced User
   718 Guide).
   719 
   720 One argument for a 2 byte resolution is smooth vertical scrolling. A pitfall
   721 of changing the screen address by 2 bytes is the change in the number of lines
   722 from the initial and final character rows that need reading by the ULA, which
   723 would need to maintain this state information (although this is a relatively
   724 trivial change). Another pitfall is the complication that might be introduced
   725 to software writing bitmaps of character height to the screen.
   726 
   727 See: http://pastraiser.com/computers/acornelectron/acornelectron.html
   728 
   729 Enhancement: Mode Layouts
   730 -------------------------
   731 
   732 Merely changing the screen memory mappings in order to have Archimedes-style
   733 row-oriented screen addresses (instead of character-oriented addresses) could
   734 be done for the existing modes, but this might not be sufficiently beneficial,
   735 especially since accessing regions of the screen would involve incrementing
   736 pointers by amounts that are inconvenient on an 8-bit CPU.
   737 
   738 However, instead of using a Archimedes-style mapping, column-oriented screen
   739 addresses could be more feasibly employed: incrementing the address would
   740 reference the vertical screen location below the currently-referenced location
   741 (just as occurs within characters using the existing ULA); instead of
   742 returning to the top of the character row and referencing the next horizontal
   743 location after eight bytes, the address would reference the next character row
   744 and continue to reference locations downwards over the height of the screen
   745 until reaching the bottom; at the bottom, the next location would be the next
   746 horizontal location at the top of the screen.
   747 
   748 In other words, the memory layout for the screen would resemble the following
   749 (for MODE 2):
   750 
   751   &3000 &3100       ... &7F00
   752   &3001 &3101
   753   ...   ...
   754   &3007
   755   &3008
   756   ...
   757   ...                   ...
   758   &30FF             ... &7FFF
   759 
   760 Since there are 256 pixel rows, each column of locations would be addressable
   761 using the low byte of the address. Meanwhile, the high byte would be
   762 incremented to address different columns. Thus, addressing screen locations
   763 would become a lot more convenient and potentially much more efficient for
   764 certain kinds of graphical output.
   765 
   766 One potential complication with this simplified addressing scheme arises with
   767 hardware scrolling. Vertical hardware scrolling by one pixel row (not supported
   768 with the existing ULA) would be achieved by incrementing or decrementing the
   769 screen start address; by one character row, it would involve adding or
   770 subtracting 8. However, the ULA only supports multiples of 64 when changing the
   771 screen start address. Thus, if such a scheme were to be adopted, three
   772 additional bits would need to be supported in the screen start register (see
   773 "Hardware Scrolling (and Enhancement)" for more details). However, horizontal
   774 scrolling would be much improved even under the severe constraints of the
   775 existing ULA: only adjustments of 256 to the screen start address would be
   776 required to produce single-location scrolling of as few as two pixels in MODE 2
   777 (four pixels in MODEs 1 and 5, eight pixels otherwise).
   778 
   779 More disruptive is the effect of this alternative layout on software.
   780 Presumably, compatibility with the BBC Micro was the primary goal of the
   781 Electron's hardware design. With the character-oriented screen layout in
   782 place, system software (and application software accessing the screen
   783 directly) would be relying on this layout to run on the Electron with little
   784 or no modification. Although it might have been possible to change the system
   785 software to use this column-oriented layout instead, this would have incurred
   786 a development cost and caused additional work porting things like games to the
   787 Electron. Moreover, a separate branch of the software from that supporting the
   788 BBC Micro and closer derivatives would then have needed maintaining.
   789 
   790 The decision to use the character-oriented layout in the BBC Micro may have
   791 been related to the choice of circuitry and to facilitate a convenient
   792 hardware implementation, and by the time the Electron was planned, it was too
   793 late to do anything about this somewhat unfortunate choice.
   794 
   795 Pixel Layouts
   796 -------------
   797 
   798 The pixel layouts are as follows:
   799 
   800   Modes         Depth (bpp)     Pixels (from bits)
   801   -----         -----------     ------------------
   802   0, 3, 4, 6    1               7 6 5 4 3 2 1 0
   803   1, 5          2               73 62 51 40
   804   2             4               7531 6420
   805 
   806 Since the ULA reads a half-byte at a time, one might expect it to attempt to
   807 produce pixels for every half-byte, as opposed to handling entire bytes.
   808 However, the pixel layout is not conducive to producing pixels as soon as a
   809 half-byte has been read for a given full-byte location: in 1bpp modes the
   810 first four pixels can indeed be produced, but in 2bpp and 4bpp modes the pixel
   811 data is spread across the entire byte in different ways.
   812 
   813 An alternative arrangement might be as follows:
   814 
   815   Modes         Depth (bpp)     Pixels (from bits)
   816   -----         -----------     ------------------
   817   0, 3, 4, 6    1               7 6 5 4 3 2 1 0
   818   1, 5          2               76 54 32 10
   819   2             4               7654 3210
   820 
   821 Just as the mode layouts were presumably decided by compatibility with the BBC
   822 Micro, the pixel layouts will have been maintained for similar reasons.
   823 Unfortunately, this layout prevents any optimisation of the ULA for handling
   824 half-byte pixel data generally.
   825 
   826 Enhancement: The Missing MODE 4
   827 -------------------------------
   828 
   829 The Electron inherits its screen mode selection from the BBC Micro, where MODE
   830 3 is a text version of MODE 0, and where MODE 6 is a text version of MODE 4.
   831 Neither MODE 3 nor MODE 6 is a genuine character-based text mode like MODE 7,
   832 however, and they are merely implemented by skipping two scanlines in every
   833 ten after the eight required to produce a character line. Thus, such modes
   834 provide a 24-row display.
   835 
   836 In principle, nothing prevents this "text mode" effect being applied to other
   837 modes. The 20-column modes are not well-suited to displaying text, which
   838 leaves MODE 1 which, unlike MODEs 3 and 6, can display 4 colours rather than
   839 2. Although the need for a non-monochrome 40-column text mode is addressed by
   840 MODE 7 on the BBC Micro, the Electron lacks such a mode.
   841 
   842 If the 4-colour, 24-row variant of MODE 1 were to be provided, logically it
   843 would occupy MODE 4 instead of the current MODE 4:
   844 
   845   Screen mode  Size (kilobytes)  Colours  Rows  Resolution
   846   -----------  ----------------  -------  ----  ----------
   847   0            20                2        32    640x256
   848   1            20                4        32    320x256
   849   2            20                16       32    160x256
   850   3            16                2        24    640x256
   851   4 (new)      16                4        24    320x256
   852   4 (old)      10                2        32    320x256
   853   5            10                4        32    160x256
   854   6            8                 2        24    320x256
   855 
   856 Thus, for increasing mode numbers, the size of each mode would be the same or
   857 less than the preceding mode.
   858 
   859 Enhancement: Display Mode Property Control
   860 ------------------------------------------
   861 
   862 It is rather curious that the ULA supports the mode numbers directly in bits 3
   863 to 5 of &FE07 since these would presumably need to be decoded in order to set
   864 the fundamental properties of the display mode. These properties are as
   865 follows:
   866 
   867  * Screen data retrieval rate: number of fetches per pair of 2MHz cycles
   868  * Pixel colour depth
   869  * Text mode vertical spacing
   870 
   871 From these, the following properties emerge:
   872 
   873   Property                        Influences
   874   --------                        ----------
   875   Character row size (bytes)      Retrieval rate
   876 
   877   Number of character rows        Text mode setting
   878 
   879   Display size (bytes)            Retrieval rate (character row size)
   880                                   Text mode setting (number of rows)
   881 
   882   Pixel frequency                 Retrieval rate
   883   Horizontal resolution (pixels)  Colour depth
   884 
   885 One can imagine a register bitfield arrangement as follows:
   886 
   887   Field             Values                  Formula
   888   -----             ------                  -------
   889   Pixel depth       00: 1 bit per pixel     log2(depth)
   890                     01: 2 bits per pixel
   891                     10: 4 bits per pixel
   892 
   893   Retrieval rate     0: twice               2 - fetches per cycle pair
   894                      1: once
   895 
   896   Text mode enable   0: disable/off         text mode enabled
   897                      1: enable/on
   898 
   899 This arrangement would require four bits. However, one bit in &FE07 is
   900 seemingly inactive and might possibly be reallocated.
   901 
   902 The resulting combination of properties would permit all of the existing modes
   903 plus some additional ones, including the missing MODE 4 mentioned above. With
   904 the bitfields above ordered from the most significant bits to the least
   905 significant bits providing the low-level "mode" values, the following table
   906 can be produced:
   907 
   908   Screen mode  Depth Rate   Text  Size (K)  Colours  Rows  Resolution
   909   -----------  ----- ----   ----  --------  -------  ----  ----------
   910   0  (0000)    1     twice  off   20        2        32    640x256    (MODE 0)
   911   1  (0001)    1     twice  on    16        2        24    640x256    (MODE 3)
   912   2  (0010)    1     once   off   10        2        32    320x256    (MODE 4)
   913   3  (0011)    1     once   on    8         2        24    320x256    (MODE 6)
   914   4  (0100)    2     twice  off   20        4        32    320x256    (MODE 1)
   915   5  (0101)    2     twice  on    16        4        24    320x256
   916   6  (0110)    2     once   off   10        4        32    160x256    (MODE 5)
   917   7  (0111)    2     once   on    8         4        24    160x256
   918   8  (1000)    4     twice  off   20        16       32    160x256    (MODE 2)
   919   9  (1001)    4     twice  on    16        16       24    160x256
   920   10 (1010)    4     once   off   10        16       32    80x256
   921   11 (1011)    4     once   on    8         16       24    80x256
   922 
   923 The existing modes would be covered in a way that is incompatible with the
   924 existing numbering, thus requiring a table in software, but additional text
   925 modes would be provided for MODE 1, MODE 5 and MODE 2. An additional two lower
   926 resolution modes would also be conceivable within this scheme, requiring the
   927 stretching of 16MHz pixels by a factor of eight to yield 80 pixels per
   928 scanline. The utility of such modes is questionable and such modes might not
   929 be supported.
   930 
   931 Enhancement: 2MHz RAM Access
   932 ----------------------------
   933 
   934 Given that the CPU and ULA both access RAM at 2MHz, but given that the CPU
   935 when not competing with the ULA only accesses RAM every other 2MHz cycle (as
   936 if the ULA still needed to access the RAM), one useful enhancement would be a
   937 mechanism to let the CPU take over the ULA cycles outside the ULA's period of
   938 activity comparable to the way the ULA takes over the CPU cycles in MODE 0 to
   939 3.
   940 
   941 Thus, the RAM access cycles would resemble the following in MODE 0 to 3:
   942 
   943   Upon a transition from display cycles: UUUUCCCC (instead of UUUUC_C_)
   944   On a non-display line:                 CCCCCCCC (instead of C_C_C_C_)
   945 
   946 In MODE 4 to 6:
   947  
   948   Upon a transition from display cycles: CUCUCCCC (instead of CUCUC_C_)
   949   On a non-display line:                 CCCCCCCC (instead of C_C_C_C_)
   950 
   951 This would improve CPU bandwidth as follows:
   952 
   953                 Standard ULA    Enhanced ULA    % Total Bandwidth   Speedup
   954 MODE 0, 1, 2    9728 bytes      19456 bytes     24% -> 49%          2
   955 MODE 3          12288 bytes     24576 bytes     31% -> 62%          2
   956 MODE 4, 5       19968 bytes     29696 bytes     50% -> 74%          1.5
   957 MODE 6          19968 bytes     32256 bytes     50% -> 81%          1.6
   958 
   959 (Here, the uncontended total 2MHz bandwidth for a display period would be
   960 39936 bytes, being 128 cycles per line over 312 lines.)
   961 
   962 With such an enhancement, MODE 0 to 3 experience a doubling of CPU bandwidth
   963 because all access opportunities to RAM are doubled. Meanwhile, in the other
   964 modes, some CPU accesses occur alongside ULA accesses and thus cannot be
   965 doubled, but the CPU bandwidth increase is still significant.
   966 
   967 Unfortunately, the mechanism for accessing the RAM is too slow to provide data
   968 within the time constraints of 2MHz operation. There is no time remaining in a
   969 2MHz cycle for the CPU to receive and process any retrieved data once the
   970 necessary signalling has been performed.
   971 
   972 The only way for the CPU to be able to access the RAM quickly enough would be
   973 to do away with the double 4-bit access mechanism and to have a single 8-bit
   974 channel to the memory. This would require twice as many 1-bit RAM chips or a
   975 different kind of RAM chip, but it would also potentially simplify the ULA.
   976 
   977 The section on 8-bit wide RAM access discusses the possibilities around
   978 changing the memory architecture, also describing the possibility of ULA
   979 accesses achieving two bytes per 2MHz cycle due to the doubling of the memory
   980 channel, leaving every other access free for the CPU during the display period
   981 in MODE 0 to 3...
   982 
   983   Standard display period: UUUUUUUU
   984   Modified display period: UCUCUCUC
   985 
   986 ...and consolidating accesses in MODE 4 to 6:
   987 
   988   Standard display period: UCUCUCUC
   989   Modified display period: UCCCUCCC
   990 
   991 Together with the enhancements for non-display periods, such an "Enhanced+ ULA"
   992 would perform as follows:
   993 
   994                 Standard ULA    Enhanced+ ULA   % Total Bandwidth   Speedup
   995 MODE 0, 1, 2    9728 bytes      29696 bytes     24% -> 74%          3.1
   996 MODE 3          12288 bytes     32256 bytes     31% -> 81%          2.6
   997 MODE 4, 5       19968 bytes     34816 bytes     50% -> 87%          1.7
   998 MODE 6          19968 bytes     36096 bytes     50% -> 90%          1.8
   999 
  1000 Of course, the principal enhancement would be the wider memory channel, with
  1001 more buffering in the ULA being its contribution to this arrangement.
  1002 
  1003 Enhancement: Region Blanking
  1004 ----------------------------
  1005 
  1006 The problem of permitting character-oriented blitting in programs whilst
  1007 scrolling the screen by sub-character amounts could be mitigated by permitting
  1008 a region of the display to be blank, such as the final lines of the display.
  1009 Consider the following vertical scrolling by 2 bytes that would cause an
  1010 initial character row of 6 lines and a final character row of 2 lines:
  1011 
  1012     6 lines - initial, partial character row
  1013   248 lines - 31 complete rows
  1014     2 lines - final, partial character row
  1015 
  1016 If a routine were in use that wrote 8 line bitmaps to the partial character
  1017 row now split in two, it would be advisable to hide one of the regions in
  1018 order to prevent content appearing in the wrong place on screen (such as
  1019 content meant to appear at the top "leaking" onto the bottom). Blanking 6
  1020 lines would be sufficient, as can be seen from the following cases.
  1021 
  1022 Scrolling up by 2 lines:
  1023 
  1024     6 lines - initial, partial character row
  1025   240 lines - 30 complete rows
  1026     4 lines - part of 1 complete row
  1027   -----------------------------------------------------------------
  1028     4 lines - part of 1 complete row (hidden to maintain 250 lines)
  1029     2 lines - final, partial character row (hidden)
  1030 
  1031 Scrolling down by 2 lines:
  1032 
  1033     2 lines - initial, partial character row
  1034   248 lines - 31 complete rows
  1035   ----------------------------------------------------------
  1036     6 lines - final, partial character row (hidden)
  1037 
  1038 Thus, in this case, region blanking would impose a 250 line display with the
  1039 bottom 6 lines blank.
  1040 
  1041 See the description of the display suspend enhancement for a more efficient
  1042 way of blanking lines than merely blanking the palette whilst allowing the CPU
  1043 to perform useful work during the blanking period.
  1044 
  1045 To control the blanking or suspending of lines at the top and bottom of the
  1046 display, a memory location could be dedicated to the task: the upper 4 bits
  1047 could define a blanking region of up to 16 lines at the top of the screen,
  1048 whereas the lower 4 bits could define such a region at the bottom of the
  1049 screen. If more lines were required, two locations could be employed, allowing
  1050 the top and bottom regions to occupy the entire screen.
  1051 
  1052 Enhancement: Screen Height Adjustment
  1053 -------------------------------------
  1054 
  1055 The height of the screen could be configurable in order to reduce screen
  1056 memory consumption. This is not quite done in MODE 3 and 6 since the start of
  1057 the screen appears to be rounded down to the nearest page, but by reducing the
  1058 height by amounts more than a page, savings would be possible. For example:
  1059 
  1060   Screen width  Depth  Height  Bytes per line  Saving in bytes  Start address
  1061   ------------  -----  ------  --------------  ---------------  -------------
  1062   640           1      252     80              320              &3140 -> &3100
  1063   640           1      248     80              640              &3280 -> &3200
  1064   320           1      240     40              640              &5A80 -> &5A00
  1065   320           2      240     80              1280             &3500
  1066 
  1067 Screen Mode Selection
  1068 ---------------------
  1069 
  1070 Bits 3, 4 and 5 of address &FE*7 control the selected screen mode. For a wider
  1071 range of modes, the other bits of &FE*7 (related to sound, cassette
  1072 input/output and the Caps Lock LED) would need to be reassigned and bit 0
  1073 potentially being made available for use.
  1074 
  1075 Enhancement: Palette Definition
  1076 -------------------------------
  1077 
  1078 Since all memory accesses go via the ULA, an enhanced ULA could employ more
  1079 specific addresses than &FE*X to perform enhanced functions. For example, the
  1080 palette control is done using &FE*8-F and merely involves selecting predefined
  1081 colours, whereas an enhanced ULA could support the redefinition of all 16
  1082 colours using specific ranges such as &FE18-F (colours 0 to 7) and &FE28-F
  1083 (colours 8 to 15), where a single byte might provide 8 bits per pixel colour
  1084 specifications similar to those used on the Archimedes.
  1085 
  1086 The principal limitation here is actually the hardware: the Electron has only
  1087 a single output line for each of the red, green and blue channels, and if
  1088 those outputs are strictly digital and can only be set to a "high" and "low"
  1089 value, then only the existing eight colours are possible. If a modern ULA were
  1090 able to output analogue values (or values at well-defined points between the
  1091 high and low values, such as the half-on value supported by the Amstrad CPC
  1092 series), it would still need to be assessed whether the circuitry could
  1093 successfully handle and propagate such values. Various sources indicate that
  1094 only "TTL levels" are supported by the RGB output circuit, and since there are
  1095 74LS08 AND logic gates involved in the RGB component outputs from the ULA, it
  1096 is likely that the ULA is expected to provide only "high" or "low" values.
  1097 
  1098 Short of adding extra outputs from the ULA (either additional red, green and
  1099 blue outputs or a combined intensity output), another approach might involve
  1100 some kind of modulation where an output value might be encoded in multiple
  1101 pulses at a higher frequency than the pixel frequency. However, this would
  1102 demand additional circuitry outside the ULA, and component RGB monitors would
  1103 probably not be able to take advantage of this feature; only UHF and composite
  1104 video devices (the latter with the composite video colour support enabled on
  1105 the Electron's circuit board) would potentially benefit.
  1106 
  1107 Flashing Colours
  1108 ----------------
  1109 
  1110 According to the Advanced User Guide, "The cursor and flashing colours are
  1111 entirely generated in software: This means that all of the logical to physical
  1112 colour map must be changed to cause colours to flash." This appears to suggest
  1113 that the palette registers must be updated upon the flash counter - read and
  1114 written by OSBYTE &C1 (193) - reaching zero and that some way of changing the
  1115 colour pairs to be any combination of colours might be possible, instead of
  1116 having colour complements as pairs.
  1117 
  1118 It is conceivable that the interrupt code responsible does the simple thing
  1119 and merely inverts the current values for any logical colours (LC) for which
  1120 the associated physical colour (as supplied as the second parameter to the VDU
  1121 19 call) has the top bit of its four bit value set. These top bits are not
  1122 recorded in the palette registers but are presumably recorded separately and
  1123 used to build bitmaps as follows:
  1124 
  1125   LC  2 colour  4 colour  16 colour  4-bit value for inversion
  1126   --  --------  --------  ---------  -------------------------
  1127    0  00010001  00010001  00010001   1, 1, 1
  1128    1  01000100  00100010  00010001   4, 2, 1
  1129    2            01000100  00100010      4, 2
  1130    3            10001000  00100010      8, 2
  1131    4                      00010001         1
  1132    5                      00010001         1
  1133    6                      00100010         2
  1134    7                      00100010         2
  1135    8                      01000100         4
  1136    9                      01000100         4
  1137   10                      10001000         8
  1138   11                      10001000         8
  1139   12                      01000100         4
  1140   13                      01000100         4
  1141   14                      10001000         8
  1142   15                      10001000         8
  1143 
  1144   Inversion value calculation:
  1145 
  1146    2 colour formula: 1 << (colour * 2)
  1147    4 colour formula: 1 << colour
  1148   16 colour formula: 1 << ((colour & 2) + ((colour & 8) * 2))
  1149 
  1150 For example, where logical colour 0 has been mapped to a physical colour in
  1151 the range 8 to 15, a bitmap of 00010001 would be chosen as its contribution to
  1152 the inversion operation. (The lower three bits of the physical colour would be
  1153 used to set the underlying colour information affected by the inversion
  1154 operation.)
  1155 
  1156 An operation in the interrupt code would then combine the bitmaps for all
  1157 logical colours in 2 and 4 colour modes, with the 16 colour bitmaps being
  1158 combined for groups of logical colours as follows:
  1159 
  1160    Logical colours
  1161    ---------------
  1162    0,  2,  8, 10
  1163    4,  6, 12, 14
  1164    5,  7, 13, 15
  1165    1,  3,  9, 11
  1166 
  1167 These combined bitmaps would be EORed with the existing palette register
  1168 values in order to perform the value inversion necessary to produce the
  1169 flashing effect.
  1170 
  1171 Thus, in the VDU 19 operation, the appropriate inversion value would be
  1172 calculated for the logical colour, and this value would then be combined with
  1173 other inversion values in a dedicated memory location corresponding to the
  1174 colour's group as indicated above. Meanwhile, the palette channel values would
  1175 be derived from the lower three bits of the specified physical colour and
  1176 combined with other palette data in dedicated memory locations corresponding
  1177 to the palette registers.
  1178 
  1179 Interestingly, although flashing colours on the BBC Micro are controlled by
  1180 toggling bit 0 of the &FE20 control register location for the Video ULA, the
  1181 actual colour inversion is done in hardware.
  1182 
  1183 Enhancement: Palette Definition Lists
  1184 -------------------------------------
  1185 
  1186 It can be useful to redefine the palette in order to change the colours
  1187 available for a particular region of the screen, particularly in modes where
  1188 the choice of colours is constrained, and if an increased colour depth were
  1189 available, palette redefinition would be useful to give the illusion of more
  1190 than 16 colours in MODE 2. Traditionally, palette redefinition has been done
  1191 by using interrupt-driven timers, but a more efficient approach would involve
  1192 presenting lists of palette definitions to the ULA so that it can change the
  1193 palette at a particular display line.
  1194 
  1195 One might define a palette redefinition list in a region of memory and then
  1196 communicate its contents to the ULA by writing the address and length of the
  1197 list, along with the display line at which the palette is to be changed, to
  1198 ULA registers such that the ULA buffers the list and performs the redefinition
  1199 at the appropriate time. Throughput/bandwidth considerations might impose
  1200 restrictions on the practical length of such a list, however.
  1201 
  1202 A simple form of palette definition might be useful in text modes. Within the
  1203 blank region between lines, the foreground palette could be changed to apply
  1204 to the next line. Palette values could be read from a table in RAM, perhaps
  1205 preceding the screen data, with 24 2-byte entries providing palette
  1206 redefinition support in 2- and 4-colour modes.
  1207 
  1208 Enhancement: Display Synchronisation Interrupts
  1209 -----------------------------------------------
  1210 
  1211 When completing each scanline of the display, the ULA could trigger an
  1212 interrupt. Since this might impact system performance substantially, the
  1213 feature would probably need to be configurable, and it might be sufficient to
  1214 have an interrupt only after a certain number of display lines instead.
  1215 Permitting the CPU to take action after eight lines would allow palette
  1216 switching and other effects to occur on a character row basis.
  1217 
  1218 The ULA provides an interrupt at the end of the display period, presumably so
  1219 that software can schedule updates to the screen, avoid flickering or tearing,
  1220 and so on. However, some applications might benefit from an interrupt at, or
  1221 just before, the start of the display period so that palette modifications or
  1222 similar effects could be scheduled.
  1223 
  1224 Enhancement: Palette-Free Modes
  1225 -------------------------------
  1226 
  1227 Palette-free modes might be defined where bit values directly correspond to
  1228 the red, green and blue channels, although this would mostly make sense only
  1229 for modes with depths greater than the standard 4 bits per pixel, and such
  1230 modes would require more memory than MODE 2 if they were to have an acceptable
  1231 resolution.
  1232 
  1233 Enhancement: Display Suspend
  1234 ----------------------------
  1235 
  1236 Especially when writing to the screen memory, it could be beneficial to be
  1237 able to suspend the ULA's access to the memory, instead producing blank values
  1238 for all screen pixels until a program is ready to reveal the screen. This is
  1239 different from palette blanking since with a blank palette, the ULA is still
  1240 reading screen memory and translating its contents into pixel values that end
  1241 up being blank.
  1242 
  1243 This function is reminiscent of a capability of the ZX81, albeit necessary on
  1244 that hardware to reduce the load on the system CPU which was responsible for
  1245 producing the video output. By allowing display suspend on the Electron, the
  1246 performance benefit would be derived from giving the CPU full access to the
  1247 memory bandwidth.
  1248 
  1249 Note that since the CPU is only able to access RAM at 1MHz, there is no
  1250 possibility to improve performance beyond that achieved in MODE 4, 5 or 6
  1251 normally. However, if faster RAM access were to be made possible (see the
  1252 discussion of 8-bit wide RAM access), the CPU could benefit from freeing up
  1253 the ULA's access slots entirely.
  1254 
  1255 The region blanking feature mentioned above could be implemented using this
  1256 enhancement instead of employing palette blanking for the affected lines of
  1257 the display.
  1258 
  1259 Enhancement: Memory Filling
  1260 ---------------------------
  1261 
  1262 A capability that could be given to an enhanced ULA is that of permitting the
  1263 ULA to write to screen memory as well being able to read from it. Although
  1264 such a capability would probably not be useful in conjunction with the
  1265 existing read operations when producing a screen display, and insufficient
  1266 bandwidth would exist to do so in high-bandwidth screen modes anyway, the
  1267 capability could be offered during a display suspend period (as described
  1268 above), permitting a more efficient mechanism to rapidly fill memory with a
  1269 predetermined value.
  1270 
  1271 This capability could also support block filling, where the limits of the
  1272 filled memory would be defined by the position and size of a screen area,
  1273 although this would demand the provision of additional registers in the ULA to
  1274 retain the details of such areas and additional logic to control the fill
  1275 operation.
  1276 
  1277 Enhancement: Region Filling
  1278 ---------------------------
  1279 
  1280 An alternative to memory writing might involve indicating regions using
  1281 additional registers or memory where the ULA fills regions of the screen with
  1282 content instead of reading from memory. Unlike hardware sprites which should
  1283 realistically provide varied content, region filling could employ single
  1284 colours or patterns, and one advantage of doing so would be that the ULA need
  1285 not access memory at all within a particular region.
  1286 
  1287 Regions would be defined on a row-by-row basis. Instead of reading memory and
  1288 blitting a direct representation to the screen, the ULA would read region
  1289 definitions containing a start column, region width and colour details. There
  1290 might be a certain number of definitions allowed per row, or the ULA might
  1291 just traverse an ordered list of such definitions with each one indicating the
  1292 row, start column, region width and colour details.
  1293 
  1294 One could even compress this information further by requiring only the row,
  1295 start column and colour details with each subsequent definition terminating
  1296 the effect of the previous one. However, one would also need to consider the
  1297 convenience of preparing such definitions and whether efficient access to
  1298 definitions for a particular row might be desirable. It might also be
  1299 desirable to avoid having to prepare definitions for "empty" areas of the
  1300 screen, effectively making the definition of the screen contents employ
  1301 run-length encoding and employ only colour plus length information.
  1302 
  1303 One application of region filling is that of simple 2D and 3D shape rendering.
  1304 Although it is entirely possible to plot such shapes to the screen and have
  1305 the ULA blit the memory contents to the screen, such operations consume
  1306 bandwidth both in the initial plotting and in the final transfer to the
  1307 screen. Region filling would reduce such bandwidth usage substantially.
  1308 
  1309 This way of representing screen images would make certain kinds of images
  1310 unfeasible to represent - consider alternating single pixel values which could
  1311 easily occur in some character bitmaps - even if an internal queue of regions
  1312 were to be supported such that the ULA could read ahead and buffer such
  1313 "bandwidth intensive" areas. Thus, the ULA might be better served providing
  1314 this feature for certain areas of the display only as some kind of special
  1315 graphics window.
  1316 
  1317 Enhancement: Hardware Sprites
  1318 -----------------------------
  1319 
  1320 An enhanced ULA might provide hardware sprites, but this would be done in an
  1321 way that is incompatible with the standard ULA, since no &FE*X locations are
  1322 available for allocation. To keep the facility simple, hardware sprites would
  1323 have a standard byte width and height.
  1324 
  1325 The specification of sprites could involve the reservation of 16 locations
  1326 (for example, &FE20-F) specifying a fixed number of eight sprites, with each
  1327 location pair referring to the sprite data. By limiting the ULA to dealing
  1328 with a fixed number of sprites, the work required inside the ULA would be
  1329 reduced since it would avoid having to deal with arbitrary numbers of sprites.
  1330 
  1331 The principal limitation on providing hardware sprites is that of having to
  1332 obtain sprite data, given that the ULA is usually required to retrieve screen
  1333 data, and given the lack of memory bandwidth available to retrieve sprite data
  1334 (particularly from multiple sprites supposedly at the same position) and
  1335 screen data simultaneously. Although the ULA could potentially read sprite
  1336 data and screen data in alternate memory accesses in screen modes where the
  1337 bandwidth is not already fully utilised, this would result in a degradation of
  1338 performance.
  1339 
  1340 Enhancement: Additional Screen Mode Configurations
  1341 --------------------------------------------------
  1342 
  1343 Alternative screen mode configurations could be supported. The ULA has to
  1344 produce 640 pixel values across the screen, with pixel doubling or quadrupling
  1345 employed to fill the screen width:
  1346 
  1347   Screen width      Columns     Scaling     Depth       Bytes
  1348   ------------      -------     -------     -----       -----
  1349   640               80          x1          1           80
  1350   320               40          x2          1, 2        40, 80
  1351   160               20          x4          2, 4        40, 80
  1352 
  1353 It must also use at most 80 byte-sized memory accesses to provide the
  1354 information for the display. Given that characters must occupy an 8x8 pixel
  1355 array, if a configuration featuring anything other than 20, 40 or 80 character
  1356 columns is to be supported, compromises must be made such as the introduction
  1357 of blank pixels either between characters (such as occurs between rows in MODE
  1358 3 and 6) or at the end of a scanline (such as occurs at the end of the frame
  1359 in MODE 3 and 6). Consider the following configuration:
  1360 
  1361   Screen width      Columns     Scaling     Depth       Bytes       Blank
  1362   ------------      -------     -------     -----       ------      -----
  1363   208               26          x3          1, 2        26, 52      16
  1364 
  1365 Here, if the ULA can triple pixels, a 26 column mode with either 2 or 4
  1366 colours could be provided, with 16 blank pixel values (out of a total of 640)
  1367 generated either at the start or end (or split between the start and end) of
  1368 each scanline.
  1369 
  1370 Enhancement: Character Attributes
  1371 ---------------------------------
  1372 
  1373 The BBC Micro MODE 7 employs something resembling character attributes to
  1374 support teletext displays, but depends on circuitry providing a character
  1375 generator. The ZX Spectrum, on the other hand, provides character attributes
  1376 as a means of colouring bitmapped graphics. Although such a feature is very
  1377 limiting as the sole means of providing multicolour graphics, in situations
  1378 where the choice is between low resolution multicolour graphics or high
  1379 resolution monochrome graphics, character attributes provide a potentially
  1380 useful compromise.
  1381 
  1382 For each byte read, the ULA must deliver 8 pixel values (out of a total of
  1383 640) to the video output, doing so by either emptying its pixel buffer on a
  1384 pixel per cycle basis, or by multiplying pixels and thus holding them for more
  1385 than one cycle. For example for a screen mode having 640 pixels in width:
  1386 
  1387   Cycle:    0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15
  1388   Reads:    B                               B
  1389   Pixels:   0   1   2   3   4   5   6   7   0   1   2   3   4   5   6   7
  1390 
  1391 And for a screen mode having 320 pixels in width:
  1392 
  1393   Cycle:    0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15
  1394   Reads:    B
  1395   Pixels:   0   0   1   1   2   2   3   3   4   4   5   5   6   6   7   7
  1396 
  1397 However, in modes where less than 80 bytes are required to generate the pixel
  1398 values, an enhanced ULA might be able to read additional bytes between those
  1399 providing the bitmapped graphics data:
  1400 
  1401   Cycle:    0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15
  1402   Reads:    B                               A
  1403   Pixels:   0   0   1   1   2   2   3   3   4   4   5   5   6   6   7   7
  1404 
  1405 These additional bytes could provide colour information for the bitmapped data
  1406 in the following character column (of 8 pixels). Since it would be desirable
  1407 to apply attribute data to the first column, the initial 8 cycles might be
  1408 configured to not produce pixel values.
  1409 
  1410 For an entire character, attribute data need only be read for the first row of
  1411 pixels for a character. The subsequent rows would have attribute information
  1412 applied to them, although this would require the attribute data to be stored
  1413 in some kind of buffer. Thus, the following access pattern would be observed:
  1414 
  1415   Reads:    A B _ B _ B _ B _ B _ B _ B _ B ...
  1416 
  1417 In modes 3 and 6, the blank display lines could be used to retrieve attribute
  1418 data:
  1419 
  1420   Reads (blank):     A _ A _ A _ A _ A _ A _ A _ A _ ...
  1421   Reads (active):    B _ B _ B _ B _ B _ B _ B _ B _ ...
  1422   Reads (active):    B _ B _ B _ B _ B _ B _ B _ B _ ...
  1423                      ...
  1424 
  1425 See below for a discussion of using this for character data as well.
  1426 
  1427 A whole byte used for colour information for a whole character would result in
  1428 a choice of 256 colours, and this might be somewhat excessive. By only reading
  1429 attribute bytes at every other opportunity, a choice of 16 colours could be
  1430 applied individually to two characters.
  1431 
  1432   Cycle:    0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
  1433   Reads:    B               A               B               -
  1434   Pixels:   0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
  1435 
  1436 Further reductions in attribute data access, offering 4 colours for every
  1437 character in a four character block, for example, might also be worth
  1438 considering.
  1439 
  1440 Consider the following configurations for screen modes with a colour depth of
  1441 1 bit per pixel for bitmap information:
  1442 
  1443   Screen width  Columns  Scaling  Bytes (B)  Bytes (A)  Colours  Screen start
  1444   ------------  -------  -------  ---------  ---------  -------  ------------
  1445   320           40       x2       40         40         256      &5300
  1446   320           40       x2       40         20         16       &5580 -> &5500
  1447   320           40       x2       40         10         4        &56C0 -> &5600
  1448   208           26       x3       26         26         256      &62C0 -> &6200
  1449   208           26       x3       26         13         16       &6460 -> &6400
  1450 
  1451 Enhancement: Text-Only Modes using Character and Attribute Data
  1452 ---------------------------------------------------------------
  1453 
  1454 In modes 3 and 6, the blank display lines could be used to retrieve character
  1455 and attribute data instead of trying to insert it between bitmap data accesses,
  1456 but this data would then need to be retained:
  1457 
  1458   Reads:    A C A C A C A C A C A C A C A C ...
  1459   Reads:    B _ B _ B _ B _ B _ B _ B _ B _ ...
  1460 
  1461 Only attribute (A) and character (C) reads would require screen memory
  1462 storage. Bitmap data reads (B) would involve either accesses to memory to
  1463 obtain character definition details or could, at the cost of special storage
  1464 in the ULA, involve accesses within the ULA that would then free up the RAM.
  1465 However, the CPU would not benefit from having any extra access slots due to
  1466 the limitations of the RAM access mechanism.
  1467 
  1468 A scheme without caching might be possible. The same line of memory addresses
  1469 might be visited over and over again for eight display lines, with an index
  1470 into the bitmap data being incremented from zero to seven. The access patterns
  1471 would look like this:
  1472 
  1473   Reads:    C B C B C B C B C B C B C B C B ... (generate data from index 0)
  1474   Reads:    C B C B C B C B C B C B C B C B ... (generate data from index 1)
  1475   Reads:    C B C B C B C B C B C B C B C B ... (generate data from index 2)
  1476   Reads:    C B C B C B C B C B C B C B C B ... (generate data from index 3)
  1477   Reads:    C B C B C B C B C B C B C B C B ... (generate data from index 4)
  1478   Reads:    C B C B C B C B C B C B C B C B ... (generate data from index 5)
  1479   Reads:    C B C B C B C B C B C B C B C B ... (generate data from index 6)
  1480   Reads:    C B C B C B C B C B C B C B C B ... (generate data from index 7)
  1481 
  1482 The bandwidth requirements would be the sum of the accesses to read the
  1483 character values (repeatedly) and those to read the bitmap data to reproduce
  1484 the characters on screen.
  1485 
  1486 Enhancement: 40-Column Text Modes by Interleaving Screen and Bitmap Accesses
  1487 ----------------------------------------------------------------------------
  1488 
  1489 A simplified form of the above interleaved character/bitmap reading scheme.
  1490 This was also suggested in a discussion here:
  1491 
  1492 https://stardot.org.uk/forums/viewtopic.php?p=393243#p393243
  1493 
  1494 The ULA could be run in high-bandwidth mode to fetch character codes from
  1495 screen memory in one cycle and then to use the character code to look up a
  1496 pixel row of a character bitmap, reading that bitmap slice in the following
  1497 cycle. The bitmap would be converted to pixel values that would then be
  1498 emitted over the subsequent two cycles concurrently with the preparation of
  1499 the next character's pixels.
  1500 
  1501   2MHz cycle: 0 1 2 3 4 5 ...
  1502   Reads:      C B C B C B ...
  1503   Pixels:         a   b   ...
  1504 
  1505 The memory access to bitmap data would be computed as follows, assuming the
  1506 normal eight pixel height and single-byte encoding of character bitmaps:
  1507 
  1508   bitmap address = bitmap table base + (character code * 8) + index
  1509 
  1510 Each successive pixel row on the screen would expose the appropriate row in
  1511 the character bitmap, with this index looping from 0 to 7 repeatedly as shown
  1512 previously. Spacing between character lines could be introduced as already
  1513 done in MODE 6.
  1514 
  1515 Character bitmap data would be stored in RAM, since this is the only possible
  1516 source of data for the ULA as delivered. The use of ROM would require changes
  1517 to the broader system architecture. Thus, the total memory requirements of
  1518 such a mode would be the locations for character positions plus the storage
  1519 requirements of the bitmaps to be supported.
  1520 
  1521   Columns  Rows  Screen size  Bitmaps  Bitmaps size  Total size
  1522   -------  ----  -----------  -------  ------------  ----------
  1523   40       25    1000         256      2048          3048
  1524   40       25    1000         128      1024          2024
  1525   40       25    1000         96       768           1768
  1526   40       32    1280         256      2048          3328
  1527   40       32    1280         128      1024          2304
  1528   40       32    1280         96       768           2048
  1529 
  1530 The simplest arrangement would involve bitmap definitions for all 256 possible
  1531 character codes, demanding a total of around 3K of RAM. Reducing the number of
  1532 supported bitmaps to 96 (codes 32 to 127 inclusive) would bring this total to
  1533 a maximum of 2K, but this would incur additional complexity in the ULA itself
  1534 if the codes not corresponding to bitmaps were to be specially mapped to, say,
  1535 the bitmap for the space character or to a null character.
  1536 
  1537 With the screen start address controllable, it is conceivable that with a
  1538 256-entry bitmap table, the screen memory could be made to overlap the bitmap
  1539 table for bitmaps not likely to be used. For example, the bitmap table might
  1540 be situated at &7700, with this leaving enough space for 128 entries (&400 or
  1541 1024 bytes) and a 40x32 text screen (&500 or 1280 bytes):
  1542 
  1543   &8000 +---------------+---------------+
  1544   &7F00 +---------------+               |
  1545         |               |    Display    |
  1546         | Bitmaps (128) |    (40x32)    |
  1547         |               |               |
  1548   &7B00 +---------------+---------------+
  1549         |               |
  1550         | Bitmaps (128) |
  1551         |               |
  1552   &7700 +---------------+
  1553 
  1554 Care would then need to be taken to avoid the use of codes from 128 to 255 in
  1555 the screen memory as these would replicate character data as bitmap data.
  1556 
  1557 Enhancement: MODE 7 Emulation using Character Attributes
  1558 --------------------------------------------------------
  1559 
  1560 If the scheme of applying attributes to character regions were employed to
  1561 emulate MODE 7, in conjunction with the MODE 6 display technique, the
  1562 following configuration would be required:
  1563 
  1564   Screen width  Columns  Rows  Bytes (B)  Bytes (A)  Colours  Screen start
  1565   ------------  -------  ----  ---------  ---------  -------  ------------
  1566   320           40       25    40         20         16       &5ECC -> &5E00
  1567   320           40       25    40         10         4        &5FC6 -> &5F00
  1568 
  1569 Although this requires much more memory than MODE 7 (8500 bytes versus MODE
  1570 7's 1000 bytes), it does not need much more memory than MODE 6, and it would
  1571 at least make a limited 40-column multicolour mode available as a substitute
  1572 for MODE 7.
  1573 
  1574 Using the text-only enhancement with caching of data or with repeated reads of
  1575 the same character data line for eight display lines, the storage requirements
  1576 would be diminished substantially:
  1577 
  1578   Screen width  Columns  Rows  Bytes (C)  Bytes (A)  Colours  Screen start
  1579   ------------  -------  ----  ---------  ---------  -------  ------------
  1580   320           40       25    40         20         16       &7A94 -> &7A00
  1581   320           40       25    40         10         4        &7B1E -> &7B00
  1582   320           40       25    40         5          2        &7B9B -> &7B00
  1583   320           40       25    40         0          (2)      &7C18 -> &7C00
  1584   640           80       25    80         40         16       &7448 -> &7400
  1585   640           80       25    80         20         4        &763C -> &7600
  1586   640           80       25    80         10         2        &7736 -> &7700
  1587   640           80       25    80         0          (2)      &7830 -> &7800
  1588 
  1589 Note that the colours describe the locally defined attributes for each
  1590 character. When no attribute information is provided, the colours are defined
  1591 globally.
  1592 
  1593 Enhancement: Character Generator Support and Vertical Scaling
  1594 -------------------------------------------------------------
  1595 
  1596 When generating a picture, the ULA traverses screen memory, obtaining 40 or 80
  1597 bytes of pixel data for each scanline. It then proceeds to the next row of
  1598 pixel data for each successive scanline, with the exception of the text modes
  1599 where scanlines may be blank (for which the row address does not advance).
  1600 This arrangement provides a conventional bitmapped graphics display.
  1601 
  1602 However, the ULA could instead facilitate the use of character generators. The
  1603 principles involved can be demonstrated by the Jafa Mode 7 Mark 2 Display Unit
  1604 expansion for the Electron which feeds the pixel data from a MODE 4 screen to
  1605 a SAA5050 character generator to create a MODE 7 display. The solution adopted
  1606 involves the replication of 40 bytes of character data across as many pixel
  1607 rows as is necessary for the character generator to receive the appropriate
  1608 character data for all scanlines in any given character row. If only a single
  1609 40-byte row of character data were to be present for the first scanline of a
  1610 character row, the character generator would only produce the first scanline
  1611 (or the uppermost pixels of the characters) correctly, with the rest of the
  1612 character shapes being ill-defined.
  1613 
  1614 Here, the ULA could facilitate the use of memory-efficient character mode
  1615 representations (such as MODE 7) by holding the row address for a number of
  1616 scanlines, thus providing the same row of screen data for those scanlines,
  1617 then advancing to the next row. Visualised in terms of pixel data, it would be
  1618 like providing a display with a very low vertical resolution. Indeed, being
  1619 able to reduce the vertical resolution of a display mode by a factor of eight
  1620 or ten would be equivalent to the above character generation technique in
  1621 terms of the ULA's screen reading activities.
  1622 
  1623 By combining this vertical scaling or scanline replication with a circuit
  1624 switchable between bitmapped graphics output and character graphics output,
  1625 MODE 7 support could be made available, potentially as a hardware option
  1626 separate from the ULA.
  1627 
  1628 Enhancement: Compressed Character Data
  1629 --------------------------------------
  1630 
  1631 Another observation about text-only modes is that they only need to store a
  1632 restricted set of bitmapped data values. Encoding this set of values in a
  1633 smaller unit of storage than a byte could possibly help to reduce the amount
  1634 of storage and bandwidth required to reproduce the characters on the display.
  1635 
  1636 Enhancement: High Resolution Graphics and Larger Colour Depths
  1637 --------------------------------------------------------------
  1638 
  1639 Screen modes with higher resolutions and larger colour depths might be
  1640 possible, but this would in most cases involve the allocation of more screen
  1641 memory, and the ULA would probably then be obliged to page in such memory for
  1642 the CPU to be able to sensibly access it all. Higher resolutions would also
  1643 involve a faster pixel clock.
  1644 
  1645 However, we may consider a doubled colour depth and the need for higher
  1646 bandwidth transfers by a ULA having an 8-bit data bus to access the RAM,
  1647 utilising two "page mode" transfers per 2MHz cycle. If such transfers were to
  1648 access consecutive bytes in the same memory region (for example, bytes &3000
  1649 and &3001) this would require a change to the arrangement of screen memory,
  1650 also incurring changes to the memory map for larger modes:
  1651 
  1652  (&3000 &3001) (&3010 &3011) ...
  1653  (&3002 &3003) (&3012 &3013)
  1654  ...           ...
  1655  (&300E &300F) (&301E &301F)
  1656 
  1657 If such transfers were to access two adjacent columns of bytes (for example,
  1658 bytes &3000 and &3008), this would still require a change in the step size
  1659 across the screen memory, also incur memory map changes for larger modes, and
  1660 the method for programs to update the screen would be more complicated:
  1661 
  1662  (&3000 &3008) (&3010 &3018) ...
  1663  (&3001 &3009) (&3011 &3019)
  1664  ...           ...
  1665  (&3007 &300F) (&3017 &301F)
  1666 
  1667 However, such transfers could instead map the device address bit that is
  1668 toggled between transfers to the most significant system memory address bit.
  1669 Thus, bits in adjacent locations within each RAM device would actually reside
  1670 in different memory regions:
  1671 
  1672  (&3000 &B000) (&3008 &B008) ...
  1673  (&3001 &B001) (&3009 &B009)
  1674  ...           ...
  1675  (&3007 &B007) (&300F &B00F)
  1676 
  1677 Since &B000 can also be considered as &3000 combined with &8000, this
  1678 introducing the asserted uppermost bit, address &B000 can be considered as
  1679 &3000 in an upper memory bank.
  1680 
  1681 Other mechanisms might be employed to allow programs to access the uppermost
  1682 bank, but the ULA would be able to access it trivially and unconditionally.
  1683 
  1684 Enhancement: Assembling a Display from Separate Display Planes
  1685 --------------------------------------------------------------
  1686 
  1687 Continuing from the use of separate memory regions for higher bandwidth modes,
  1688 one can consider a memory layout where modes 1 and 2 would employ two regions
  1689 that individually resemble modes 4 and 5 respectively. Programs would be able
  1690 to populate two copies of the screen memory for a low-bandwidth mode in order
  1691 to produce a single screen memory region for the corresponding high-bandwidth
  1692 mode. This would allow a seamless transition between displays with different
  1693 numbers of colours without needing to redraw the display.
  1694 
  1695 Enhancement: Genlock Support
  1696 ----------------------------
  1697 
  1698 The ULA generates a video signal in conjunction with circuitry producing the
  1699 output features necessary for the correct display of the screen image.
  1700 However, it appears that the ULA drives the video synchronisation mechanism
  1701 instead of reacting to an existing signal. Genlock support might be possible
  1702 if the ULA were made to be responsive to such external signals, resetting its
  1703 address generators upon receiving synchronisation events.
  1704 
  1705 Enhancement: Improved Sound
  1706 ---------------------------
  1707 
  1708 The standard ULA reserves &FE*6 for sound generation and cassette input/output
  1709 (with bits 1 and 2 of &FE*7 being used to select either sound generation or
  1710 cassette I/O), thus making it impossible to support multiple channels within
  1711 the given framework. The BBC Micro ULA employs &FE40-&FE4F for sound control,
  1712 and an enhanced ULA could adopt this interface.
  1713 
  1714 The BBC Micro uses the SN76489 chip to produce sound, and the entire
  1715 functionality of this chip could be emulated for enhanced sound, with a subset
  1716 of the functionality exposed via the &FE*6 interface.
  1717 
  1718 See: http://en.wikipedia.org/wiki/Texas_Instruments_SN76489
  1719 See: http://www.smspower.org/Development/SN76489
  1720 
  1721 Enhancement: Waveform Upload
  1722 ----------------------------
  1723 
  1724 As with a hardware sprite function, waveforms could be uploaded or referenced
  1725 using locations as registers referencing memory regions.
  1726 
  1727 Enhancement: Sound Input/Output
  1728 -------------------------------
  1729 
  1730 Since the ULA already controls audio input/output for cassette-based data, it
  1731 would have been interesting to entertain the idea of sampling and output of
  1732 sounds through the cassette interface. However, a significant amount of
  1733 circuitry is employed to process the input signal for use by the ULA and to
  1734 process the output signal for recording.
  1735 
  1736 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw_03.htm#3.11
  1737 
  1738 Enhancement: BBC ULA Compatibility
  1739 ----------------------------------
  1740 
  1741 Although some new ULA functions could be defined in a way that is also
  1742 compatible with the BBC Micro, the BBC ULA is itself incompatible with the
  1743 Electron ULA: &FE00-7 is reserved for the video controller in the BBC memory
  1744 map, but controls various functions specific to the 6845 video controller;
  1745 &FE08-F is reserved for the serial controller. It therefore becomes possible
  1746 to disregard compatibility where compatibility is already disregarded for a
  1747 particular area of functionality.
  1748 
  1749 &FE20-F maps to video ULA functionality on the BBC Micro which provides
  1750 control over the palette (using address &FE21, compared to &FE07-F on the
  1751 Electron) and other system-specific functions. Since the location usage is
  1752 generally incompatible, this region could be reused for other purposes.
  1753 
  1754 Enhancement: Increased RAM, ULA and CPU Performance
  1755 ---------------------------------------------------
  1756 
  1757 More modern implementations of the hardware might feature faster RAM coupled
  1758 with an increased ULA clock frequency in order to increase the bandwidth
  1759 available to the ULA and to the CPU in situations where the ULA is not needed
  1760 to perform work. A ULA employing a 32MHz clock would be able to complete the
  1761 retrieval of a byte from RAM in only 250ns and thus be able to enable the CPU
  1762 to access the RAM for the following 250ns even in display modes requiring the
  1763 retrieval of a byte for the display every 500ns. The CPU could, subject to
  1764 timing issues, run at 2MHz even in MODE 0, 1 and 2.
  1765 
  1766 A scheme such as that described above would have a similar effect to the
  1767 scheme employed in the BBC Micro, although the latter made use of RAM with a
  1768 wider bandwidth in order to complete memory transfers within 250ns and thus
  1769 permit the CPU to run continuously at 2MHz.
  1770 
  1771 Higher bandwidth could potentially be used to implement exotic features such
  1772 as RAM-resident hardware sprites or indeed any feature demanding RAM access
  1773 concurrent with the production of the display image.
  1774 
  1775 Enhancement: Multiple CPU Stacks and Zero Pages
  1776 -----------------------------------------------
  1777 
  1778 The 6502 maintains a stack for subroutine calls and register storage in page
  1779 &01. Although the stack register can be manipulated using the TSX and TXS
  1780 instructions, thereby permitting the maintenance of multiple stack regions and
  1781 thus the potential coexistence of multiple programs each using a separate
  1782 region, only programs that make little use of the stack (perhaps avoiding
  1783 deeply-nested subroutine invocations and significant register storage) would
  1784 be able to coexist without overwriting each other's stacks.
  1785 
  1786 One way that this issue could be alleviated would involve the provision of a
  1787 facility to redirect accesses to page &01 to other areas of memory. The ULA
  1788 would provide a register that defines a physical page for the use of the CPU's
  1789 "logical" page &01, and upon any access to page &01 by the CPU, the ULA would
  1790 change the asserted address lines to redirect the access to the appropriate
  1791 physical region.
  1792 
  1793 By providing an 8-bit register, mapping to the most significant byte (MSB) of
  1794 a 16-bit address, the ULA could then replace any MSB equal to &01 with the
  1795 register value before the access is made. Where multiple programs coexist,
  1796 upon switching programs, the register would be updated to point the ULA to the
  1797 appropriate stack location, thus providing a simple memory management unit
  1798 (MMU) capability.
  1799 
  1800 In a similar fashion, zero page accesses could also be redirected so that code
  1801 could run from sideways RAM and have zero page operations redirected to "upper
  1802 memory" - for example, to page &BE (with stack accesses redirected to page
  1803 &BF, perhaps) - thereby permitting most CPU operations to occur without
  1804 inadvertent accesses to "lower memory" (the RAM) which would risk stalling the
  1805 CPU as it contends with the ULA for memory access.
  1806 
  1807 Such facilities could also be provided by a separate circuit between the CPU
  1808 and ULA in a fashion similar to that employed by a "turbo" board, but unlike
  1809 such boards, no additional RAM would be provided: all memory accesses would
  1810 occur as normal through the ULA, albeit redirected when configured
  1811 appropriately.
  1812 
  1813 ULA Pin Functions
  1814 -----------------
  1815 
  1816 The functions of the ULA pins are described in the Electron Service Manual. Of
  1817 interest to video processing are the following:
  1818 
  1819   CSYNC (low during horizontal or vertical synchronisation periods, high
  1820          otherwise)
  1821 
  1822   HS (low during horizontal synchronisation periods, high otherwise)
  1823 
  1824   RED, GREEN, BLUE (pixel colour outputs)
  1825 
  1826   CLOCK IN (a 16MHz clock input, 4V peak to peak)
  1827 
  1828   PHI OUT (a 1MHz, 2MHz and stopped clock signal for the CPU)
  1829 
  1830 More general memory access pins:
  1831 
  1832   RAM0...RAM3 (data lines to/from the RAM)
  1833 
  1834   RA0...RA7 (address lines for sending both row and column addresses to the RAM)
  1835 
  1836   RAS (row address strobe setting the row address on a negative edge - see the
  1837        timing notes)
  1838 
  1839   CAS (column address strobe setting the column address on a negative edge -
  1840        see the timing notes)
  1841 
  1842   WE (sets write enable with logic 0, read with logic 1)
  1843 
  1844   ROM (select data access from ROM)
  1845 
  1846 CPU-oriented memory access pins:
  1847 
  1848   A0...A15 (CPU address lines)
  1849 
  1850   PD0...PD7 (CPU data lines)
  1851 
  1852   R/W (indicates CPU write with logic 0, CPU read with logic 1)
  1853 
  1854 Interrupt-related pins:
  1855 
  1856   NMI (CPU request for uninterrupted 1MHz access to memory)
  1857 
  1858   IRQ (signal event to CPU)
  1859 
  1860   POR (power-on reset, resetting the ULA on a positive edge and asserting the
  1861        CPU's RST pin)
  1862 
  1863   RST (master reset for the CPU signalled on power-up and by the Break key)
  1864 
  1865 Keyboard-related pins:
  1866 
  1867   KBD0...KBD3 (keyboard inputs)
  1868 
  1869   CAPS LOCK (control status LED)
  1870 
  1871 Sound-related pins:
  1872 
  1873   SOUND O/P (sound output using internal oscillator)
  1874 
  1875 Cassette-related pins:
  1876 
  1877   CAS IN (cassette circuit input, between 0.5V to 2V peak to peak)
  1878 
  1879   CAS OUT (pseudo-sinusoidal output, 1.8V peak to peak)
  1880 
  1881   CAS RC (detect high tone)
  1882 
  1883   CAS MO (motor relay output)
  1884 
  1885   ÷13 IN (~1200 baud clock input)
  1886 
  1887 ULA Socket
  1888 ----------
  1889 
  1890 The socket used for the ULA is a 3M/TexTool 268-5400 68-pin socket.
  1891 
  1892 References
  1893 ----------
  1894 
  1895 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw.htm
  1896 
  1897 About this Document
  1898 -------------------
  1899 
  1900 The most recent version of this document and accompanying distribution should
  1901 be available from the following location:
  1902 
  1903 http://hgweb.boddie.org.uk/ULA
  1904 
  1905 Copyright and licence information can be found in the docs directory of this
  1906 distribution - see docs/COPYING.txt for more information.