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Added notes about RAM access limitations preventing 2MHz RAM access by the CPU. |
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Removed the width instance attribute. |
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Moved address preparation onto negative edges and data acquisition onto positive |
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Shifted the timing states so that cycle 0 is aligned with the positive edge of |
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Refined and expanded the RAM access timings, moving data transfers to the |
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Renamed address to pixel_address. |
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Added initial CPU abstraction support together with read/write selection and |
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Made the next_vertical control-flow more hierarchical. |
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Introduced positive and negative signal transition update methods in order to |
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Tidied, introducing a write_pixels function, removing PIXEL_POSITIONS. |
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Fixed and tidied up pixel production, employing the general state counter for |
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Fixed the timing of pixel data decoding. Made the pixel data a plain integer. |
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Initialise the palette as red/green/blue triples. |
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Replaced the pixel buffer with translated byte data and a function converting |
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Changed the processing of pixel data and added remarks about pixel layout. |
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Replaced row spacing variables with row height and row offset variables. |
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Renamed reset methods and tidied slightly. |
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Separated address updating from the NMI-dependent RAM access condition. |
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Use the horizontal position counter by itself to manage the pixel buffer. |
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Refined video timings according to measurements and a review of the documents. |
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Introduced a pixel position counter, eliminating the horizontal position counter |
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Separated out the screen layout section and described a column-oriented layout. |
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Updated Amstrad CPC-related notes concerning extra colour information. |
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Added a note about redirecting zero page accesses as well as stack accesses. |
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Added a textual MODE 1 enhancement plus remarks about display interrupts. |
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Added 625-line, 312/313 scanline notes. |
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Added a note about the 2MHz RAM access enhancement. |
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Added RAM access corrections related to CPU activity plus bandwidth figures. |
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Added multiple CPU stack "MMU" enhancement. |
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Added region blanking and display suspend notes. |
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Added ByteDelight.com 4164 chips source. |
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Added notes about sideways RAM/ROM access, flashing colours, and the ULA socket. |
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Added copyright and licensing information. |
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Added Amstrad CPC-related note. |
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Added notes about cartridges, Econet, and region filling. |
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Merged general changes. |
shedskin |
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Added an explicit branch to track Shedskin-specific changes. |
shedskin |
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Introduced a shift register abstraction for the ULA's internal state. |
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Added Unicorn Electronics references for RAM and CPU chips. |
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Added more RAM timing details and compared different ICs. |
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Added a note about a possible memory filling capability. |
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Added notes about a display suspend capability. |
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Merged general changes. |
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Added some clarifications about the implementation of an expanded palette. |
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Added initial support for CPU address and data propagation. |
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Added a note about a mechanism to allow more flexible colour output, marking the |
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Improved the assessment of various RAM ICs, adding other product details. |
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Added information on the RAM ICs and modern replacement parts. |
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Added enhancement clarifications to various headings along with a |
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Added more details about how palette data would be inverted in order to cause |
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Described how the inversion bitmap would be used to update each flashing colour. |
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Fixed the description of flashing colours since all logical colours can be made |
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Added a note about flashing colours. |
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Modelled the state of the ULA with a collection of latches instead of a counter. |
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Added a note about increased component performance and bandwidth consequences. |
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Updated the interpretation of how the RAM ICs are accessed by the ULA. |
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Added display circuitry note. |
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Added video, audio and general notes. |
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Minor type-related change discovered through Shedskin compilation. |
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Merged general changes. |
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