# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1328224888 -3600
# Node ID 007ccb845f7e64b5bfba56db59b8f305e10f27fb
# Parent  d3cc0494f825319d9285062e52581bb83b6c483f
Improved the timing notes, adding information about the memory access mechanism
and a note about supporting shadow/extended memory.

diff -r d3cc0494f825 -r 007ccb845f7e ULA.txt
--- a/ULA.txt	Sun Jan 29 21:50:13 2012 +0100
+++ b/ULA.txt	Fri Feb 03 00:21:28 2012 +0100
@@ -3,10 +3,10 @@
 
 According to the above (15.3.2 in the AUG), there are 312 scanlines, 256 of
 which are used to generate pixel data. At 50Hz, this means that 128 cycles are
-used to produce pixel data (2000000 / 50 = 40000; 40000 / 312 ~= 128). This is
-consistent with the observation that each scanline requires at most 80 bytes
-of data, and that the ULA is apparently busy for 40 out of 64 microseconds in
-each scanline.
+used to produce pixel data (2000000 cycles / 50 = 40000 cycles; 40000 cycles /
+312 ~= 128 cycles). This is consistent with the observation that each scanline
+requires at most 80 bytes of data, and that the ULA is apparently busy for 40
+out of 64 microseconds in each scanline.
 
 See: Acorn Electron Advanced User Guide
 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
@@ -20,6 +20,40 @@
 frequency is divided by the ULA (IC1) depending on the screen mode in use.
 
 See: Acorn Electron Service Manual
+     http://acorn.chriswhy.co.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf
+
+Each 16MHz cycle is approximately 62.5ns. To access the memory, the following
+patterns corresponding to 16MHz cycles are required:
+
+     Time (ns):  0-------------- 500------------
+   2 MHz cycle:  0               1               ...
+  16 MHz cycle:  0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
+          ~RAS:  0           1   0           1   ...
+          ~CAS:    0   1 0   1     0   1 0   1   ...
+                             A         B
+                                   F     S
+
+Here, "A" indicates the row and column addresses being latched into the RAM
+(on a negative edge for RAS and CAS respectively), and "B" indicates the
+second column address being latched into the RAM. Presumably, the first and
+second half-bytes can be read at "F" and "S" respectively.
+
+Shadow/Expanded Memory
+----------------------
+
+The Electron exposes all sixteen address lines and all eight data lines
+through the expansion bus. Using such lines, it is possible to provide
+additional memory - typically sideways ROM and RAM - on expansion cards and
+through cartridges, although the official cartridge specification provides
+fewer address lines and only seeks to provide access to memory in 16K units.
+
+Various modifications and upgrades were developed to offer "turbo"
+capabilities to the Electron, permitting the CPU to access a separate 8K of
+RAM at 2MHz, presumably preventing access to the low 8K of RAM accessible via
+the ULA through additional logic. However, an enhanced ULA might support
+independent CPU access to memory over the expansion bus by allowing itself to
+be discharged from providing access to memory, potentially for a range of
+addresses, and for the CPU to communicate with external memory uninterrupted.
 
 Hardware Scrolling
 ------------------