# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1640959971 -3600
# Node ID 0e1245115d28446b22a31327ed8b5050450b0aee
# Parent  af46c81f8916e1a933c8858b700cf5f172d10186
Added more remarks about 8-bit wide RAM access.

diff -r af46c81f8916 -r 0e1245115d28 ULA.txt
--- a/ULA.txt	Fri Dec 31 15:11:32 2021 +0100
+++ b/ULA.txt	Fri Dec 31 15:12:51 2021 +0100
@@ -223,7 +223,8 @@
 access rate employed by the ULA does not involve the complete process for
 accessing the RAM: upon setting up the address and issuing the ~RAS signal,
 the ULA is able to make a pair of column accesses on the same "row" of memory,
-effectively achieving an average access rate of 4MHz.
+effectively achieving an average access rate of 4MHz in an 8-bit
+configuration.
 
 However, if arbitrary pairs of column accesses were to be attempted, as would
 be required by CPU and ULA interleaving, the ~RAS signal would need to be
@@ -231,6 +232,13 @@
 access a memory location to beyond the period of a 4MHz cycle, making it
 impossible to employ interleaved accesses at such a rate.
 
+In conclusion, a strict interleaving strategy is not possible, but by using
+pixel data buffering and employing two ULA accesses per 2MHz cycle to obtain
+two bytes in that cycle, each adjacent 2MHz cycle can be given to the CPU,
+thus achieving an effective throughput during display update periods of 3
+bytes for every pair of cycles (2 bytes for the ULA, 1 byte for the CPU), and
+thus 1.5 bytes per cycle, giving an illusion of 3MHz access to RAM.
+
 CPU Clock Notes
 ---------------