# HG changeset patch # User Paul Boddie # Date 1586290393 -7200 # Node ID 2baff40d749c9246fc002054743bf1a2467284da # Parent 7bef8e6b48a1fd7830121d644f3ce998c7e52cc1 Added remarks on 8-bit wide RAM access and possible 8MHz ULA frequency. diff -r 7bef8e6b48a1 -r 2baff40d749c Electron.txt --- a/Electron.txt Tue Apr 07 21:31:19 2020 +0200 +++ b/Electron.txt Tue Apr 07 22:13:13 2020 +0200 @@ -93,9 +93,12 @@ have significantly lowered the total production cost. This might indicate that different choices would have been viable. For example, instead of employing 1-bit RAM chips in groups of four, perhaps two such groups might have been -employed, with the resulting memory architecture being simplified and the -corresponding component cost increase proving to be less than projections made -early in the design process. +employed, with the resulting memory architecture being simplified, the +performance requirements for the ULA being reduced (perhaps employing 8MHz +cycles instead of 16MHz to coordinate signalling, potentially reducing power +consumption and increasing yield and reliability), and the corresponding +component cost increase proving to be less than projections made early in the +design process, particularly if slower RAM chips became usable. Improving Display Capabilities ------------------------------ diff -r 7bef8e6b48a1 -r 2baff40d749c ULA.txt --- a/ULA.txt Tue Apr 07 21:31:19 2020 +0200 +++ b/ULA.txt Tue Apr 07 22:13:13 2020 +0200 @@ -137,6 +137,36 @@ See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm See: http://stardot.org.uk/forums/viewtopic.php?p=120438#p120438 +A Note on 8-Bit Wide RAM Access +------------------------------- + +It is worth considering the timing when 8 bits of data can be obtained at once +from the RAM chips: + + Time (ns): 0-------------- 500------------- ... + 2 MHz cycle: 0 1 ... + 8 MHz cycle: 0 1 2 3 0 1 2 3 ... + /-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_ ... + ~RAS: /---\___________/---\___________ ... + ~CAS: /-------\_______/-------\_______ ... +Address events: A B A B ... + Data events: F F ... + + ~RAS ops: 1 0 1 0 ... + ~CAS ops: 1 0 1 0 ... + + Address ops: a b a b ... + Data ops: f s f ... + + ~WE: ........W ... + PHI OUT: \_______/-------\_______/------- ... + CPU: L D L D ... + RnW: R R ... + +Since only one fetch is required per 2MHz cycle, instead of two fetches for +the 4-bit wide RAM arrangement, it seems likely that longer 8MHz cycles could +be used to coordinate the necessary signalling. + CPU Clock Notes ---------------