# HG changeset patch # User Paul Boddie # Date 1586982668 -7200 # Node ID 4f335343eec7ff0cbfd468df183e0b56c5e31b57 # Parent 8b00fd59f03ac642cea6dc4cd55765ceb1dddc13 Added clarifications about the use of 8MHz cycles with an 8-bit memory channel. In particular, 16MHz is still required for the pixel clock in MODE 0. diff -r 8b00fd59f03a -r 4f335343eec7 Electron.txt --- a/Electron.txt Mon Apr 13 17:05:49 2020 +0200 +++ b/Electron.txt Wed Apr 15 22:31:08 2020 +0200 @@ -95,10 +95,11 @@ 1-bit RAM chips in groups of four, perhaps two such groups might have been employed, with the resulting memory architecture being simplified, the performance requirements for the ULA being reduced (perhaps employing 8MHz -cycles instead of 16MHz to coordinate signalling, potentially reducing power -consumption and increasing yield and reliability), and the corresponding -component cost increase proving to be less than projections made early in the -design process, particularly if slower (and smaller) RAM chips became usable. +cycles instead of 16MHz to coordinate signalling, although retaining 16MHz +cycles for the MODE 0 pixel clock, potentially reducing power consumption and +increasing yield and reliability), and the corresponding component cost +increase proving to be less than projections made early in the design process, +particularly if slower (and smaller) RAM chips became usable. In the document "One of the Most Popular 65,536-Bit (64K) Dynamic RAMs The TMS 4164", a note is made of 4164 RAM prices dropping from $25 to $5 per unit in diff -r 8b00fd59f03a -r 4f335343eec7 ULA.txt --- a/ULA.txt Mon Apr 13 17:05:49 2020 +0200 +++ b/ULA.txt Wed Apr 15 22:31:08 2020 +0200 @@ -176,6 +176,10 @@ CPU to signal directly to the RAM instead of having the ULA perform the access signalling on the CPU's behalf. +Note that 16MHz cycles would still be needed for the pixel clock in MODE 0, +which needs to output eight pixels per 2MHz cycle, producing 640 monochrome +pixels per 80-byte line. + CPU Clock Notes ---------------