# HG changeset patch # User Paul Boddie # Date 1665759707 -7200 # Node ID 4f4cad6abd6dad33742cf6788b197929396a5ca6 # Parent becf57305c5187a198c451f6d4638818cdb2d96c Added notes about dual page mode transfers in each 2MHz cycle for an 8-bit RAM data bus configuration, suggesting how the screen memory could combine two separate banks of memory. diff -r becf57305c51 -r 4f4cad6abd6d ULA.txt --- a/ULA.txt Fri Oct 14 16:59:34 2022 +0200 +++ b/ULA.txt Fri Oct 14 17:01:47 2022 +0200 @@ -1543,13 +1543,53 @@ smaller unit of storage than a byte could possibly help to reduce the amount of storage and bandwidth required to reproduce the characters on the display. -Enhancement: High Resolution Graphics -------------------------------------- +Enhancement: High Resolution Graphics and Larger Colour Depths +-------------------------------------------------------------- Screen modes with higher resolutions and larger colour depths might be possible, but this would in most cases involve the allocation of more screen memory, and the ULA would probably then be obliged to page in such memory for -the CPU to be able to sensibly access it all. +the CPU to be able to sensibly access it all. Higher resolutions would also +involve a faster pixel clock. + +However, we may consider a doubled colour depth and the need for higher +bandwidth transfers by a ULA having an 8-bit data bus to access the RAM, +utilising two "page mode" transfers per 2MHz cycle. If such transfers were to +access consecutive bytes in the same memory region (for example, bytes &3000 +and &3001) this would require a change to the arrangement of screen memory, +also incurring changes to the memory map for larger modes: + + (&3000 &3001) (&3010 &3011) ... + (&3002 &3003) (&3012 &3013) + ... ... + (&300E &300F) (&301E &301F) + +If such transfers were to access two adjacent columns of bytes (for example, +bytes &3000 and &3008), this would still require a change in the step size +across the screen memory, also incur memory map changes for larger modes, and +the method for programs to update the screen would be more complicated: + + (&3000 &3008) (&3010 &3018) ... + (&3001 &3009) (&3011 &3019) + ... ... + (&3007 &300F) (&3017 &301F) + +However, such transfers could instead map the device address bit that is +toggled between transfers to the most significant system memory address bit. +Thus, bits in adjacent locations within each RAM device would actually reside +in different memory regions: + + (&3000 &B000) (&3008 &B008) ... + (&3001 &B001) (&3009 &B009) + ... ... + (&3007 &B007) (&300F &B00F) + +Since &B000 can also be considered as &3000 combined with &8000, this +introducing the asserted uppermost bit, address &B000 can be considered as +&3000 in an upper memory bank. + +Other mechanisms might be employed to allow programs to access the uppermost +bank, but the ULA would be able to access it trivially and unconditionally. Enhancement: Genlock Support ----------------------------