# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1351547713 -3600
# Node ID 5050f1bd14bba91bf86a14aa2e6c835c03995891
# Parent  f3f4e632c631f764f18942efab37502d6b5cf642
Updated the interpretation of how the RAM ICs are accessed by the ULA.

diff -r f3f4e632c631 -r 5050f1bd14bb ula.py
--- a/ula.py	Thu May 03 01:28:46 2012 +0200
+++ b/ula.py	Mon Oct 29 22:55:13 2012 +0100
@@ -83,10 +83,10 @@
 
     """
     A class representing the RAM circuits (IC4 to IC7). Each circuit
-    traditionally holds 64 kilobits, with two accesses required to read 2 bits
-    from each in order to obtain a whole byte. Here, we model the circuits with
-    a list of 65536 half-bytes with each bit representing a bit stored on a
-    separate IC.
+    traditionally holds 64 kilobits, with each access obtaining 1 bit from each
+    IC, and thus two accesses being required to obtain a whole byte. Here, we
+    model the circuits with a list of 65536 half-bytes with each bit in a
+    half-byte representing a bit stored on a separate IC.
     """
 
     def __init__(self):