# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1351636632 -3600
# Node ID 731d6b286df8bf58f6f7724b6c4123506b025f02
# Parent  6621d6210f8d22ec138f9c34946d1d5ce91a1906
Modelled the state of the ULA with a collection of latches instead of a counter.

diff -r 6621d6210f8d -r 731d6b286df8 ula.py
--- a/ula.py	Tue Oct 30 00:04:27 2012 +0100
+++ b/ula.py	Tue Oct 30 23:37:12 2012 +0100
@@ -159,7 +159,7 @@
 
         # Internal state.
 
-        self.cycle = 0          # counter within each 2MHz period
+        self.cycle = [0]*8      # counter within each 2MHz period represented by 8 latches
         self.access = 0         # counter used to determine whether a byte needs reading
         self.ram_address = 0    # address given to the RAM
         self.data = 0           # data read from the RAM
@@ -167,6 +167,8 @@
         self.writing_pixels = 0 # whether pixel data can be written
         self.buffer = [BLANK]*8 # pixel buffer for decoded RAM data
 
+        self.cycle[7] = 1       # assert the final latch (asserting the first on update)
+
         self.reset_vertical()
 
     def set_mode(self, mode):
@@ -309,9 +311,18 @@
 
         access_ram = not self.nmi and self.access == 0 and self.read_pixels() and not self.ssub
 
+        # Update the state of the device.
+        # NOTE: This is not meant to be "nice" Python, but instead models the
+        # NOTE: propagation of state through the latches.
+
+        self.cycle[0], self.cycle[1], self.cycle[2], self.cycle[3], \
+        self.cycle[4], self.cycle[5], self.cycle[6], self.cycle[7] = \
+        self.cycle[7], self.cycle[0], self.cycle[1], self.cycle[2], \
+        self.cycle[3], self.cycle[4], self.cycle[5], self.cycle[6]
+
         # Set row address (for ULA access only).
 
-        if self.cycle == 0:
+        if self.cycle[0]:
 
             # NOTE: Propagate CPU address here.
 
@@ -328,7 +339,7 @@
 
         # Latch row address, set column address (for ULA access only).
 
-        elif self.cycle == 1:
+        elif self.cycle[1]:
 
             # NOTE: Permit CPU access here.
 
@@ -342,7 +353,7 @@
 
         # Latch column address.
 
-        elif self.cycle == 2:
+        elif self.cycle[2]:
 
             # NOTE: Permit CPU access here.
 
@@ -352,7 +363,7 @@
         # Read 4 bits (for ULA access only).
         # NOTE: Perhaps map alternate bits, not half-bytes.
 
-        elif self.cycle == 3:
+        elif self.cycle[3]:
 
             # NOTE: Propagate CPU data here.
 
@@ -361,7 +372,7 @@
 
         # Set column address (for ULA access only).
 
-        elif self.cycle == 4:
+        elif self.cycle[4]:
             self.ram.column_deselect()
 
             # NOTE: Propagate CPU address here.
@@ -371,7 +382,7 @@
 
         # Latch column address.
 
-        elif self.cycle == 5:
+        elif self.cycle[5]:
 
             # NOTE: Permit CPU access here.
 
@@ -381,7 +392,7 @@
         # Read 4 bits (for ULA access only).
         # NOTE: Perhaps map alternate bits, not half-bytes.
 
-        elif self.cycle == 6:
+        elif self.cycle[6]:
 
             # NOTE: Propagate CPU data here.
 
@@ -396,7 +407,7 @@
 
         # Reset addresses.
 
-        elif self.cycle == 7:
+        elif self.cycle[7]:
             self.ram.column_deselect()
             self.ram.row_deselect()
 
@@ -404,8 +415,6 @@
 
             self.access = (self.access + 1) % self.access_frequency
 
-        self.cycle = (self.cycle + 1) % 8
-
 
 
         # Video signalling.