# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1440536244 -7200
# Node ID 73ec9c2e0c11213000cd8225c4e043fc6c743930
# Parent  4ba74d41cfbaafb18778849f764c5601e3b78533
Added multiple CPU stack "MMU" enhancement.

diff -r 4ba74d41cfba -r 73ec9c2e0c11 ULA.txt
--- a/ULA.txt	Fri Mar 06 01:13:44 2015 +0100
+++ b/ULA.txt	Tue Aug 25 22:57:24 2015 +0200
@@ -839,6 +839,31 @@
 as RAM-resident hardware sprites or indeed any feature demanding RAM access
 concurrent with the production of the display image.
 
+Enhancement: Multiple CPU Stacks
+--------------------------------
+
+The 6502 maintains a stack for subroutine calls and register storage in page
+&01. Although the stack register can be manipulated using the TSX and TXS
+instructions, thereby permitting the maintenance of multiple stack regions and
+thus the potential coexistence of multiple programs each using a separate
+region, only programs that make little use of the stack (perhaps avoiding
+deeply-nested subroutine invocations and significant register storage) would
+be able to coexist without overwriting each other's stacks.
+
+One way that this issue could be alleviated would involve the provision of a
+facility to redirect accesses to page &01 to other areas of memory. The ULA
+would provide a register that defines a physical page for the use of the CPU's
+"logical" page &01, and upon any access to page &01 by the CPU, the ULA would
+change the asserted address lines to redirect the access to the appropriate
+physical region.
+
+By providing an 8-bit register, mapping to the most significant byte (MSB) of
+a 16-bit address, the ULA could then replace any MSB equal to &01 with the
+register value before the access is made. Where multiple programs coexist,
+upon switching programs, the register would be updated to point the ULA to the
+appropriate stack location, thus providing a simple memory management unit
+(MMU) capability.
+
 ULA Pin Functions
 -----------------