# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1615036842 -3600
# Node ID 78d6156a1db35a27f3f252260042da66c7ba66e0
# Parent  6e4fcde513009a29e55c688a58c1c6c124e758a2
Added a note about 4MHz CPU/ULA memory access interleaving.

diff -r 6e4fcde51300 -r 78d6156a1db3 ULA.txt
--- a/ULA.txt	Wed Nov 11 01:33:16 2020 +0100
+++ b/ULA.txt	Sat Mar 06 14:20:42 2021 +0100
@@ -217,6 +217,20 @@
 the bandwidth is shared (MODE 4 to 6), consolidating pairs of ULA accesses into
 single cycles and freeing up an extra cycle for CPU accesses.
 
+A further consideration is whether the CPU and ULA could access the memory on
+interleaved 4MHz cycles, thus replicating the arrangement used by the CPU and
+Video ULA on the BBC Micro. One potential obstacle is that the apparent 4MHz
+access rate employed by the ULA does not involve the complete process for
+accessing the RAM: upon setting up the address and issuing the ~RAS signal,
+the ULA is able to make a pair of column accesses on the same "row" of memory,
+effectively achieving an average access rate of 4MHz.
+
+However, if arbitrary pairs of column accesses were to be attempted, as would
+be required by CPU and ULA interleaving, the ~RAS signal would need to be
+re-issued with different addresses being set up. This would expand the time to
+access a memory location to beyond the period of a 4MHz cycle, making it
+impossible to employ interleaved accesses at such a rate.
+
 CPU Clock Notes
 ---------------