# HG changeset patch # User Paul Boddie # Date 1586287879 -7200 # Node ID 7bef8e6b48a1fd7830121d644f3ce998c7e52cc1 # Parent f1ad140b086bc520e469bfea3e16890b2b496c73 Added some memory bandwidth and architecture notes. diff -r f1ad140b086b -r 7bef8e6b48a1 Electron.txt --- a/Electron.txt Tue Nov 26 15:38:07 2019 +0100 +++ b/Electron.txt Tue Apr 07 21:31:19 2020 +0200 @@ -88,6 +88,15 @@ peripheral would maintain its own framebuffer by registering writes on the bus to the display memory region. +Of course, the economic considerations related to the choice of RAM products +could be revisited, reviewing the assumption that the products chosen would +have significantly lowered the total production cost. This might indicate that +different choices would have been viable. For example, instead of employing +1-bit RAM chips in groups of four, perhaps two such groups might have been +employed, with the resulting memory architecture being simplified and the +corresponding component cost increase proving to be less than projections made +early in the design process. + Improving Display Capabilities ------------------------------ diff -r f1ad140b086b -r 7bef8e6b48a1 ULA.txt --- a/ULA.txt Tue Nov 26 15:38:07 2019 +0100 +++ b/ULA.txt Tue Apr 07 21:31:19 2020 +0200 @@ -640,14 +640,14 @@ This would improve CPU bandwidth as follows: - Standard ULA Enhanced ULA -MODE 0, 1, 2 9728 bytes 19456 bytes -MODE 3 12288 bytes 24576 bytes -MODE 4, 5 19968 bytes 29696 bytes -MODE 6 19968 bytes 32256 bytes + Standard ULA Enhanced ULA % Total Bandwidth Speedup +MODE 0, 1, 2 9728 bytes 19456 bytes 24% -> 49% 2 +MODE 3 12288 bytes 24576 bytes 31% -> 62% 2 +MODE 4, 5 19968 bytes 29696 bytes 50% -> 74% 1.5 +MODE 6 19968 bytes 32256 bytes 50% -> 81% 1.6 -(Here, the uncontended 2MHz bandwidth for a display period would be 39936 -bytes, being 128 cycles per line over 312 lines.) +(Here, the uncontended total 2MHz bandwidth for a display period would be +39936 bytes, being 128 cycles per line over 312 lines.) With such an enhancement, MODE 0 to 3 experience a doubling of CPU bandwidth because all access opportunities to RAM are doubled. Meanwhile, in the other @@ -656,7 +656,12 @@ Unfortunately, the mechanism for accessing the RAM is too slow to provide data within the time constraints of 2MHz operation. There is no time remaining in a -2MHz cycle for the CPU to receive and process any retrieved data. +2MHz cycle for the CPU to receive and process any retrieved data once the +necessary signalling has been performed. The only way for the CPU to be able +to access the RAM quickly enough would be to do away with the double 4-bit +access mechanism and to have a single 8-bit channel to the memory. This would +require twice as many 1-bit RAM chips or a different kind of RAM chip, but it +would also potentially simplify the ULA. Enhancement: Region Blanking ----------------------------