# HG changeset patch # User Paul Boddie # Date 1444660614 -7200 # Node ID 89b5767d944def0c6e7514de886db19729d93a96 # Parent 2fb743173c10f204fe719fb6969af9bd06846c7c Added a note about redirecting zero page accesses as well as stack accesses. diff -r 2fb743173c10 -r 89b5767d944d ULA.txt --- a/ULA.txt Wed Sep 30 01:47:16 2015 +0200 +++ b/ULA.txt Mon Oct 12 16:36:54 2015 +0200 @@ -975,8 +975,8 @@ as RAM-resident hardware sprites or indeed any feature demanding RAM access concurrent with the production of the display image. -Enhancement: Multiple CPU Stacks --------------------------------- +Enhancement: Multiple CPU Stacks and Zero Pages +----------------------------------------------- The 6502 maintains a stack for subroutine calls and register storage in page &01. Although the stack register can be manipulated using the TSX and TXS @@ -1000,6 +1000,19 @@ appropriate stack location, thus providing a simple memory management unit (MMU) capability. +In a similar fashion, zero page accesses could also be redirected so that code +could run from sideways RAM and have zero page operations redirected to "upper +memory" - for example, to page &BE (with stack accesses redirected to page +&BF, perhaps) - thereby permitting most CPU operations to occur without +inadvertent accesses to "lower memory" (the RAM) which would risk stalling the +CPU as it contends with the ULA for memory access. + +Such facilities could also be provided by a separate circuit between the CPU +and ULA in a fashion similar to that employed by a "turbo" board, but unlike +such boards, no additional RAM would be provided: all memory accesses would +occur as normal through the ULA, albeit redirected when configured +appropriately. + ULA Pin Functions -----------------