# HG changeset patch # User Paul Boddie # Date 1328742862 -3600 # Node ID 94641db1c64a00ff77a7de36609e90e46b648186 # Parent 007ccb845f7e64b5bfba56db59b8f305e10f27fb Changed the description of the memory access behaviour after consulting the TM4164EC4 datasheet. diff -r 007ccb845f7e -r 94641db1c64a ULA.txt --- a/ULA.txt Fri Feb 03 00:21:28 2012 +0100 +++ b/ULA.txt Thu Feb 09 00:14:22 2012 +0100 @@ -30,14 +30,20 @@ 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ... ~RAS: 0 1 0 1 ... ~CAS: 0 1 0 1 0 1 0 1 ... - A B - F S + A B B A B B + F S F S Here, "A" indicates the row and column addresses being latched into the RAM -(on a negative edge for RAS and CAS respectively), and "B" indicates the +(on a negative edge for ~RAS and ~CAS respectively), and "B" indicates the second column address being latched into the RAM. Presumably, the first and second half-bytes can be read at "F" and "S" respectively. +Note that the Service Manual refers to the negative edge of RAS and CAS, but +the datasheet for the similar TM4164EC4 product shows latching on the negative +edge of ~RAS and ~CAS. It is possible that the Service Manual also intended to +communicate the latter behaviour. In the TM4164EC4 datasheet, it appears that +"page mode" provides the appropriate behaviour for that particular product. + Shadow/Expanded Memory ---------------------- @@ -408,9 +414,11 @@ RA0...RA7 (address lines for sending both row and column addresses to the RAM) - RAS (row address strobe setting the row address on a negative edge) + RAS (row address strobe setting the row address on a negative edge - see the + timing notes) - CAS (column address strobe setting the column address on a negative edge) + CAS (column address strobe setting the column address on a negative edge - + see the timing notes) WE (sets write enable with logic 0, read with logic 1)