# HG changeset patch # User Paul Boddie # Date 1328832440 -3600 # Node ID 9adfa08bfa74973defd0345bc5deff637c9665e5 # Parent 94641db1c64a00ff77a7de36609e90e46b648186 Improved the general timing description and revised the access event timeline. Added the points at which addresses should presumably be set for RAM access. diff -r 94641db1c64a -r 9adfa08bfa74 ULA.txt --- a/ULA.txt Thu Feb 09 00:14:22 2012 +0100 +++ b/ULA.txt Fri Feb 10 01:07:20 2012 +0100 @@ -3,8 +3,8 @@ According to the above (15.3.2 in the AUG), there are 312 scanlines, 256 of which are used to generate pixel data. At 50Hz, this means that 128 cycles are -used to produce pixel data (2000000 cycles / 50 = 40000 cycles; 40000 cycles / -312 ~= 128 cycles). This is consistent with the observation that each scanline +spent on each scanline (2000000 cycles / 50 = 40000 cycles; 40000 cycles / 312 +~= 128 cycles). This is consistent with the observation that each scanline requires at most 80 bytes of data, and that the ULA is apparently busy for 40 out of 64 microseconds in each scanline. @@ -25,18 +25,21 @@ Each 16MHz cycle is approximately 62.5ns. To access the memory, the following patterns corresponding to 16MHz cycles are required: - Time (ns): 0-------------- 500------------ + Time (ns): 0-------------- 500------------ ... 2 MHz cycle: 0 1 ... 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ... - ~RAS: 0 1 0 1 ... - ~CAS: 0 1 0 1 0 1 0 1 ... - A B B A B B - F S F S + ~RAS: 0 1 0 1 ... + ~CAS: 0 1 0 1 0 1 0 1 ... + A B B A B B ... + F S F S ... + a b b a b b ... Here, "A" indicates the row and column addresses being latched into the RAM (on a negative edge for ~RAS and ~CAS respectively), and "B" indicates the second column address being latched into the RAM. Presumably, the first and -second half-bytes can be read at "F" and "S" respectively. +second half-bytes can be read at "F" and "S" respectively, and the row and +column addresses must be made available at "a" and "b" respectively at the +latest. Note that the Service Manual refers to the negative edge of RAS and CAS, but the datasheet for the similar TM4164EC4 product shows latching on the negative @@ -44,6 +47,12 @@ communicate the latter behaviour. In the TM4164EC4 datasheet, it appears that "page mode" provides the appropriate behaviour for that particular product. +See: http://www.datasheetarchive.com/dl/Datasheets-112/DSAP0051030.pdf + +Each 62.5ns cycle happens to correspond to 64µs divided by 1024, meaning that +each scanline can be divided into 1024 cycles, although only 640 at most are +actively used to provide pixel data. + Shadow/Expanded Memory ----------------------