# HG changeset patch # User Paul Boddie # Date 1646235760 -3600 # Node ID b26589485c226778ea20e85a526104968117dd3c # Parent 0e1245115d28446b22a31327ed8b5050450b0aee Added more 8-bit wide RAM access notes plus alternative keyboard matrix support. diff -r 0e1245115d28 -r b26589485c22 ULA.txt --- a/ULA.txt Fri Dec 31 15:12:51 2021 +0100 +++ b/ULA.txt Wed Mar 02 16:42:40 2022 +0100 @@ -239,6 +239,102 @@ bytes for every pair of cycles (2 bytes for the ULA, 1 byte for the CPU), and thus 1.5 bytes per cycle, giving an illusion of 3MHz access to RAM. +Some other considerations apply to introducing 8-bit wide access. The ULA +employs four pins for data transfer to and from the memory devices (RAM0..3), +and obviously another four pins would be needed in an 8-bit wide scheme. +However, there may have been a physical limitation on the number of pins +permissible on a ULA package or the device's socket. This would necessitate +the reassignment of pins, although few are readily available for such +reassignment. + +One approach might involve connecting the RAM devices to the CPU data bus, +with each line connecting to a different RAM chip. The signalling of the RAM +would remain under the control of the ULA, thus preventing the RAM devices +from interfering with other memory transfer operations, with the ROM +signalling also remaining under the ULA's control. One potential disadvantage +of this scheme would involve the elimination of the separate data paths +between the CPU and ROM and between the ULA and RAM. + +Another approach might involve reclaiming the keyboard input pins (KBD0..3) as +data pins for ULA access to RAM. This would necessitate the reorganisation of +the keyboard interface, perhaps integrating the keyboard matrix more directly +as a kind of ROM device. A bus transceiver could be used to isolate the +keyboard inputs, with a pin being used to control the transceiver, since the +keyboard data lines are pulled high. In effect, the transceiver would act as a +kind of output enable for the keyboard. + +To make the matrix appear within the sideways ROM region of the memory map, +A15 would need to be set to a high value and A14 to a low value. Signals A13 +to A0 would then be brought low to select the appropriate column, with the +individual key states being made available via data lines, perhaps D3 to D0. +This mostly retains the existing addressing arrangement and scanning +mechanism. Internally, the ULA would continue to enable access to the keyboard +through the ROM paging mechanism, but instead of integrating separate data +pins into the CPU's data path, it would integrate the keyboard inputs using +the transceiver. + +Enhancement: Keyboard Matrix Scanning +------------------------------------- + +The keyboard scanning mechanism is presumably designed to be as inexpensive as +possible, being driven by software and avoiding extra logic, but at the +expense of occupying large regions of the memory map when paged in. A more +efficient mapping of the keyboard columns could possibly be done using +decoders such as the 74xx138 part which permits the decoding of three inputs +to select one of eight outputs. Using two of these parts, six address lines +would be dedicated to the keyboard columns as follows: + + A5...A3 select up to eight columns via one decoder + A2...A0 select up to eight columns via another decoder + +In this arrangement, only one of the two ranges of pins would be used at any +given time. If the ULA were to require a certain combination of the remaining +address bits, a region as small as 64 bytes could be dedicated to the +keyboard. + +A more efficient arrangement could be used by introducing logic that allows +the decoders to work together to address the keyboard: + + A2...A0 select up to eight columns via both decoders + A3 would enable one decoder if low and the other decoder if high + +With ULA constraints on the remaining address bits, a 16-byte region could be +used to represent the keyboard. + +A further refinement might involve combining the existing columns into groups +of eight keys. This would reduce the number of columns to seven, requiring +only three address lines, with all eight data lines being used to read the +matrix. + +On the BBC Micro, the system 6522 VIA is used to monitor and read from the +keyboard. The memory locations involved with this chip are located in the +region from &FE40 to &FE7F inclusive, although the memory is allocated in a +way that is appropriate to operate that chip, as opposed to merely exposing +the keyboard matrix. + +Enhancement: Hardware Device Selection +-------------------------------------- + +An alternative to the existing, rather cumbersome, sideways ROM mapping of the +keyboard might involve making it accessible via a hardware-related memory page +like page FE. With ULA addresses confined to FE0x, and with the ULA itself +having to trap accesses to page FE, the page selection signal might be brought +out of the ULA instead of any dedicated signal for the keyboard. Various +address lines corresponding to A7 through A4, or a subset of these, could be +fed into a decoder to permit the selection of other devices, with the keyboard +being one of these. + +Meanwhile, a more efficient keyboard mapping using the above matrix +enhancement would permit the different keyboard columns to appear as a group +of sixteen or eight bytes. Thus: + + A15...A8 select page FE + A7...A4 select a device or peripheral + A3...A0 select a register or keyboard column + +Conceivably, devices such as sound generators could be mapped to device +regions. + CPU Clock Notes ---------------