# HG changeset patch # User Paul Boddie # Date 1586703908 -7200 # Node ID b3383787c26f3ad6baf7baf47ea5ae19a0fb9ccf # Parent 2baff40d749c9246fc002054743bf1a2467284da Added more remarks, particularly regarding direct CPU access to RAM. diff -r 2baff40d749c -r b3383787c26f Electron.txt --- a/Electron.txt Tue Apr 07 22:13:13 2020 +0200 +++ b/Electron.txt Sun Apr 12 17:05:08 2020 +0200 @@ -98,7 +98,7 @@ cycles instead of 16MHz to coordinate signalling, potentially reducing power consumption and increasing yield and reliability), and the corresponding component cost increase proving to be less than projections made early in the -design process, particularly if slower RAM chips became usable. +design process, particularly if slower (and smaller) RAM chips became usable. Improving Display Capabilities ------------------------------ diff -r 2baff40d749c -r b3383787c26f ULA.txt --- a/ULA.txt Tue Apr 07 22:13:13 2020 +0200 +++ b/ULA.txt Sun Apr 12 17:05:08 2020 +0200 @@ -150,7 +150,7 @@ ~RAS: /---\___________/---\___________ ... ~CAS: /-------\_______/-------\_______ ... Address events: A B A B ... - Data events: F F ... + Data events: E E ... ~RAS ops: 1 0 1 0 ... ~CAS ops: 1 0 1 0 ... @@ -163,10 +163,17 @@ CPU: L D L D ... RnW: R R ... +Here, "E" indicates the availability of an entire byte. + Since only one fetch is required per 2MHz cycle, instead of two fetches for the 4-bit wide RAM arrangement, it seems likely that longer 8MHz cycles could be used to coordinate the necessary signalling. +Another conceivable simplification from using an 8-bit wide RAM access channel +with a single access within each 2MHz cycle is the possibility of allowing the +CPU to signal directly to the RAM instead of having the ULA perform the access +signalling on the CPU's behalf. + CPU Clock Notes ---------------