# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1479143917 -3600
# Node ID d998a098edb629ff9f33f8ea00bb0b29cbdbcc88
# Parent  65b890e3e7f68e65612319b8eefe602cceaeed74
Added a note about the CPU clock phases.

diff -r 65b890e3e7f6 -r d998a098edb6 ULA.txt
--- a/ULA.txt	Sun Sep 04 00:59:40 2016 +0200
+++ b/ULA.txt	Mon Nov 14 18:18:37 2016 +0100
@@ -120,6 +120,17 @@
 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
 See: http://stardot.org.uk/forums/viewtopic.php?p=120438#p120438
 
+CPU Clock Notes
+---------------
+
+"The 6502 has a synchronous memory bus where the master clock is divided into
+two phases (Phase 1 and Phase 2). The address is always generated during Phase
+1 and all memory accesses take place during Phase 2."
+
+Thus, the inverse of PHI OUT provides the other phase of the clock.
+
+See: http://www.jmargolin.com/vgens/vgens.htm
+
 Bandwidth Figures
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