# HG changeset patch # User Paul Boddie # Date 1665961789 -7200 # Node ID e16067046f2af3a9d19182220e61d6f2fd1ab46f # Parent 796798b4d18a0e6ddf103ec31ca80496d57b1e83 Fixed CPU clock cycle scheduling, synchronising with memory signalling. diff -r 796798b4d18a -r e16067046f2a ULA.txt --- a/ULA.txt Sun Oct 16 01:27:06 2022 +0200 +++ b/ULA.txt Mon Oct 17 01:09:49 2022 +0200 @@ -72,7 +72,8 @@ ~RAS: /---\___________/---\___________ ... ~CAS: /-----\___/-\___/-----\___/-\___ ... Address events: A B C A B C ... - Data events: F S F S ... + Data events: ...F ...S ...F ...S ... + ~WE: W W ... ~RAS ops: 1 0 1 0 ... ~CAS ops: 1 0 1 0 1 0 1 0 ... @@ -80,14 +81,13 @@ Address ops: a.b. c. a.b. c. ... Data ops: s f s f ... - ~WE: ......W ... - PHI OUT: \_______________/--------------- ... - CPU (RAM): L D ... - RnW: R ... + PHI OUT: ----\_______/------------------- ... + CPU (RAM): .....L ....D ... + RnW: .....R ... - PHI OUT: \_______/-------\_______/------- ... - CPU (ROM): L D L D ... - RnW: R R ... + PHI OUT: ----\_______/-------\_______/--- ... + CPU (ROM): D .....L ....D .....L .... ... + RnW: .....R .....R ... ~RAS must be high for 100ns, ~CAS must be high for 50ns. ~RAS must be low for 150ns, ~CAS must be low for 90ns. @@ -103,15 +103,6 @@ are brought low. Data can be read at "f" and "s" for the first and second half-bytes respectively. -For the CPU, "L" indicates the point at which an address is taken from the CPU -address bus, on a negative edge of PHI OUT, with "D" being the point at which -data may either be read or be asserted for writing, on a positive edge of PHI -OUT. Here, PHI OUT is driven at 1MHz. Given that ~WE needs to be driven low -for writing or high for reading, and thus propagates RnW from the CPU, this -would need to be done before data would be retrieved and, according to the -TM4164EC4 datasheet, even as late as the column address is presented and ~CAS -brought low. - The TM4164EC4-15 has a row address access time of 150ns (maximum) and a column address access time of 90ns (maximum), which appears to mean that ~RAS must be held low for at least 150ns and that ~CAS must be held low for at least 90ns @@ -133,6 +124,29 @@ from the RAM, which is approximately 7 cycles (at 16MHz): much longer than the 4 cycles that would be required for 2MHz operation. +Write operations expose some uncertainty about the relationship between the +ULA's RAM access schedule and the PHI OUT clock. The Service Manual shows PHI +IN (which should be the ULA's PHI OUT signal) as being synchronised with ~RAS. +Since the CPU makes its address available potentially as late as 140ns after +its PHI2 clock goes low (this clock being broadly similar to PHI OUT), it +would make no sense to expect the ULA to be able perform a memory access +immediately. What seems more likely is that the CPU makes data available, and +this is written during the next 2MHz cycle. + +For the CPU, "L" indicates the point at which an address is taken from the CPU +address bus, following a negative edge of PHI OUT, with "D" being the point at +which data may be asserted for writing, following a positive edge of PHI OUT. +Here, PHI OUT is driven at 1MHz. Given that ~WE needs to be driven low for +writing or high for reading, and thus propagates RnW from the CPU, this would +need to be done before data would be retrieved and, according to the TM4164EC4 +datasheet, even as late as the column address is presented and ~CAS brought +low. + +It must be concluded that where accesses are interleaved between the CPU and +ULA, the CPU access begins concurrently with the ULA access, with the CPU +address and data retained by the ULA, and after the ULA access, the rest of +the CPU transaction occurs in the following 2MHz cycle. + See: Acorn Electron Advanced User Guide See: Acorn Electron Service Manual http://chrisacorns.computinghistory.org.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf @@ -140,6 +154,9 @@ See: http://stardot.org.uk/forums/viewtopic.php?p=120438#p120438 See: One of the Most Popular 65,536-Bit (64K) Dynamic RAMs The TMS 4164 http://smithsonianchips.si.edu/augarten/p64.htm +See: https://www.mups.co.uk/project/hardware/acorn_electron/ +See: Rockwell R650X and R651X Microprocessors (CPU) +See: http://wilsonminesco.com/6502primer/ A Note on 8-Bit Wide RAM Access ------------------------------- @@ -154,18 +171,18 @@ ~RAS: /---\___________/---\___________ ... ~CAS: /-------\_______/-------\_______ ... Address events: A B A B ... - Data events: E E ... + Data events: ...E ...E ... + ~WE: W W ... ~RAS ops: 1 0 1 0 ... ~CAS ops: 1 0 1 0 ... - Address ops: a b a b ... + Address ops: a. b. a. b. ... Data ops: f s f ... - ~WE: ........W ... - PHI OUT: \_______/-------\_______/------- ... - CPU: L D L D ... - RnW: R R ... + PHI OUT: ----\_______/-------\_______/--- ... + CPU: D .....L ....D .....L .... ... + RnW: .....R .....R ... Here, "E" indicates the availability of an entire byte. @@ -194,18 +211,18 @@ ~RAS: /---\___________/---\___________ ... ~CAS: /-----\___/-\___/-----\___/-\___ ... Address events: A B C A B C ... - Data events: 1 2 1 2 ... + Data events: ...1 ...2 ...1 ...2 ... + ~WE: W W ... ~RAS ops: 1 0 1 0 ... ~CAS ops: 1 0 1 0 1 0 1 0 ... - Address ops: a b c a b c ... + Address ops: a.b. c a.b. c ... Data ops: s f s f ... - ~WE: ......W ... - PHI OUT: \_______/-------\_______/------- ... - CPU: L D L D ... - RnW: R R ... + PHI OUT: ----\_______/-------\_______/--- ... + CPU: D .....L ....D .....L .... ... + RnW: .....R .....R ... Here, "1" and "2" in the data events correspond to whole byte accesses, effectively upgrading the half-byte "F" and "S" events in the existing ULA