1.1 --- a/ULA.txt Sun Jan 29 21:50:13 2012 +0100
1.2 +++ b/ULA.txt Fri Feb 03 00:21:28 2012 +0100
1.3 @@ -3,10 +3,10 @@
1.4
1.5 According to the above (15.3.2 in the AUG), there are 312 scanlines, 256 of
1.6 which are used to generate pixel data. At 50Hz, this means that 128 cycles are
1.7 -used to produce pixel data (2000000 / 50 = 40000; 40000 / 312 ~= 128). This is
1.8 -consistent with the observation that each scanline requires at most 80 bytes
1.9 -of data, and that the ULA is apparently busy for 40 out of 64 microseconds in
1.10 -each scanline.
1.11 +used to produce pixel data (2000000 cycles / 50 = 40000 cycles; 40000 cycles /
1.12 +312 ~= 128 cycles). This is consistent with the observation that each scanline
1.13 +requires at most 80 bytes of data, and that the ULA is apparently busy for 40
1.14 +out of 64 microseconds in each scanline.
1.15
1.16 See: Acorn Electron Advanced User Guide
1.17 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
1.18 @@ -20,6 +20,40 @@
1.19 frequency is divided by the ULA (IC1) depending on the screen mode in use.
1.20
1.21 See: Acorn Electron Service Manual
1.22 + http://acorn.chriswhy.co.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf
1.23 +
1.24 +Each 16MHz cycle is approximately 62.5ns. To access the memory, the following
1.25 +patterns corresponding to 16MHz cycles are required:
1.26 +
1.27 + Time (ns): 0-------------- 500------------
1.28 + 2 MHz cycle: 0 1 ...
1.29 + 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
1.30 + ~RAS: 0 1 0 1 ...
1.31 + ~CAS: 0 1 0 1 0 1 0 1 ...
1.32 + A B
1.33 + F S
1.34 +
1.35 +Here, "A" indicates the row and column addresses being latched into the RAM
1.36 +(on a negative edge for RAS and CAS respectively), and "B" indicates the
1.37 +second column address being latched into the RAM. Presumably, the first and
1.38 +second half-bytes can be read at "F" and "S" respectively.
1.39 +
1.40 +Shadow/Expanded Memory
1.41 +----------------------
1.42 +
1.43 +The Electron exposes all sixteen address lines and all eight data lines
1.44 +through the expansion bus. Using such lines, it is possible to provide
1.45 +additional memory - typically sideways ROM and RAM - on expansion cards and
1.46 +through cartridges, although the official cartridge specification provides
1.47 +fewer address lines and only seeks to provide access to memory in 16K units.
1.48 +
1.49 +Various modifications and upgrades were developed to offer "turbo"
1.50 +capabilities to the Electron, permitting the CPU to access a separate 8K of
1.51 +RAM at 2MHz, presumably preventing access to the low 8K of RAM accessible via
1.52 +the ULA through additional logic. However, an enhanced ULA might support
1.53 +independent CPU access to memory over the expansion bus by allowing itself to
1.54 +be discharged from providing access to memory, potentially for a range of
1.55 +addresses, and for the CPU to communicate with external memory uninterrupted.
1.56
1.57 Hardware Scrolling
1.58 ------------------