1.1 --- a/Electron.txt Tue Apr 07 21:31:19 2020 +0200
1.2 +++ b/Electron.txt Tue Apr 07 22:13:13 2020 +0200
1.3 @@ -93,9 +93,12 @@
1.4 have significantly lowered the total production cost. This might indicate that
1.5 different choices would have been viable. For example, instead of employing
1.6 1-bit RAM chips in groups of four, perhaps two such groups might have been
1.7 -employed, with the resulting memory architecture being simplified and the
1.8 -corresponding component cost increase proving to be less than projections made
1.9 -early in the design process.
1.10 +employed, with the resulting memory architecture being simplified, the
1.11 +performance requirements for the ULA being reduced (perhaps employing 8MHz
1.12 +cycles instead of 16MHz to coordinate signalling, potentially reducing power
1.13 +consumption and increasing yield and reliability), and the corresponding
1.14 +component cost increase proving to be less than projections made early in the
1.15 +design process, particularly if slower RAM chips became usable.
1.16
1.17 Improving Display Capabilities
1.18 ------------------------------
2.1 --- a/ULA.txt Tue Apr 07 21:31:19 2020 +0200
2.2 +++ b/ULA.txt Tue Apr 07 22:13:13 2020 +0200
2.3 @@ -137,6 +137,36 @@
2.4 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
2.5 See: http://stardot.org.uk/forums/viewtopic.php?p=120438#p120438
2.6
2.7 +A Note on 8-Bit Wide RAM Access
2.8 +-------------------------------
2.9 +
2.10 +It is worth considering the timing when 8 bits of data can be obtained at once
2.11 +from the RAM chips:
2.12 +
2.13 + Time (ns): 0-------------- 500------------- ...
2.14 + 2 MHz cycle: 0 1 ...
2.15 + 8 MHz cycle: 0 1 2 3 0 1 2 3 ...
2.16 + /-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_ ...
2.17 + ~RAS: /---\___________/---\___________ ...
2.18 + ~CAS: /-------\_______/-------\_______ ...
2.19 +Address events: A B A B ...
2.20 + Data events: F F ...
2.21 +
2.22 + ~RAS ops: 1 0 1 0 ...
2.23 + ~CAS ops: 1 0 1 0 ...
2.24 +
2.25 + Address ops: a b a b ...
2.26 + Data ops: f s f ...
2.27 +
2.28 + ~WE: ........W ...
2.29 + PHI OUT: \_______/-------\_______/------- ...
2.30 + CPU: L D L D ...
2.31 + RnW: R R ...
2.32 +
2.33 +Since only one fetch is required per 2MHz cycle, instead of two fetches for
2.34 +the 4-bit wide RAM arrangement, it seems likely that longer 8MHz cycles could
2.35 +be used to coordinate the necessary signalling.
2.36 +
2.37 CPU Clock Notes
2.38 ---------------
2.39