1.1 --- a/ULA.txt Tue Jun 21 16:06:47 2016 +0200
1.2 +++ b/ULA.txt Tue Jun 21 20:18:37 2016 +0200
1.3 @@ -54,20 +54,28 @@
1.4 /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ ...
1.5 ~RAS: /---\___________/---\___________ ...
1.6 ~CAS: /-----\___/-\___/-----\___/-\___ ...
1.7 - A B C A B C ...
1.8 - F S F S ...
1.9 - a b c a b c ...
1.10 - s f s f ...
1.11 +Address events: A B C A B C ...
1.12 + Data events: F S F S ...
1.13
1.14 - ~WE: ......W ...
1.15 + ~RAS ops: 1 0 1 0 ...
1.16 + ~CAS ops: 1 0 1 0 1 0 1 0 ...
1.17 +
1.18 + Address ops: a b c a b c ...
1.19 + Data ops: s f s f ...
1.20 +
1.21 + ~WE: ......W ...
1.22 PHI OUT: \_______________/--------------- ...
1.23 CPU (RAM): L D ...
1.24 - RnW: R ...
1.25 + RnW: R ...
1.26
1.27 PHI OUT: \_______/-------\_______/------- ...
1.28 CPU (ROM): L D L D ...
1.29 RnW: R R ...
1.30
1.31 +~RAS must be high for 100ns, ~CAS must be high for 50ns.
1.32 +~RAS must be low for 150ns, ~CAS must be low for 90ns.
1.33 +Data is available 150ns after ~RAS goes low, 90ns after ~CAS goes low.
1.34 +
1.35 Here, "A" and "B" respectively indicate the row and first column addresses
1.36 being latched into the RAM (on a negative edge for ~RAS and ~CAS
1.37 respectively), and "C" indicates the second column address being latched into
2.1 --- a/ula.py Tue Jun 21 16:06:47 2016 +0200
2.2 +++ b/ula.py Tue Jun 21 20:18:37 2016 +0200
2.3 @@ -375,33 +375,32 @@
2.4
2.5 def posedge_ram(self):
2.6
2.7 - "RAM signalling."
2.8 + """
2.9 + RAM signalling.
2.10 +
2.11 + States handled: * _ * * _ * * _
2.12 + """
2.13
2.14 # Clock management.
2.15
2.16 - # Reset addresses.
2.17 + # Read 4 bits (for RAM access only).
2.18
2.19 if self.cycle == 1:
2.20 +
2.21 + # Reset addresses.
2.22 +
2.23 self.ram.column_deselect()
2.24 self.ram.row_deselect()
2.25
2.26 - # Read the CPU address, if appropriate.
2.27 -
2.28 - if not self.access_ram():
2.29 - self.cpu_update_clock()
2.30 -
2.31 - # Set row address (for ULA access only).
2.32 -
2.33 - elif self.cycle == 2:
2.34 + # Either read from a required address or transfer CPU data.
2.35
2.36 - # Either assert a required address or propagate the CPU address.
2.37 + if self.have_pixels:
2.38 + self.data = (self.data & 0xf0) | self.ram.data
2.39 + else:
2.40 + self.cpu_update_clock()
2.41 + self.cpu_transfer_low()
2.42
2.43 - if self.access_ram():
2.44 - self.init_row_address(self.pixel_address)
2.45 - else:
2.46 - self.init_row_address(self.cpu_address)
2.47 -
2.48 - # Latch row address, set column address (for ULA access only).
2.49 + # Latch row address.
2.50
2.51 elif self.cycle == 4:
2.52
2.53 @@ -409,13 +408,6 @@
2.54
2.55 self.ram.row_select(self.ram_address)
2.56
2.57 - # Either assert a required address or propagate the CPU address.
2.58 -
2.59 - if self.access_ram():
2.60 - self.init_column_address(self.pixel_address, 0)
2.61 - else:
2.62 - self.init_column_address(self.cpu_address, 0)
2.63 -
2.64 # Latch column address.
2.65
2.66 elif self.cycle == 8:
2.67 @@ -431,19 +423,20 @@
2.68 else:
2.69 self.cpu_transfer_select()
2.70
2.71 - # Cycle handled in negedge.
2.72 -
2.73 - # Set column address (for ULA access only).
2.74 + # Read 4 bits (for RAM access only).
2.75
2.76 elif self.cycle == 32:
2.77 +
2.78 + # Prepare to latch column address.
2.79 +
2.80 self.ram.column_deselect()
2.81
2.82 - # Either assert a required address or propagate the CPU address.
2.83 + # Either read from a required address or transfer CPU data.
2.84
2.85 if self.access_ram():
2.86 - self.init_column_address(self.pixel_address, 1)
2.87 + self.data = self.ram.data << 4
2.88 else:
2.89 - self.init_column_address(self.cpu_address, 1)
2.90 + self.cpu_transfer_high()
2.91
2.92 # Latch column address.
2.93
2.94 @@ -453,15 +446,6 @@
2.95
2.96 self.ram.column_select(self.ram_address)
2.97
2.98 - # Read 4 bits (for ULA access only).
2.99 -
2.100 - elif self.cycle == 128:
2.101 -
2.102 - # Advance to the next column even if an NMI is asserted.
2.103 -
2.104 - if self.would_access_ram():
2.105 - self.next_horizontal()
2.106 -
2.107 def posedge_pixel(self):
2.108
2.109 "Pixel production."
2.110 @@ -487,7 +471,7 @@
2.111 """
2.112 Update the state of the device.
2.113
2.114 - Cycles handled: * _ _ _ * _ _ *
2.115 + States handled: * * * _ _ * _ *
2.116 """
2.117
2.118 # Clock management.
2.119 @@ -500,28 +484,52 @@
2.120 self.pcycle = 1
2.121 self.have_pixels = 0
2.122
2.123 - # Read 4 bits (for ULA access only).
2.124 + # Set row address (for RAM access only).
2.125
2.126 - elif self.cycle == 16:
2.127 + elif self.cycle == 2:
2.128
2.129 - # Either read from a required address or transfer CPU data.
2.130 + # Either assert a required address or propagate the CPU address.
2.131
2.132 if self.access_ram():
2.133 - self.data = self.ram.data << 4
2.134 + self.init_row_address(self.pixel_address)
2.135 + else:
2.136 + self.init_row_address(self.cpu_address)
2.137 +
2.138 + # Latch row address, set column address (for RAM access only).
2.139 +
2.140 + elif self.cycle == 4:
2.141 +
2.142 + # Either assert a required address or propagate the CPU address.
2.143 +
2.144 + if self.access_ram():
2.145 + self.init_column_address(self.pixel_address, 0)
2.146 else:
2.147 - self.cpu_transfer_high()
2.148 + self.init_column_address(self.cpu_address, 0)
2.149 +
2.150 + # Set column address (for RAM access only).
2.151 +
2.152 + elif self.cycle == 32:
2.153
2.154 - # Read 4 bits (for ULA access only).
2.155 + # Either assert a required address or propagate the CPU address.
2.156 +
2.157 + if self.access_ram():
2.158 + self.init_column_address(self.pixel_address, 1)
2.159 + else:
2.160 + self.init_column_address(self.cpu_address, 1)
2.161 +
2.162 + # Update addresses.
2.163
2.164 elif self.cycle == 128:
2.165
2.166 - # Either read from a required address or transfer CPU data.
2.167 + # Advance to the next column even if an NMI is asserted.
2.168 +
2.169 + if self.would_access_ram():
2.170 + self.next_horizontal()
2.171 +
2.172 + # If the ULA accessed RAM, indicate that a read needs completing.
2.173
2.174 if self.access_ram():
2.175 - self.data = self.data | self.ram.data
2.176 self.have_pixels = 1
2.177 - else:
2.178 - self.cpu_transfer_low()
2.179
2.180 # Start a new cycle.
2.181