1.1 --- a/ula.py Thu May 03 01:28:46 2012 +0200
1.2 +++ b/ula.py Mon Oct 29 22:55:13 2012 +0100
1.3 @@ -83,10 +83,10 @@
1.4
1.5 """
1.6 A class representing the RAM circuits (IC4 to IC7). Each circuit
1.7 - traditionally holds 64 kilobits, with two accesses required to read 2 bits
1.8 - from each in order to obtain a whole byte. Here, we model the circuits with
1.9 - a list of 65536 half-bytes with each bit representing a bit stored on a
1.10 - separate IC.
1.11 + traditionally holds 64 kilobits, with each access obtaining 1 bit from each
1.12 + IC, and thus two accesses being required to obtain a whole byte. Here, we
1.13 + model the circuits with a list of 65536 half-bytes with each bit in a
1.14 + half-byte representing a bit stored on a separate IC.
1.15 """
1.16
1.17 def __init__(self):