1.1 --- a/ula.py Sun Nov 17 01:00:40 2013 +0100
1.2 +++ b/ula.py Sat Feb 01 17:55:57 2014 +0100
1.3 @@ -127,6 +127,33 @@
1.4 self.memory[i << 1] = value >> 4
1.5 self.memory[i << 1 | 0x1] = value & 0xf
1.6
1.7 +class ShiftRegister:
1.8 +
1.9 + """
1.10 + A class representing a shift register, used for the internal state of the
1.11 + ULA within each 2MHz period.
1.12 + """
1.13 +
1.14 + def __init__(self):
1.15 + self.state = [0] * 8
1.16 + self.input = 0
1.17 +
1.18 + def set_input(self, input):
1.19 + self.input = input
1.20 +
1.21 + def shift(self):
1.22 +
1.23 + # NOTE: This is not meant to be "nice" Python, but instead models the
1.24 + # NOTE: propagation of state through the latches.
1.25 +
1.26 + self.state[0], self.state[1], self.state[2], self.state[3], \
1.27 + self.state[4], self.state[5], self.state[6], self.state[7] = \
1.28 + self.input, self.state[0], self.state[1], self.state[2], \
1.29 + self.state[3], self.state[4], self.state[5], self.state[6]
1.30 +
1.31 + def __getitem__(self, i):
1.32 + return self.state[i]
1.33 +
1.34 class ULA:
1.35
1.36 """
1.37 @@ -172,13 +199,16 @@
1.38
1.39 # Internal state.
1.40
1.41 - self.cycle = [0]*8 # counter within each 2MHz period represented by 8 latches
1.42 self.access = 0 # counter used to determine whether a byte needs reading
1.43 self.have_pixels = 0 # whether pixel data has been read
1.44 self.writing_pixels = 0 # whether pixel data can be written
1.45 self.buffer = [BLANK]*8 # pixel buffer for decoded RAM data
1.46
1.47 - self.cycle[7] = 1 # assert the final latch (asserting the first on update)
1.48 + self.cycle = ShiftRegister() # 8-state counter within each 2MHz period
1.49 +
1.50 + self.cycle.set_input(1) # assert the input to set the first state output
1.51 + self.cycle.shift()
1.52 + self.cycle.set_input(0) # reset the input since only one state output will be active
1.53
1.54 self.reset_vertical()
1.55
1.56 @@ -322,15 +352,6 @@
1.57
1.58 access_ram = not self.nmi and self.access == 0 and self.read_pixels() and not self.ssub
1.59
1.60 - # Update the state of the device.
1.61 - # NOTE: This is not meant to be "nice" Python, but instead models the
1.62 - # NOTE: propagation of state through the latches.
1.63 -
1.64 - self.cycle[0], self.cycle[1], self.cycle[2], self.cycle[3], \
1.65 - self.cycle[4], self.cycle[5], self.cycle[6], self.cycle[7] = \
1.66 - self.cycle[7], self.cycle[0], self.cycle[1], self.cycle[2], \
1.67 - self.cycle[3], self.cycle[4], self.cycle[5], self.cycle[6]
1.68 -
1.69 # Set row address (for ULA access only).
1.70
1.71 if self.cycle[0]:
1.72 @@ -433,6 +454,11 @@
1.73
1.74 self.access = (self.access + 1) % self.access_frequency
1.75
1.76 + # Update the state of the device.
1.77 +
1.78 + self.cycle.set_input(self.cycle[7])
1.79 + self.cycle.shift()
1.80 +
1.81
1.82
1.83 # Video signalling.