1.1 --- a/ULA.txt Sun Feb 24 01:55:30 2019 +0100
1.2 +++ b/ULA.txt Tue Apr 09 00:49:32 2019 +0200
1.3 @@ -4,15 +4,17 @@
1.4 Principal Design and Feature Constraints
1.5 ----------------------------------------
1.6
1.7 -The features of the ULA are limited by the amount of time and resources that
1.8 -can be allocated to each activity necessary to support such features given the
1.9 -fundamental obligations of the unit. Maintaining a screen display based on the
1.10 -contents of RAM itself requires the ULA to have exclusive access to such
1.11 -hardware resources for a significant period of time. Whilst other elements of
1.12 -the ULA can in principle run in parallel with this activity, they cannot also
1.13 -access the RAM. Consequently, other features that might use the RAM must
1.14 -accept a reduced allocation of that resource in comparison to a hypothetical
1.15 -architecture where concurrent RAM access is possible.
1.16 +The features of the ULA are limited in sophistication by the amount of time
1.17 +and resources that can be allocated to each activity supporting the
1.18 +fundamental features and obligations of the unit. Maintaining a screen display
1.19 +based on the contents of RAM itself requires the ULA to have exclusive access
1.20 +to various hardware resources for a significant period of time.
1.21 +
1.22 +Whilst other elements of the ULA can in principle run in parallel with the
1.23 +display refresh activity, they cannot also access the RAM at the same time.
1.24 +Consequently, other features that might use the RAM must accept a reduced
1.25 +allocation of that resource in comparison to a hypothetical architecture where
1.26 +concurrent RAM access is possible at all times.
1.27
1.28 Thus, the principal constraint for many features is bandwidth. The duration of
1.29 access to hardware resources is one aspect of this; the rate at which such
1.30 @@ -22,6 +24,20 @@
1.31 for anything other than the production of pixel output during the active
1.32 scanline periods.
1.33
1.34 +Another constraint is imposed by the method of RAM access provided by the ULA.
1.35 +The ULA is able to access RAM by fetching 4 bits at a time and thus managing
1.36 +to transfer 8 bits within a single 2MHz cycle, this being sufficient to
1.37 +provide display data for the most demanding screen modes. However, this
1.38 +mechanism's timing requirements are beyond the capabilities of the CPU when
1.39 +running at 2MHz.
1.40 +
1.41 +Consequently, the CPU will only ever be able to access RAM via the ULA at
1.42 +1MHz, even when the ULA is not accessing the RAM. Fortunately, when needing to
1.43 +refresh the display, the ULA is still able to make use of the idle part of
1.44 +each 1MHz cycle (or, rather, the idle 2MHz cycle unused by the CPU) to itself
1.45 +access the RAM at a rate of 1 byte per 1MHz cycle (or 1 byte every other 2MHz
1.46 +cycle), thus supporting the less demanding screen modes.
1.47 +
1.48 Timing
1.49 ------
1.50