1.1 --- a/Electron.txt Tue Nov 26 15:38:07 2019 +0100
1.2 +++ b/Electron.txt Tue Apr 07 21:31:19 2020 +0200
1.3 @@ -88,6 +88,15 @@
1.4 peripheral would maintain its own framebuffer by registering writes on the bus
1.5 to the display memory region.
1.6
1.7 +Of course, the economic considerations related to the choice of RAM products
1.8 +could be revisited, reviewing the assumption that the products chosen would
1.9 +have significantly lowered the total production cost. This might indicate that
1.10 +different choices would have been viable. For example, instead of employing
1.11 +1-bit RAM chips in groups of four, perhaps two such groups might have been
1.12 +employed, with the resulting memory architecture being simplified and the
1.13 +corresponding component cost increase proving to be less than projections made
1.14 +early in the design process.
1.15 +
1.16 Improving Display Capabilities
1.17 ------------------------------
1.18
2.1 --- a/ULA.txt Tue Nov 26 15:38:07 2019 +0100
2.2 +++ b/ULA.txt Tue Apr 07 21:31:19 2020 +0200
2.3 @@ -640,14 +640,14 @@
2.4
2.5 This would improve CPU bandwidth as follows:
2.6
2.7 - Standard ULA Enhanced ULA
2.8 -MODE 0, 1, 2 9728 bytes 19456 bytes
2.9 -MODE 3 12288 bytes 24576 bytes
2.10 -MODE 4, 5 19968 bytes 29696 bytes
2.11 -MODE 6 19968 bytes 32256 bytes
2.12 + Standard ULA Enhanced ULA % Total Bandwidth Speedup
2.13 +MODE 0, 1, 2 9728 bytes 19456 bytes 24% -> 49% 2
2.14 +MODE 3 12288 bytes 24576 bytes 31% -> 62% 2
2.15 +MODE 4, 5 19968 bytes 29696 bytes 50% -> 74% 1.5
2.16 +MODE 6 19968 bytes 32256 bytes 50% -> 81% 1.6
2.17
2.18 -(Here, the uncontended 2MHz bandwidth for a display period would be 39936
2.19 -bytes, being 128 cycles per line over 312 lines.)
2.20 +(Here, the uncontended total 2MHz bandwidth for a display period would be
2.21 +39936 bytes, being 128 cycles per line over 312 lines.)
2.22
2.23 With such an enhancement, MODE 0 to 3 experience a doubling of CPU bandwidth
2.24 because all access opportunities to RAM are doubled. Meanwhile, in the other
2.25 @@ -656,7 +656,12 @@
2.26
2.27 Unfortunately, the mechanism for accessing the RAM is too slow to provide data
2.28 within the time constraints of 2MHz operation. There is no time remaining in a
2.29 -2MHz cycle for the CPU to receive and process any retrieved data.
2.30 +2MHz cycle for the CPU to receive and process any retrieved data once the
2.31 +necessary signalling has been performed. The only way for the CPU to be able
2.32 +to access the RAM quickly enough would be to do away with the double 4-bit
2.33 +access mechanism and to have a single 8-bit channel to the memory. This would
2.34 +require twice as many 1-bit RAM chips or a different kind of RAM chip, but it
2.35 +would also potentially simplify the ULA.
2.36
2.37 Enhancement: Region Blanking
2.38 ----------------------------