1.1 --- a/ULA.txt Mon Jun 20 23:40:11 2016 +0200
1.2 +++ b/ULA.txt Tue Jun 21 14:34:11 2016 +0200
1.3 @@ -48,26 +48,33 @@
1.4 Each 16MHz cycle is approximately 62.5ns. To access the memory, the following
1.5 patterns corresponding to 16MHz cycles are required:
1.6
1.7 - Time (ns): 0-------------- 500------------ ...
1.8 - 2 MHz cycle: 0 1 ...
1.9 - 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
1.10 - ~RAS: 0 1 0 1 ...
1.11 - ~CAS: 0 1 0 1 0 1 0 1 ...
1.12 - A B C A B C ...
1.13 - F S F S ...
1.14 - a b c a b c ...
1.15 + Time (ns): 0-------------- 500------------- ...
1.16 + 2 MHz cycle: 0 1 ...
1.17 + 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
1.18 + /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ ...
1.19 + ~RAS: --\___________/---\___________/- ...
1.20 + ~CAS: ----\___/-\___/-----\___/-\___/- ...
1.21 + A B C A B C ...
1.22 + F S F S ...
1.23 + a b c a b c ...
1.24 + f s f s ...
1.25
1.26 - ~WE: ......W ...
1.27 - PHI OUT: ______________/---------------\ ...
1.28 - CPU: D L ...
1.29 - RnW: R ...
1.30 + ~WE: ......W ...
1.31 + PHI OUT: ______________/---------------\ ...
1.32 + CPU (RAM): D L ...
1.33 + RnW: R ...
1.34 +
1.35 + PHI OUT: ______/-------\_______/-------\ ...
1.36 + CPU (ROM): D L D L ...
1.37 + RnW: R R ...
1.38
1.39 Here, "A" and "B" respectively indicate the row and first column addresses
1.40 being latched into the RAM (on a negative edge for ~RAS and ~CAS
1.41 respectively), and "C" indicates the second column address being latched into
1.42 the RAM. Presumably, the first and second half-bytes can be read at "F" and
1.43 "S" respectively, and the row and column addresses must be made available at
1.44 -"a" and "b" (and "c") respectively at the latest.
1.45 +"a" and "b" (and "c") respectively at the latest. Data can be read at "f" and
1.46 +"s" for the first and second half-bytes respectively.
1.47
1.48 For the CPU, "L" indicates the point at which an address is taken from the CPU
1.49 address bus, on a negative edge of PHI OUT, with "D" being the point at which
1.50 @@ -79,9 +86,11 @@
1.51 brought low.
1.52
1.53 The TM4164EC4-15 has a row address access time of 150ns (maximum) and a column
1.54 -address access time of 90ns (maximum), which appears to mean that
1.55 -approximately two 16MHz cycles after the row address is latched, and one and a
1.56 -half cycles after the column address is latched, the data becomes available.
1.57 +address access time of 90ns (maximum), which appears to mean that ~RAS must be
1.58 +held low for at least 150ns and that ~CAS must be held low for at least 90ns
1.59 +before data becomes available. 150ns is 2.4 cycles (at 16MHz) and 90ns is 1.44
1.60 +cycles. Thus, "A" to "F" is 2.5 cycles, "B" to "F" is 1.5 cycles, "C" to "S"
1.61 +is 1.5 cycles.
1.62
1.63 Note that the Service Manual refers to the negative edge of RAS and CAS, but
1.64 the datasheet for the similar TM4164EC4 product shows latching on the negative
2.1 --- a/ula.py Mon Jun 20 23:40:11 2016 +0200
2.2 +++ b/ula.py Tue Jun 21 14:34:11 2016 +0200
2.3 @@ -417,16 +417,7 @@
2.4 else:
2.5 self.cpu_transfer_select()
2.6
2.7 - # Read 4 bits (for ULA access only).
2.8 -
2.9 - elif self.cycle == 8:
2.10 -
2.11 - # Either read from a required address or transfer CPU data.
2.12 -
2.13 - if access_ram:
2.14 - self.data = self.ram.data << 4
2.15 - else:
2.16 - self.cpu_transfer_high()
2.17 + # Cycle handled in negedge.
2.18
2.19 # Set column address (for ULA access only).
2.20
2.21 @@ -452,14 +443,6 @@
2.22
2.23 elif self.cycle == 64:
2.24
2.25 - # Either read from a required address or transfer CPU data.
2.26 -
2.27 - if access_ram:
2.28 - self.data = self.data | self.ram.data
2.29 - self.have_pixels = 1
2.30 - else:
2.31 - self.cpu_transfer_low()
2.32 -
2.33 # Advance to the next column even if an NMI is asserted.
2.34
2.35 if would_access_ram:
2.36 @@ -502,12 +485,44 @@
2.37
2.38 def negedge(self):
2.39
2.40 - "Update the state of the device."
2.41 + """
2.42 + Update the state of the device.
2.43 +
2.44 + Cycles handled: _ _ _ * _ _ * *
2.45 + """
2.46 +
2.47 + # Clock management.
2.48 +
2.49 + would_access_ram = self.access == 0 and self.read_pixels() and self.in_line()
2.50 + access_ram = not self.nmi and would_access_ram
2.51 +
2.52 + # Read 4 bits (for ULA access only).
2.53 +
2.54 + if self.cycle == 8:
2.55 +
2.56 + # Either read from a required address or transfer CPU data.
2.57 +
2.58 + if access_ram:
2.59 + self.data = self.ram.data << 4
2.60 + else:
2.61 + self.cpu_transfer_high()
2.62 +
2.63 + # Read 4 bits (for ULA access only).
2.64 +
2.65 + elif self.cycle == 64:
2.66 +
2.67 + # Either read from a required address or transfer CPU data.
2.68 +
2.69 + if access_ram:
2.70 + self.data = self.data | self.ram.data
2.71 + self.have_pixels = 1
2.72 + else:
2.73 + self.cpu_transfer_low()
2.74
2.75 # Initialise the pixel buffer if appropriate. Output starts after
2.76 # this cycle.
2.77
2.78 - if self.cycle == 128 and self.have_pixels:
2.79 + elif self.cycle == 128 and self.have_pixels:
2.80 self.pdata = decode(self.data, self.depth)
2.81 self.pcycle = 1
2.82 self.have_pixels = 0