1.1 --- a/ULA.txt Wed Sep 30 01:47:16 2015 +0200
1.2 +++ b/ULA.txt Mon Oct 12 16:36:54 2015 +0200
1.3 @@ -975,8 +975,8 @@
1.4 as RAM-resident hardware sprites or indeed any feature demanding RAM access
1.5 concurrent with the production of the display image.
1.6
1.7 -Enhancement: Multiple CPU Stacks
1.8 ---------------------------------
1.9 +Enhancement: Multiple CPU Stacks and Zero Pages
1.10 +-----------------------------------------------
1.11
1.12 The 6502 maintains a stack for subroutine calls and register storage in page
1.13 &01. Although the stack register can be manipulated using the TSX and TXS
1.14 @@ -1000,6 +1000,19 @@
1.15 appropriate stack location, thus providing a simple memory management unit
1.16 (MMU) capability.
1.17
1.18 +In a similar fashion, zero page accesses could also be redirected so that code
1.19 +could run from sideways RAM and have zero page operations redirected to "upper
1.20 +memory" - for example, to page &BE (with stack accesses redirected to page
1.21 +&BF, perhaps) - thereby permitting most CPU operations to occur without
1.22 +inadvertent accesses to "lower memory" (the RAM) which would risk stalling the
1.23 +CPU as it contends with the ULA for memory access.
1.24 +
1.25 +Such facilities could also be provided by a separate circuit between the CPU
1.26 +and ULA in a fashion similar to that employed by a "turbo" board, but unlike
1.27 +such boards, no additional RAM would be provided: all memory accesses would
1.28 +occur as normal through the ULA, albeit redirected when configured
1.29 +appropriately.
1.30 +
1.31 ULA Pin Functions
1.32 -----------------
1.33