1.1 --- a/ULA.txt Fri Dec 31 15:12:51 2021 +0100
1.2 +++ b/ULA.txt Wed Mar 02 16:42:40 2022 +0100
1.3 @@ -239,6 +239,102 @@
1.4 bytes for every pair of cycles (2 bytes for the ULA, 1 byte for the CPU), and
1.5 thus 1.5 bytes per cycle, giving an illusion of 3MHz access to RAM.
1.6
1.7 +Some other considerations apply to introducing 8-bit wide access. The ULA
1.8 +employs four pins for data transfer to and from the memory devices (RAM0..3),
1.9 +and obviously another four pins would be needed in an 8-bit wide scheme.
1.10 +However, there may have been a physical limitation on the number of pins
1.11 +permissible on a ULA package or the device's socket. This would necessitate
1.12 +the reassignment of pins, although few are readily available for such
1.13 +reassignment.
1.14 +
1.15 +One approach might involve connecting the RAM devices to the CPU data bus,
1.16 +with each line connecting to a different RAM chip. The signalling of the RAM
1.17 +would remain under the control of the ULA, thus preventing the RAM devices
1.18 +from interfering with other memory transfer operations, with the ROM
1.19 +signalling also remaining under the ULA's control. One potential disadvantage
1.20 +of this scheme would involve the elimination of the separate data paths
1.21 +between the CPU and ROM and between the ULA and RAM.
1.22 +
1.23 +Another approach might involve reclaiming the keyboard input pins (KBD0..3) as
1.24 +data pins for ULA access to RAM. This would necessitate the reorganisation of
1.25 +the keyboard interface, perhaps integrating the keyboard matrix more directly
1.26 +as a kind of ROM device. A bus transceiver could be used to isolate the
1.27 +keyboard inputs, with a pin being used to control the transceiver, since the
1.28 +keyboard data lines are pulled high. In effect, the transceiver would act as a
1.29 +kind of output enable for the keyboard.
1.30 +
1.31 +To make the matrix appear within the sideways ROM region of the memory map,
1.32 +A15 would need to be set to a high value and A14 to a low value. Signals A13
1.33 +to A0 would then be brought low to select the appropriate column, with the
1.34 +individual key states being made available via data lines, perhaps D3 to D0.
1.35 +This mostly retains the existing addressing arrangement and scanning
1.36 +mechanism. Internally, the ULA would continue to enable access to the keyboard
1.37 +through the ROM paging mechanism, but instead of integrating separate data
1.38 +pins into the CPU's data path, it would integrate the keyboard inputs using
1.39 +the transceiver.
1.40 +
1.41 +Enhancement: Keyboard Matrix Scanning
1.42 +-------------------------------------
1.43 +
1.44 +The keyboard scanning mechanism is presumably designed to be as inexpensive as
1.45 +possible, being driven by software and avoiding extra logic, but at the
1.46 +expense of occupying large regions of the memory map when paged in. A more
1.47 +efficient mapping of the keyboard columns could possibly be done using
1.48 +decoders such as the 74xx138 part which permits the decoding of three inputs
1.49 +to select one of eight outputs. Using two of these parts, six address lines
1.50 +would be dedicated to the keyboard columns as follows:
1.51 +
1.52 + A5...A3 select up to eight columns via one decoder
1.53 + A2...A0 select up to eight columns via another decoder
1.54 +
1.55 +In this arrangement, only one of the two ranges of pins would be used at any
1.56 +given time. If the ULA were to require a certain combination of the remaining
1.57 +address bits, a region as small as 64 bytes could be dedicated to the
1.58 +keyboard.
1.59 +
1.60 +A more efficient arrangement could be used by introducing logic that allows
1.61 +the decoders to work together to address the keyboard:
1.62 +
1.63 + A2...A0 select up to eight columns via both decoders
1.64 + A3 would enable one decoder if low and the other decoder if high
1.65 +
1.66 +With ULA constraints on the remaining address bits, a 16-byte region could be
1.67 +used to represent the keyboard.
1.68 +
1.69 +A further refinement might involve combining the existing columns into groups
1.70 +of eight keys. This would reduce the number of columns to seven, requiring
1.71 +only three address lines, with all eight data lines being used to read the
1.72 +matrix.
1.73 +
1.74 +On the BBC Micro, the system 6522 VIA is used to monitor and read from the
1.75 +keyboard. The memory locations involved with this chip are located in the
1.76 +region from &FE40 to &FE7F inclusive, although the memory is allocated in a
1.77 +way that is appropriate to operate that chip, as opposed to merely exposing
1.78 +the keyboard matrix.
1.79 +
1.80 +Enhancement: Hardware Device Selection
1.81 +--------------------------------------
1.82 +
1.83 +An alternative to the existing, rather cumbersome, sideways ROM mapping of the
1.84 +keyboard might involve making it accessible via a hardware-related memory page
1.85 +like page FE. With ULA addresses confined to FE0x, and with the ULA itself
1.86 +having to trap accesses to page FE, the page selection signal might be brought
1.87 +out of the ULA instead of any dedicated signal for the keyboard. Various
1.88 +address lines corresponding to A7 through A4, or a subset of these, could be
1.89 +fed into a decoder to permit the selection of other devices, with the keyboard
1.90 +being one of these.
1.91 +
1.92 +Meanwhile, a more efficient keyboard mapping using the above matrix
1.93 +enhancement would permit the different keyboard columns to appear as a group
1.94 +of sixteen or eight bytes. Thus:
1.95 +
1.96 + A15...A8 select page FE
1.97 + A7...A4 select a device or peripheral
1.98 + A3...A0 select a register or keyboard column
1.99 +
1.100 +Conceivably, devices such as sound generators could be mapped to device
1.101 +regions.
1.102 +
1.103 CPU Clock Notes
1.104 ---------------
1.105