ULA

Changeset

120:b3383787c26f
2020-04-12 Paul Boddie raw files shortlog changelog graph Added more remarks, particularly regarding direct CPU access to RAM.
Electron.txt (file) ULA.txt (file)
     1.1 --- a/Electron.txt	Tue Apr 07 22:13:13 2020 +0200
     1.2 +++ b/Electron.txt	Sun Apr 12 17:05:08 2020 +0200
     1.3 @@ -98,7 +98,7 @@
     1.4  cycles instead of 16MHz to coordinate signalling, potentially reducing power
     1.5  consumption and increasing yield and reliability), and the corresponding
     1.6  component cost increase proving to be less than projections made early in the
     1.7 -design process, particularly if slower RAM chips became usable.
     1.8 +design process, particularly if slower (and smaller) RAM chips became usable.
     1.9  
    1.10  Improving Display Capabilities
    1.11  ------------------------------
     2.1 --- a/ULA.txt	Tue Apr 07 22:13:13 2020 +0200
     2.2 +++ b/ULA.txt	Sun Apr 12 17:05:08 2020 +0200
     2.3 @@ -150,7 +150,7 @@
     2.4            ~RAS:  /---\___________/---\___________ ...
     2.5            ~CAS:  /-------\_______/-------\_______ ...
     2.6  Address events:      A   B           A   B        ...
     2.7 -   Data events:             F               F     ...
     2.8 +   Data events:             E               E     ...
     2.9  
    2.10        ~RAS ops:  1   0           1   0            ...
    2.11        ~CAS ops:  1       0       1       0        ...
    2.12 @@ -163,10 +163,17 @@
    2.13             CPU:  L       D       L       D        ...
    2.14             RnW:          R               R        ...
    2.15  
    2.16 +Here, "E" indicates the availability of an entire byte.
    2.17 +
    2.18  Since only one fetch is required per 2MHz cycle, instead of two fetches for
    2.19  the 4-bit wide RAM arrangement, it seems likely that longer 8MHz cycles could
    2.20  be used to coordinate the necessary signalling.
    2.21  
    2.22 +Another conceivable simplification from using an 8-bit wide RAM access channel
    2.23 +with a single access within each 2MHz cycle is the possibility of allowing the
    2.24 +CPU to signal directly to the RAM instead of having the ULA perform the access
    2.25 +signalling on the CPU's behalf.
    2.26 +
    2.27  CPU Clock Notes
    2.28  ---------------
    2.29