1.1 --- a/ULA.txt Sat Apr 05 00:36:04 2014 +0200
1.2 +++ b/ULA.txt Thu Oct 23 23:44:13 2014 +0200
1.3 @@ -275,6 +275,21 @@
1.4 be discharged from providing access to memory, potentially for a range of
1.5 addresses, and for the CPU to communicate with external memory uninterrupted.
1.6
1.7 +Sideways RAM/ROM and Upper Memory Access
1.8 +----------------------------------------
1.9 +
1.10 +Although the ULA controls the CPU clock, effectively slowing or stopping the
1.11 +CPU when the ULA needs to access screen memory, it is apparently able to allow
1.12 +the CPU to access addresses of &8000 and above - the upper region of memory -
1.13 +at 2MHz independently of any access to RAM that the ULA might be performing,
1.14 +only blocking the CPU if it attempts to access addresses of &7FFF and below
1.15 +during any ULA memory access - the lower region of memory - by stopping or
1.16 +stalling its clock.
1.17 +
1.18 +Thus, the ULA remains aware of the level of the A15 line, only inhibiting the
1.19 +CPU clock if the line goes low, when the CPU is attempting to access the lower
1.20 +region of memory.
1.21 +
1.22 Hardware Scrolling
1.23 ------------------
1.24
1.25 @@ -471,6 +486,10 @@
1.26 combined with other palette data in dedicated memory locations corresponding
1.27 to the palette registers.
1.28
1.29 +Interestingly, although flashing colours on the BBC Micro are controlled by
1.30 +toggling bit 0 of the &FE20 control register location for the Video ULA, the
1.31 +actual colour inversion is done in hardware.
1.32 +
1.33 Enhancement: Palette Definition Lists
1.34 -------------------------------------
1.35
1.36 @@ -880,6 +899,11 @@
1.37
1.38 ÷13 IN (~1200 baud clock input)
1.39
1.40 +ULA Socket
1.41 +----------
1.42 +
1.43 +The socket used for the ULA is a 3M/TexTool 268-5400 68-pin socket.
1.44 +
1.45 References
1.46 ----------
1.47