paul@0 | 1 | /* |
paul@0 | 2 | * Generate a VGA signal using a PIC32 microcontroller. |
paul@0 | 3 | * |
paul@0 | 4 | * Copyright (C) 2017 Paul Boddie <paul@boddie.org.uk> |
paul@0 | 5 | * |
paul@0 | 6 | * This program is free software: you can redistribute it and/or modify |
paul@0 | 7 | * it under the terms of the GNU General Public License as published by |
paul@0 | 8 | * the Free Software Foundation, either version 3 of the License, or |
paul@0 | 9 | * (at your option) any later version. |
paul@0 | 10 | * |
paul@0 | 11 | * This program is distributed in the hope that it will be useful, |
paul@0 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@0 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@0 | 14 | * GNU General Public License for more details. |
paul@0 | 15 | * |
paul@0 | 16 | * You should have received a copy of the GNU General Public License |
paul@0 | 17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
paul@0 | 18 | */ |
paul@0 | 19 | |
paul@0 | 20 | #include "mips.h" |
paul@0 | 21 | #include "pic32.h" |
paul@35 | 22 | #include "vga.h" |
paul@0 | 23 | |
paul@0 | 24 | /* Disable JTAG functionality on pins. */ |
paul@0 | 25 | |
paul@0 | 26 | .section .devcfg0, "a" |
paul@0 | 27 | .word 0xfffffffb /* DEVCFG0<2> = JTAGEN = 0 */ |
paul@0 | 28 | |
paul@0 | 29 | /* |
paul@0 | 30 | Set the oscillator to be the FRC oscillator with PLL, with peripheral clock |
paul@21 | 31 | divided by 2, and FRCDIV+PLL selected. |
paul@0 | 32 | |
paul@0 | 33 | The watchdog timer (FWDTEN) is also disabled. |
paul@9 | 34 | |
paul@54 | 35 | The primary oscillator is configured to provide an external clock and CLKO |
paul@54 | 36 | output is enabled. |
paul@54 | 37 | |
paul@9 | 38 | The secondary oscillator pin (FSOSCEN) is disabled to avoid pin conflicts with |
paul@9 | 39 | RPB4. |
paul@0 | 40 | */ |
paul@0 | 41 | |
paul@0 | 42 | .section .devcfg1, "a" |
paul@55 | 43 | .word 0xff7fdfd9 /* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 1; |
paul@9 | 44 | DEVCFG1<5> = FSOSCEN = 0; DEVCFG1<2:0> = FNOSC<2:0> = 001 */ |
paul@0 | 45 | |
paul@0 | 46 | /* |
paul@0 | 47 | Set the FRC oscillator PLL function with an input division of 4, an output |
paul@21 | 48 | division of 2, a multiplication of 24, yielding a multiplication of 3. |
paul@21 | 49 | |
paul@21 | 50 | The FRC is apparently at 16MHz and this produces a system clock of 48MHz. |
paul@0 | 51 | */ |
paul@0 | 52 | |
paul@0 | 53 | .section .devcfg2, "a" |
paul@21 | 54 | .word 0xfff9fffb /* DEVCFG2<18:16> = FPLLODIV<2:0> = 001; |
paul@21 | 55 | DEVCFG2<6:4> = FPLLMUL<2:0> = 111; |
paul@9 | 56 | DEVCFG2<2:0> = FPLLIDIV<2:0> = 011 */ |
paul@0 | 57 | |
paul@0 | 58 | .text |
paul@0 | 59 | .globl _start |
paul@36 | 60 | .extern init_framebuffer |
paul@35 | 61 | .extern init_framebuffer_with_pattern |
paul@41 | 62 | .extern screendata |
paul@41 | 63 | .extern fontdata |
paul@41 | 64 | .extern blit_string |
paul@41 | 65 | .extern message |
paul@0 | 66 | |
paul@0 | 67 | _start: |
paul@0 | 68 | /* |
paul@0 | 69 | Configure RAM. |
paul@0 | 70 | See: http://microchipdeveloper.com/32bit:mx-arch-exceptions-processor-initialization |
paul@0 | 71 | */ |
paul@0 | 72 | |
paul@0 | 73 | la $v0, BMXCON |
paul@10 | 74 | lw $v1, 0($v0) |
paul@48 | 75 | |
paul@48 | 76 | /* Set zero wait states for address setup. */ |
paul@48 | 77 | |
paul@10 | 78 | li $t8, ~(1 << 6) /* BMXCON<6> = BMXWSDRM = 0 */ |
paul@10 | 79 | and $v1, $v1, $t8 |
paul@48 | 80 | |
paul@48 | 81 | /* Set bus arbitration mode. */ |
paul@48 | 82 | |
paul@10 | 83 | li $t8, ~0b111 /* BMXCON<2:0> = BMXARB<2:0> = 0 */ |
paul@10 | 84 | ori $t8, $t8, 0b010 /* BMXCON<2:0> = BMXARB<2:0> = 2 */ |
paul@10 | 85 | and $v1, $v1, $t8 |
paul@10 | 86 | sw $v1, 0($v0) |
paul@0 | 87 | |
paul@0 | 88 | /* Enable caching. */ |
paul@0 | 89 | |
paul@14 | 90 | mfc0 $v1, CP0_CONFIG |
paul@14 | 91 | li $t8, ~CONFIG_K0 |
paul@14 | 92 | and $v1, $v1, $t8 |
paul@14 | 93 | ori $v1, $v1, CONFIG_K0_CACHABLE_NONCOHERENT |
paul@14 | 94 | mtc0 $v1, CP0_CONFIG |
paul@0 | 95 | nop |
paul@0 | 96 | |
paul@0 | 97 | /* Get the RAM size. */ |
paul@0 | 98 | |
paul@3 | 99 | la $v0, BMXDRMSZ |
paul@18 | 100 | lw $t0, 0($v0) |
paul@0 | 101 | |
paul@0 | 102 | /* Initialise the stack pointer. */ |
paul@0 | 103 | |
paul@3 | 104 | li $v1, KSEG0_BASE |
paul@18 | 105 | addu $sp, $t0, $v1 /* sp = KSEG0_BASE + RAM size */ |
paul@9 | 106 | |
paul@0 | 107 | /* Initialise the globals pointer. */ |
paul@0 | 108 | |
paul@0 | 109 | lui $gp, %hi(_GLOBAL_OFFSET_TABLE_) |
paul@0 | 110 | ori $gp, $gp, %lo(_GLOBAL_OFFSET_TABLE_) |
paul@0 | 111 | |
paul@5 | 112 | /* Set pins for output. */ |
paul@0 | 113 | |
paul@0 | 114 | jal init_pins |
paul@0 | 115 | nop |
paul@0 | 116 | |
paul@15 | 117 | la $t0, PORTA |
paul@15 | 118 | li $t1, (1 << 3) /* PORTA<3> = RA3 */ |
paul@15 | 119 | sw $t1, CLR($t0) |
paul@15 | 120 | |
paul@54 | 121 | jal init_io_pins |
paul@5 | 122 | nop |
paul@5 | 123 | |
paul@55 | 124 | jal init_refclk_pins |
paul@55 | 125 | nop |
paul@55 | 126 | |
paul@0 | 127 | /* Initialise the status register. */ |
paul@0 | 128 | |
paul@0 | 129 | jal init_interrupts |
paul@0 | 130 | nop |
paul@0 | 131 | |
paul@18 | 132 | /* Initialise framebuffer. */ |
paul@18 | 133 | |
paul@36 | 134 | la $a0, screendata |
paul@36 | 135 | jal init_framebuffer |
paul@18 | 136 | nop |
paul@18 | 137 | |
paul@18 | 138 | sync |
paul@18 | 139 | |
paul@0 | 140 | /* Initialise timer. */ |
paul@0 | 141 | |
paul@4 | 142 | jal init_timer2 |
paul@0 | 143 | nop |
paul@0 | 144 | |
paul@3 | 145 | /* Initialise DMA. */ |
paul@3 | 146 | |
paul@3 | 147 | jal init_dma |
paul@3 | 148 | nop |
paul@3 | 149 | |
paul@15 | 150 | /* Initialise OC1 and OC2. */ |
paul@5 | 151 | |
paul@9 | 152 | jal init_oc |
paul@3 | 153 | nop |
paul@3 | 154 | |
paul@34 | 155 | /* Initialise the display state. */ |
paul@34 | 156 | |
paul@34 | 157 | li $s0, 0 /* line counter */ |
paul@34 | 158 | la $s1, vbp_active /* current event */ |
paul@38 | 159 | li $s2, SCREEN_BASE /* line address */ |
paul@38 | 160 | li $s3, SCREEN_BASE /* screen address */ |
paul@38 | 161 | |
paul@38 | 162 | /* Save the state for retrieval in the interrupt handler. */ |
paul@38 | 163 | |
paul@38 | 164 | li $k0, IRQ_STACK_LIMIT |
paul@38 | 165 | sw $s0, -44($k0) |
paul@38 | 166 | sw $s1, -48($k0) |
paul@38 | 167 | sw $s2, -52($k0) |
paul@38 | 168 | sw $s3, -56($k0) |
paul@34 | 169 | |
paul@0 | 170 | /* Enable interrupts and loop. */ |
paul@0 | 171 | |
paul@0 | 172 | jal enable_interrupts |
paul@0 | 173 | nop |
paul@0 | 174 | |
paul@0 | 175 | jal handle_error_level |
paul@0 | 176 | nop |
paul@0 | 177 | |
paul@3 | 178 | /* Main program. */ |
paul@3 | 179 | |
paul@39 | 180 | li $a1, (3 << 24) /* counter ~= 50000000 */ |
paul@39 | 181 | li $a2, 0xffffff /* test counter at every 1/4 of range */ |
paul@39 | 182 | move $t2, $zero /* picture to show */ |
paul@3 | 183 | |
paul@3 | 184 | /* Monitoring loop. */ |
paul@0 | 185 | loop: |
paul@3 | 186 | addiu $a1, $a1, -1 /* counter -= 1 */ |
paul@39 | 187 | and $t1, $a2, $a1 |
paul@39 | 188 | bnez $t1, loop |
paul@0 | 189 | nop |
paul@0 | 190 | |
paul@15 | 191 | la $t0, PORTA |
paul@15 | 192 | li $t1, (1 << 3) /* PORTA<3> = RA3 */ |
paul@3 | 193 | sw $t1, INV($t0) |
paul@0 | 194 | |
paul@39 | 195 | bnez $a1, loop /* until counter == 0 */ |
paul@39 | 196 | nop |
paul@39 | 197 | |
paul@39 | 198 | bnez $t2, _picture1 |
paul@39 | 199 | nop |
paul@39 | 200 | |
paul@39 | 201 | /* Show picture 0. */ |
paul@39 | 202 | |
paul@39 | 203 | la $a0, screendata |
paul@39 | 204 | jal init_framebuffer |
paul@39 | 205 | nop |
paul@41 | 206 | |
paul@41 | 207 | la $a0, message0 |
paul@41 | 208 | li $a1, SCREEN_BASE_KSEG0 |
paul@41 | 209 | jal blit_string |
paul@41 | 210 | nop |
paul@41 | 211 | |
paul@39 | 212 | li $t2, 1 |
paul@39 | 213 | j _next |
paul@39 | 214 | nop |
paul@39 | 215 | |
paul@39 | 216 | _picture1: |
paul@39 | 217 | /* Show picture 1. */ |
paul@39 | 218 | |
paul@39 | 219 | jal init_framebuffer_with_pattern |
paul@39 | 220 | nop |
paul@41 | 221 | |
paul@41 | 222 | la $a0, message1 |
paul@41 | 223 | li $a1, SCREEN_BASE_KSEG0 |
paul@41 | 224 | jal blit_string |
paul@41 | 225 | nop |
paul@41 | 226 | |
paul@39 | 227 | move $t2, $zero |
paul@39 | 228 | |
paul@0 | 229 | _next: |
paul@39 | 230 | li $a1, (3 << 24) /* counter ~= 50000000 */ |
paul@39 | 231 | li $a2, 0xffffff /* test counter at every 1/4 of range */ |
paul@0 | 232 | j loop |
paul@0 | 233 | nop |
paul@0 | 234 | |
paul@0 | 235 | |
paul@0 | 236 | |
paul@0 | 237 | init_pins: |
paul@1 | 238 | /* DEVCFG0<2> needs setting to 0 before the program is run. */ |
paul@0 | 239 | |
paul@3 | 240 | la $v0, CFGCON |
paul@0 | 241 | li $v1, (1 << 3) /* CFGCON<3> = JTAGEN = 0 */ |
paul@0 | 242 | sw $v1, CLR($v0) |
paul@0 | 243 | |
paul@3 | 244 | init_outputs: |
paul@3 | 245 | /* Remove analogue features from pins. */ |
paul@3 | 246 | |
paul@3 | 247 | la $v0, ANSELA |
paul@3 | 248 | sw $zero, 0($v0) /* ANSELA = 0 */ |
paul@3 | 249 | la $v0, ANSELB |
paul@3 | 250 | sw $zero, 0($v0) /* ANSELB = 0 */ |
paul@3 | 251 | |
paul@3 | 252 | la $v0, TRISA |
paul@3 | 253 | sw $zero, 0($v0) |
paul@0 | 254 | la $v0, TRISB |
paul@3 | 255 | sw $zero, 0($v0) |
paul@3 | 256 | |
paul@9 | 257 | la $v0, PORTA |
paul@9 | 258 | sw $zero, 0($v0) |
paul@9 | 259 | la $v0, PORTB |
paul@9 | 260 | sw $zero, 0($v0) |
paul@0 | 261 | |
paul@3 | 262 | jr $ra |
paul@0 | 263 | nop |
paul@0 | 264 | |
paul@0 | 265 | |
paul@0 | 266 | |
paul@0 | 267 | /* Initialisation routines. */ |
paul@0 | 268 | |
paul@4 | 269 | init_timer2: |
paul@0 | 270 | |
paul@49 | 271 | /* Initialise Timer2 for sync pulses. */ |
paul@0 | 272 | |
paul@4 | 273 | la $v0, T2CON |
paul@4 | 274 | sw $zero, 0($v0) /* T2CON = 0 */ |
paul@0 | 275 | nop |
paul@0 | 276 | |
paul@4 | 277 | la $v0, TMR2 |
paul@4 | 278 | sw $zero, 0($v0) /* TMR2 = 0 */ |
paul@5 | 279 | |
paul@4 | 280 | la $v0, PR2 |
paul@0 | 281 | li $v1, HFREQ_LIMIT |
paul@4 | 282 | sw $v1, 0($v0) /* PR2 = HFREQ_LIMIT */ |
paul@0 | 283 | |
paul@4 | 284 | /* Initialise Timer2 interrupt. */ |
paul@0 | 285 | |
paul@0 | 286 | la $v0, IFS0 |
paul@4 | 287 | li $v1, (1 << 9) |
paul@5 | 288 | sw $v1, CLR($v0) /* T2IF = 0 */ |
paul@5 | 289 | |
paul@4 | 290 | la $v0, IPC2 |
paul@5 | 291 | li $v1, 0b11111 |
paul@5 | 292 | sw $v1, CLR($v0) /* T2IP, T2IS = 0 */ |
paul@5 | 293 | |
paul@4 | 294 | la $v0, IPC2 |
paul@5 | 295 | li $v1, 0b11111 |
paul@5 | 296 | sw $v1, SET($v0) /* T2IP = 7; T2IS = 3 */ |
paul@5 | 297 | |
paul@0 | 298 | la $v0, IEC0 |
paul@4 | 299 | li $v1, (1 << 9) |
paul@5 | 300 | sw $v1, SET($v0) /* T2IE = 1 */ |
paul@0 | 301 | |
paul@0 | 302 | /* Start timer. */ |
paul@0 | 303 | |
paul@4 | 304 | la $v0, T2CON |
paul@5 | 305 | li $v1, (1 << 15) |
paul@5 | 306 | sw $v1, SET($v0) /* ON = 1 */ |
paul@5 | 307 | |
paul@5 | 308 | jr $ra |
paul@5 | 309 | nop |
paul@5 | 310 | |
paul@5 | 311 | |
paul@5 | 312 | |
paul@5 | 313 | /* |
paul@5 | 314 | Output compare initialisation. |
paul@5 | 315 | |
paul@15 | 316 | Timer2 will be used to trigger two events using OC1: one initiating the hsync |
paul@9 | 317 | pulse, and one terminating the pulse. The pulse should appear after the line |
paul@9 | 318 | data has been transferred using DMA, but this is achieved by just choosing |
paul@9 | 319 | suitable start and end values. |
paul@5 | 320 | |
paul@49 | 321 | Using OC2, Timer2 triggers a level shifting event and OC2 is reconfigured to |
paul@48 | 322 | reverse the level at a later point. In this way, the vsync pulse is generated |
paul@48 | 323 | and is synchronised to the display lines. |
paul@5 | 324 | */ |
paul@5 | 325 | |
paul@9 | 326 | init_oc: |
paul@15 | 327 | /* Disable OC1 interrupts. */ |
paul@9 | 328 | |
paul@9 | 329 | la $v0, IEC0 |
paul@15 | 330 | li $v1, (1 << 7) /* IEC0<7> = OC1IE = 0 */ |
paul@9 | 331 | sw $v1, CLR($v0) |
paul@9 | 332 | |
paul@9 | 333 | la $v0, IFS0 |
paul@15 | 334 | li $v1, (1 << 7) /* IFS0<7> = OC1IF = 0 */ |
paul@9 | 335 | sw $v1, CLR($v0) |
paul@9 | 336 | |
paul@15 | 337 | /* Initialise OC1. */ |
paul@9 | 338 | |
paul@15 | 339 | la $v0, OC1CON |
paul@15 | 340 | li $v1, 0b101 /* OC1CON<2:0> = OCM<2:0> = 101 (dual compare, continuous pulse) */ |
paul@9 | 341 | sw $v1, 0($v0) |
paul@9 | 342 | |
paul@9 | 343 | /* Pulse start and end. */ |
paul@9 | 344 | |
paul@15 | 345 | la $v0, OC1R |
paul@9 | 346 | li $v1, HSYNC_END /* HSYNC_START for positive polarity */ |
paul@9 | 347 | sw $v1, 0($v0) |
paul@9 | 348 | |
paul@15 | 349 | la $v0, OC1RS |
paul@9 | 350 | li $v1, HSYNC_START /* HSYNC_END for positive polarity */ |
paul@9 | 351 | sw $v1, 0($v0) |
paul@9 | 352 | |
paul@15 | 353 | /* OC1 is enabled. */ |
paul@9 | 354 | |
paul@15 | 355 | la $v0, OC1CON |
paul@9 | 356 | li $v1, (1 << 15) |
paul@9 | 357 | sw $v1, SET($v0) |
paul@9 | 358 | |
paul@9 | 359 | /* Disable OC2 interrupts. */ |
paul@5 | 360 | |
paul@5 | 361 | la $v0, IEC0 |
paul@5 | 362 | li $v1, (1 << 12) /* IEC0<12> = OC2IE = 0 */ |
paul@5 | 363 | sw $v1, CLR($v0) |
paul@5 | 364 | |
paul@5 | 365 | la $v0, IFS0 |
paul@5 | 366 | li $v1, (1 << 12) /* IFS0<12> = OC2IF = 0 */ |
paul@5 | 367 | sw $v1, CLR($v0) |
paul@5 | 368 | |
paul@5 | 369 | /* Initialise OC2. */ |
paul@5 | 370 | |
paul@5 | 371 | la $v0, OC2CON |
paul@9 | 372 | li $v1, 0b010 /* OC2CON<2:0> = OCM<2:0> = 010 (single compare, output driven low) */ |
paul@5 | 373 | sw $v1, 0($v0) |
paul@5 | 374 | |
paul@9 | 375 | /* Set pulse position. */ |
paul@5 | 376 | |
paul@5 | 377 | la $v0, OC2R |
paul@9 | 378 | sw $zero, 0($v0) |
paul@5 | 379 | |
paul@9 | 380 | /* Enable OC2 later. */ |
paul@5 | 381 | |
paul@5 | 382 | jr $ra |
paul@5 | 383 | nop |
paul@5 | 384 | |
paul@54 | 385 | |
paul@54 | 386 | |
paul@55 | 387 | /* |
paul@55 | 388 | Clock output initialisation. The peripheral clock divided by 2 is output via the |
paul@55 | 389 | CLKO pin to drive a flip-flop. |
paul@55 | 390 | */ |
paul@55 | 391 | |
paul@55 | 392 | init_refclk_pins: |
paul@55 | 393 | /* Change the output clock frequency. */ |
paul@55 | 394 | |
paul@55 | 395 | la $v0, REFOCON |
paul@55 | 396 | li $v1, (0b1001001 << 9) |
paul@55 | 397 | sw $v1, SET($v0) /* REFOCON<15> = ON = 1; REFOCON<12> = OE = 1; REFOCON<9> = DIVSWEN = 1 */ |
paul@55 | 398 | |
paul@55 | 399 | _refclk_wait: |
paul@55 | 400 | lw $v1, 0($v0) |
paul@55 | 401 | andi $v1, $v1, (1 << 8) /* REFOCON<8> = ACTIVE */ |
paul@55 | 402 | bnez $v1, _refclk_wait |
paul@55 | 403 | nop |
paul@55 | 404 | |
paul@55 | 405 | li $v1, 0b1111 /* ROSEL<3:0> = 0000 */ |
paul@55 | 406 | sw $v1, CLR($v0) |
paul@55 | 407 | li $v1, 0b0001 /* ROSEL<3:0> = 0001 (PBCLK) */ |
paul@55 | 408 | sw $v1, SET($v0) |
paul@55 | 409 | |
paul@55 | 410 | /* |
paul@55 | 411 | The RODIV and ROTRIM values should be zero by default, yielding a |
paul@55 | 412 | frequency of half the input indicated by ROSEL. |
paul@55 | 413 | */ |
paul@55 | 414 | |
paul@55 | 415 | li $v1, (1 << 9) /* REFOCON<9> = DIVSWEN = 0 */ |
paul@55 | 416 | sw $v1, CLR($v0) |
paul@55 | 417 | |
paul@55 | 418 | jr $ra |
paul@55 | 419 | nop |
paul@55 | 420 | |
paul@55 | 421 | |
paul@55 | 422 | |
paul@54 | 423 | init_io_pins: |
paul@5 | 424 | /* Unlock the configuration register bits. */ |
paul@5 | 425 | |
paul@5 | 426 | la $v0, SYSKEY |
paul@5 | 427 | sw $zero, 0($v0) |
paul@5 | 428 | li $v1, 0xAA996655 |
paul@5 | 429 | sw $v1, 0($v0) |
paul@5 | 430 | li $v1, 0x556699AA |
paul@5 | 431 | sw $v1, 0($v0) |
paul@5 | 432 | |
paul@5 | 433 | la $v0, CFGCON |
paul@5 | 434 | lw $t8, 0($v0) |
paul@5 | 435 | li $v1, (1 << 13) /* IOLOCK = 0 */ |
paul@5 | 436 | sw $v1, CLR($v0) |
paul@5 | 437 | |
paul@15 | 438 | /* Map OC1 to RPA0. */ |
paul@9 | 439 | |
paul@15 | 440 | la $v0, RPA0R |
paul@15 | 441 | li $v1, 0b0101 /* RPA0R<3:0> = 0101 (OC1) */ |
paul@9 | 442 | sw $v1, 0($v0) |
paul@9 | 443 | |
paul@15 | 444 | /* Map OC2 to RPA1. */ |
paul@5 | 445 | |
paul@15 | 446 | la $v0, RPA1R |
paul@15 | 447 | li $v1, 0b0101 /* RPA1R<3:0> = 0101 (OC2) */ |
paul@5 | 448 | sw $v1, 0($v0) |
paul@5 | 449 | |
paul@54 | 450 | /* Map REFCLKO to RPA2. */ |
paul@54 | 451 | |
paul@54 | 452 | la $v0, RPA2R |
paul@54 | 453 | li $v1, 0b0111 /* RPA2R<3:0> = 0111 (REFCLKO) */ |
paul@54 | 454 | sw $v1, 0($v0) |
paul@54 | 455 | |
paul@54 | 456 | /* Restore CFGCON. */ |
paul@54 | 457 | |
paul@5 | 458 | la $v0, CFGCON |
paul@5 | 459 | sw $t8, 0($v0) |
paul@5 | 460 | |
paul@5 | 461 | /* Lock the oscillator control register again. */ |
paul@5 | 462 | |
paul@5 | 463 | la $v0, SYSKEY |
paul@5 | 464 | li $v1, 0x33333333 |
paul@5 | 465 | sw $v1, 0($v0) |
paul@0 | 466 | |
paul@0 | 467 | jr $ra |
paul@0 | 468 | nop |
paul@1 | 469 | |
paul@1 | 470 | |
paul@1 | 471 | |
paul@5 | 472 | /* |
paul@5 | 473 | Direct Memory Access initialisation. |
paul@3 | 474 | |
paul@15 | 475 | Write 160 pixels to PORTB for the line data. This is initiated by a timer |
paul@9 | 476 | interrupt. Upon completion of the transfer, a DMA interrupt initiates the |
paul@9 | 477 | address update routine, changing the source address of the DMA channel. |
paul@3 | 478 | */ |
paul@3 | 479 | |
paul@3 | 480 | init_dma: |
paul@3 | 481 | /* Disable DMA interrupts. */ |
paul@1 | 482 | |
paul@3 | 483 | la $v0, IEC1 |
paul@57 | 484 | li $v1, (0b111 << 28) /* IEC1<30:28> = DMA2IE, DMA1IE, DMA0IE = 0 */ |
paul@3 | 485 | sw $v1, CLR($v0) |
paul@3 | 486 | |
paul@3 | 487 | /* Clear DMA interrupt flags. */ |
paul@1 | 488 | |
paul@3 | 489 | la $v0, IFS1 |
paul@57 | 490 | li $v1, (0b111 << 28) /* IFS1<30:28> = DMA2IF, DMA1IF, DMA0IF = 0 */ |
paul@3 | 491 | sw $v1, CLR($v0) |
paul@3 | 492 | |
paul@3 | 493 | /* Enable DMA. */ |
paul@3 | 494 | |
paul@3 | 495 | la $v0, DMACON |
paul@3 | 496 | li $v1, (1 << 15) |
paul@1 | 497 | sw $v1, SET($v0) |
paul@1 | 498 | |
paul@3 | 499 | /* |
paul@58 | 500 | Initialise a start channel. |
paul@58 | 501 | The start channel will be channel 0 (x = 0). |
paul@3 | 502 | |
paul@3 | 503 | Specify a priority of 3: |
paul@3 | 504 | DCHxCON<1:0> = CHPRI<1:0> = 3 |
paul@3 | 505 | |
paul@15 | 506 | Auto-enable the channel: |
paul@3 | 507 | DCHxCON<4> = CHAEN = 1 |
paul@3 | 508 | */ |
paul@3 | 509 | |
paul@3 | 510 | la $v0, DCH0CON |
paul@3 | 511 | li $v1, 0b10011 |
paul@3 | 512 | sw $v1, 0($v0) |
paul@3 | 513 | |
paul@5 | 514 | /* |
paul@58 | 515 | Initialise line and level reset channels. |
paul@58 | 516 | The line channel will be channel 1 (x = 1). |
paul@58 | 517 | The reset channel will be channel 2 (x = 2). |
paul@15 | 518 | |
paul@15 | 519 | Specify a priority of 3: |
paul@15 | 520 | DCHxCON<1:0> = CHPRI<1:0> = 3 |
paul@15 | 521 | |
paul@15 | 522 | Chain the channel to channel 0: |
paul@15 | 523 | DCHxCON<5> = CHCHN = 1 |
paul@15 | 524 | |
paul@15 | 525 | Allow the channel to receive events when disabled: |
paul@15 | 526 | DCHxCON<6> = CHAED = 1 |
paul@15 | 527 | */ |
paul@15 | 528 | |
paul@15 | 529 | la $v0, DCH1CON |
paul@15 | 530 | li $v1, 0b1100011 |
paul@15 | 531 | sw $v1, 0($v0) |
paul@15 | 532 | |
paul@57 | 533 | la $v0, DCH2CON |
paul@57 | 534 | li $v1, 0b1100011 |
paul@57 | 535 | sw $v1, 0($v0) |
paul@57 | 536 | |
paul@15 | 537 | /* |
paul@5 | 538 | Initiate channel transfers when the initiating interrupt condition |
paul@5 | 539 | occurs: |
paul@9 | 540 | DCHxECON<15:8> = CHSIRQ<7:0> = timer 2 interrupt |
paul@11 | 541 | DCHxECON<4> = SIRQEN = 1 |
paul@20 | 542 | |
paul@20 | 543 | For now, however, prevent initiation by not setting SIRQEN. |
paul@5 | 544 | */ |
paul@3 | 545 | |
paul@3 | 546 | la $v0, DCH0ECON |
paul@20 | 547 | li $v1, (9 << 8) |
paul@3 | 548 | sw $v1, 0($v0) |
paul@1 | 549 | |
paul@3 | 550 | /* |
paul@58 | 551 | Initiate line channel transfer when channel 0 is finished: |
paul@58 | 552 | Initiate reset channel transfer when channel 1 is finished: |
paul@58 | 553 | DCHxECON<15:8> = CHSIRQ<7:0> = channel 0 or 1 interrupt |
paul@15 | 554 | DCHxECON<4> = SIRQEN = 1 |
paul@15 | 555 | */ |
paul@15 | 556 | |
paul@15 | 557 | la $v0, DCH1ECON |
paul@15 | 558 | li $v1, (60 << 8) | (1 << 4) |
paul@15 | 559 | sw $v1, 0($v0) |
paul@15 | 560 | |
paul@57 | 561 | la $v0, DCH2ECON |
paul@57 | 562 | li $v1, (61 << 8) | (1 << 4) |
paul@57 | 563 | sw $v1, 0($v0) |
paul@57 | 564 | |
paul@15 | 565 | /* |
paul@15 | 566 | The line channel has a cell size of the number bytes in a line: |
paul@9 | 567 | DCHxCSIZ<15:0> = CHCSIZ<15:0> = LINE_LENGTH |
paul@3 | 568 | */ |
paul@3 | 569 | |
paul@58 | 570 | la $v0, DCH1CSIZ |
paul@9 | 571 | li $v1, LINE_LENGTH |
paul@3 | 572 | sw $v1, 0($v0) |
paul@1 | 573 | |
paul@3 | 574 | /* |
paul@58 | 575 | The start and reset channels have a cell size of a single zero byte: |
paul@49 | 576 | DCHxCSIZ<15:0> = CHCSIZ<15:0> = 1 |
paul@15 | 577 | */ |
paul@15 | 578 | |
paul@15 | 579 | li $v1, 1 |
paul@58 | 580 | |
paul@58 | 581 | la $v0, DCH0CSIZ |
paul@15 | 582 | sw $v1, 0($v0) |
paul@15 | 583 | |
paul@57 | 584 | la $v0, DCH2CSIZ |
paul@57 | 585 | sw $v1, 0($v0) |
paul@57 | 586 | |
paul@15 | 587 | /* |
paul@11 | 588 | The source has a size identical to the cell size: |
paul@49 | 589 | DCHxSSIZ<15:0> = CHSSIZ<15:0> = LINE_LENGTH or 1 |
paul@3 | 590 | */ |
paul@3 | 591 | |
paul@58 | 592 | la $v0, DCH1SSIZ |
paul@9 | 593 | li $v1, LINE_LENGTH |
paul@3 | 594 | sw $v1, 0($v0) |
paul@3 | 595 | |
paul@15 | 596 | li $v1, 1 |
paul@58 | 597 | |
paul@58 | 598 | la $v0, DCH0SSIZ |
paul@15 | 599 | sw $v1, 0($v0) |
paul@15 | 600 | |
paul@57 | 601 | la $v0, DCH2SSIZ |
paul@57 | 602 | sw $v1, 0($v0) |
paul@57 | 603 | |
paul@3 | 604 | /* |
paul@5 | 605 | The source address is the physical address of the line data: |
paul@11 | 606 | DCHxSSA = physical(line data address) |
paul@3 | 607 | */ |
paul@1 | 608 | |
paul@58 | 609 | la $v0, DCH1SSA |
paul@38 | 610 | li $v1, SCREEN_BASE |
paul@38 | 611 | sw $v1, 0($v0) |
paul@3 | 612 | |
paul@3 | 613 | /* |
paul@58 | 614 | For the start and reset channels, a single byte of zero is transferred: |
paul@15 | 615 | DCHxSSA = physical(zero data address) |
paul@15 | 616 | */ |
paul@15 | 617 | |
paul@58 | 618 | la $v1, zerodata |
paul@57 | 619 | li $t8, KSEG0_BASE |
paul@57 | 620 | subu $v1, $v1, $t8 |
paul@58 | 621 | |
paul@58 | 622 | la $v0, DCH0SSA |
paul@57 | 623 | sw $v1, 0($v0) |
paul@57 | 624 | |
paul@57 | 625 | la $v0, DCH2SSA |
paul@15 | 626 | sw $v1, 0($v0) |
paul@15 | 627 | |
paul@15 | 628 | /* |
paul@11 | 629 | The destination has a size of 1 byte: |
paul@3 | 630 | DCHxDSIZ<15:0> = CHDSIZ<15:0> = 1 |
paul@3 | 631 | */ |
paul@3 | 632 | |
paul@58 | 633 | li $v1, 1 |
paul@58 | 634 | |
paul@3 | 635 | la $v0, DCH0DSIZ |
paul@3 | 636 | sw $v1, 0($v0) |
paul@3 | 637 | |
paul@15 | 638 | la $v0, DCH1DSIZ |
paul@15 | 639 | sw $v1, 0($v0) |
paul@15 | 640 | |
paul@57 | 641 | la $v0, DCH2DSIZ |
paul@57 | 642 | sw $v1, 0($v0) |
paul@57 | 643 | |
paul@3 | 644 | /* |
paul@15 | 645 | The destination address is the physical address of PORTB: |
paul@15 | 646 | DCHxDSA = physical(PORTB) |
paul@3 | 647 | */ |
paul@3 | 648 | |
paul@15 | 649 | li $v1, PORTB |
paul@3 | 650 | li $t8, KSEG1_BASE |
paul@3 | 651 | subu $v1, $v1, $t8 |
paul@58 | 652 | |
paul@58 | 653 | la $v0, DCH0DSA |
paul@3 | 654 | sw $v1, 0($v0) |
paul@3 | 655 | |
paul@15 | 656 | la $v0, DCH1DSA |
paul@15 | 657 | sw $v1, 0($v0) |
paul@15 | 658 | |
paul@57 | 659 | la $v0, DCH2DSA |
paul@57 | 660 | sw $v1, 0($v0) |
paul@57 | 661 | |
paul@7 | 662 | /* |
paul@7 | 663 | Use the block transfer completion interrupt to indicate when the source |
paul@7 | 664 | address can be updated. |
paul@7 | 665 | */ |
paul@7 | 666 | |
paul@3 | 667 | la $v0, DCH0INT |
paul@7 | 668 | li $v1, (1 << 19) /* CHBCIE = 1 */ |
paul@7 | 669 | sw $v1, 0($v0) |
paul@7 | 670 | |
paul@57 | 671 | la $v0, DCH1INT |
paul@57 | 672 | li $v1, (1 << 19) /* CHBCIE = 1 */ |
paul@57 | 673 | sw $v1, 0($v0) |
paul@57 | 674 | |
paul@7 | 675 | /* Enable interrupt for address updating. */ |
paul@7 | 676 | |
paul@7 | 677 | la $v0, IPC10 |
paul@57 | 678 | li $v1, 0b1111100011111 /* DMA1IP, DMA1IS, DMA0IP, DMA0IS = 0 */ |
paul@7 | 679 | sw $v1, CLR($v0) |
paul@7 | 680 | |
paul@7 | 681 | la $v0, IPC10 |
paul@57 | 682 | li $v1, 0b1111100011111 /* DMA1IP, DMA0IP = 7, DMA1IS, DMA0IS = 3 */ |
paul@7 | 683 | sw $v1, SET($v0) |
paul@7 | 684 | |
paul@7 | 685 | la $v0, IEC1 |
paul@57 | 686 | li $v1, (0b11 << 28) /* IEC1<29:28> = DMA1IE, DMA0IE = 1 */ |
paul@9 | 687 | sw $v1, SET($v0) |
paul@1 | 688 | |
paul@58 | 689 | /* Enable start channel. */ |
paul@3 | 690 | |
paul@3 | 691 | la $v0, DCH0CON |
paul@3 | 692 | li $v1, 0b10000000 |
paul@3 | 693 | sw $v1, SET($v0) |
paul@3 | 694 | |
paul@1 | 695 | jr $ra |
paul@1 | 696 | nop |
paul@1 | 697 | |
paul@15 | 698 | zerodata: |
paul@15 | 699 | .word 0 |
paul@15 | 700 | |
paul@1 | 701 | |
paul@1 | 702 | |
paul@9 | 703 | /* Utilities. */ |
paul@9 | 704 | |
paul@9 | 705 | handle_error_level: |
paul@9 | 706 | mfc0 $t3, CP0_STATUS |
paul@9 | 707 | li $t4, ~(STATUS_ERL | STATUS_EXL) |
paul@9 | 708 | and $t3, $t3, $t4 |
paul@9 | 709 | mtc0 $t3, CP0_STATUS |
paul@9 | 710 | jr $ra |
paul@9 | 711 | nop |
paul@9 | 712 | |
paul@9 | 713 | enable_interrupts: |
paul@9 | 714 | mfc0 $t3, CP0_STATUS |
paul@9 | 715 | li $t4, ~STATUS_IRQ /* Clear interrupt priority bits. */ |
paul@9 | 716 | and $t3, $t3, $t4 |
paul@9 | 717 | li $t4, ~STATUS_BEV /* CP0_STATUS &= ~STATUS_BEV (use non-bootloader vectors) */ |
paul@9 | 718 | and $t3, $t3, $t4 |
paul@9 | 719 | ori $t3, $t3, STATUS_IE |
paul@9 | 720 | mtc0 $t3, CP0_STATUS |
paul@9 | 721 | jr $ra |
paul@9 | 722 | nop |
paul@9 | 723 | |
paul@9 | 724 | init_interrupts: |
paul@9 | 725 | mfc0 $t3, CP0_DEBUG |
paul@9 | 726 | li $t4, ~DEBUG_DM |
paul@9 | 727 | and $t3, $t3, $t4 |
paul@9 | 728 | mtc0 $t3, CP0_DEBUG |
paul@9 | 729 | |
paul@9 | 730 | mfc0 $t3, CP0_STATUS |
paul@11 | 731 | li $t4, STATUS_BEV /* BEV = 1 or EBASE cannot be set */ |
paul@9 | 732 | or $t3, $t3, $t4 |
paul@9 | 733 | mtc0 $t3, CP0_STATUS |
paul@9 | 734 | |
paul@9 | 735 | la $t3, exception_handler |
paul@9 | 736 | mtc0 $t3, CP0_EBASE /* EBASE = exception_handler */ |
paul@9 | 737 | |
paul@9 | 738 | li $t3, 0x20 /* Must be non-zero or the CPU gets upset */ |
paul@9 | 739 | mtc0 $t3, CP0_INTCTL |
paul@9 | 740 | |
paul@9 | 741 | li $t3, CAUSE_IV /* IV = 1 (use EBASE+0x200 for interrupts) */ |
paul@9 | 742 | mtc0 $t3, CP0_CAUSE |
paul@9 | 743 | |
paul@9 | 744 | jr $ra |
paul@9 | 745 | nop |
paul@9 | 746 | |
paul@9 | 747 | |
paul@9 | 748 | |
paul@9 | 749 | /* Exception servicing. */ |
paul@9 | 750 | |
paul@9 | 751 | .section .flash, "a" |
paul@9 | 752 | |
paul@33 | 753 | /* TLB error servicing. */ |
paul@33 | 754 | |
paul@33 | 755 | tlb_handler: |
paul@9 | 756 | j exception_handler |
paul@9 | 757 | nop |
paul@9 | 758 | |
paul@9 | 759 | |
paul@9 | 760 | |
paul@33 | 761 | /* General exception servicing. */ |
paul@33 | 762 | |
paul@33 | 763 | .org 0x180 |
paul@33 | 764 | |
paul@33 | 765 | exception_handler: |
paul@33 | 766 | j exc_handler |
paul@33 | 767 | nop |
paul@33 | 768 | |
paul@33 | 769 | |
paul@45 | 770 | |
paul@9 | 771 | /* Interrupt servicing. */ |
paul@9 | 772 | |
paul@9 | 773 | .org 0x200 |
paul@9 | 774 | |
paul@9 | 775 | interrupt_handler: |
paul@9 | 776 | |
paul@38 | 777 | /* Store affected registers. */ |
paul@38 | 778 | |
paul@38 | 779 | li $k0, IRQ_STACK_LIMIT |
paul@38 | 780 | sw $v0, -4($k0) |
paul@38 | 781 | sw $v1, -8($k0) |
paul@38 | 782 | sw $s0, -12($k0) |
paul@38 | 783 | sw $s1, -16($k0) |
paul@38 | 784 | sw $s2, -20($k0) |
paul@38 | 785 | sw $s3, -24($k0) |
paul@38 | 786 | sw $t8, -28($k0) |
paul@38 | 787 | sw $ra, -32($k0) |
paul@38 | 788 | sw $sp, -36($k0) |
paul@38 | 789 | |
paul@38 | 790 | /* Load state. */ |
paul@38 | 791 | |
paul@38 | 792 | lw $s0, -44($k0) |
paul@38 | 793 | lw $s1, -48($k0) |
paul@38 | 794 | lw $s2, -52($k0) |
paul@38 | 795 | lw $s3, -56($k0) |
paul@38 | 796 | |
paul@38 | 797 | li $sp, IRQ_STACK_TOP |
paul@38 | 798 | |
paul@9 | 799 | /* Check for a timer interrupt condition. */ |
paul@9 | 800 | |
paul@9 | 801 | la $v0, IFS0 |
paul@9 | 802 | lw $v1, 0($v0) |
paul@9 | 803 | andi $v1, $v1, (1 << 9) /* T2IF */ |
paul@9 | 804 | beqz $v1, irq_dma |
paul@9 | 805 | nop |
paul@9 | 806 | |
paul@44 | 807 | /* Clear the timer interrupt condition. */ |
paul@44 | 808 | |
paul@44 | 809 | sw $v1, CLR($v0) |
paul@44 | 810 | |
paul@47 | 811 | /* |
paul@48 | 812 | The timer interrupt will only occur outside the visible region, but the |
paul@48 | 813 | interrupt condition will still occur as the timer wraps around. |
paul@47 | 814 | Therefore, the handling of other interrupts may find the timer interrupt |
paul@47 | 815 | condition set. |
paul@47 | 816 | |
paul@47 | 817 | For the visible region, the event handler is invoked when handling the |
paul@47 | 818 | DMA interrupt. Otherwise, the event handler is invoked in response to |
paul@47 | 819 | the timer interrupt. |
paul@47 | 820 | */ |
paul@47 | 821 | |
paul@47 | 822 | la $t8, visible_active |
paul@47 | 823 | beq $s1, $t8, irq_dma |
paul@47 | 824 | nop |
paul@47 | 825 | |
paul@47 | 826 | /* Increment the line counter (only outside the visible region). */ |
paul@9 | 827 | |
paul@9 | 828 | addiu $s0, $s0, 1 |
paul@9 | 829 | |
paul@47 | 830 | /* Jump to the event handler (only outside the visible region). */ |
paul@9 | 831 | |
paul@9 | 832 | jalr $s1 |
paul@9 | 833 | nop |
paul@9 | 834 | |
paul@9 | 835 | irq_dma: |
paul@9 | 836 | /* Check for a DMA interrupt condition. */ |
paul@9 | 837 | |
paul@9 | 838 | la $v0, IFS1 |
paul@9 | 839 | lw $v1, 0($v0) |
paul@57 | 840 | li $t8, (0b11 << 28) /* DMA1IF, DMA0IF */ |
paul@9 | 841 | and $v1, $v1, $t8 |
paul@9 | 842 | beqz $v1, irq_exit |
paul@9 | 843 | nop |
paul@9 | 844 | |
paul@44 | 845 | /* Clear the DMA interrupt condition. */ |
paul@44 | 846 | |
paul@44 | 847 | sw $v1, CLR($v0) |
paul@44 | 848 | |
paul@9 | 849 | /* Test the block transfer completion interrupt flag. */ |
paul@9 | 850 | |
paul@9 | 851 | la $v0, DCH0INT |
paul@9 | 852 | lw $v1, 0($v0) |
paul@9 | 853 | andi $v1, $v1, (1 << 3) /* CHBCIF */ |
paul@57 | 854 | beqz $v1, irq_dma_next |
paul@57 | 855 | nop |
paul@57 | 856 | |
paul@57 | 857 | /* Clear the block transfer completion interrupt flag. */ |
paul@57 | 858 | |
paul@57 | 859 | sw $v1, CLR($v0) |
paul@57 | 860 | |
paul@57 | 861 | irq_dma_next: |
paul@57 | 862 | /* Test the block transfer completion interrupt flag. */ |
paul@57 | 863 | |
paul@57 | 864 | la $v0, DCH1INT |
paul@57 | 865 | lw $v1, 0($v0) |
paul@57 | 866 | andi $v1, $v1, (1 << 3) /* CHBCIF */ |
paul@44 | 867 | beqz $v1, irq_exit |
paul@9 | 868 | nop |
paul@9 | 869 | |
paul@9 | 870 | /* Clear the block transfer completion interrupt flag. */ |
paul@9 | 871 | |
paul@9 | 872 | sw $v1, CLR($v0) |
paul@9 | 873 | |
paul@47 | 874 | /* |
paul@47 | 875 | The DMA interrupt should only be active within the visible region. |
paul@47 | 876 | The event handler is invoked here instead of in response to a timer |
paul@47 | 877 | interrupt within that region. |
paul@47 | 878 | */ |
paul@47 | 879 | |
paul@47 | 880 | /* Increment the line counter (only within the visible region). */ |
paul@47 | 881 | |
paul@47 | 882 | addiu $s0, $s0, 1 |
paul@47 | 883 | |
paul@47 | 884 | /* Jump to the event handler (only within the visible region). */ |
paul@47 | 885 | |
paul@47 | 886 | jalr $s1 |
paul@47 | 887 | nop |
paul@47 | 888 | |
paul@45 | 889 | /* Jump to the DMA update routine. */ |
paul@9 | 890 | |
paul@45 | 891 | j visible_update_address |
paul@45 | 892 | nop |
paul@42 | 893 | |
paul@9 | 894 | irq_exit: |
paul@38 | 895 | /* Save state. */ |
paul@38 | 896 | |
paul@38 | 897 | li $k0, IRQ_STACK_LIMIT |
paul@38 | 898 | sw $s0, -44($k0) |
paul@38 | 899 | sw $s1, -48($k0) |
paul@38 | 900 | sw $s2, -52($k0) |
paul@38 | 901 | sw $s3, -56($k0) |
paul@38 | 902 | |
paul@38 | 903 | /* Restore affected registers. */ |
paul@38 | 904 | |
paul@38 | 905 | lw $v0, -4($k0) |
paul@38 | 906 | lw $v1, -8($k0) |
paul@38 | 907 | lw $s0, -12($k0) |
paul@38 | 908 | lw $s1, -16($k0) |
paul@38 | 909 | lw $s2, -20($k0) |
paul@38 | 910 | lw $s3, -24($k0) |
paul@38 | 911 | lw $t8, -28($k0) |
paul@38 | 912 | lw $ra, -32($k0) |
paul@38 | 913 | lw $sp, -36($k0) |
paul@38 | 914 | |
paul@9 | 915 | eret |
paul@9 | 916 | nop |
paul@9 | 917 | |
paul@9 | 918 | |
paul@9 | 919 | |
paul@33 | 920 | exc_handler: |
paul@33 | 921 | li $t9, 0x80000000 |
paul@45 | 922 | mfc0 $t6, CP0_ERROREPC |
paul@33 | 923 | nop |
paul@33 | 924 | exc_loop: |
paul@33 | 925 | and $t7, $t9, $t6 |
paul@33 | 926 | beqz $t7, exc_errorepc_zero |
paul@33 | 927 | nop |
paul@33 | 928 | exc_errorepc_one: |
paul@33 | 929 | la $v0, PORTA |
paul@33 | 930 | li $v1, (1 << 2) /* PORTA<2> = RA2 */ |
paul@33 | 931 | sw $v1, SET($v0) |
paul@33 | 932 | j exc_loop_wait |
paul@33 | 933 | nop |
paul@33 | 934 | exc_errorepc_zero: |
paul@33 | 935 | la $v0, PORTA |
paul@33 | 936 | li $v1, (1 << 3) /* PORTA<3> = RA3 */ |
paul@33 | 937 | sw $v1, SET($v0) |
paul@33 | 938 | exc_loop_wait: |
paul@33 | 939 | li $t8, 5000000 |
paul@33 | 940 | exc_loop_delay: |
paul@33 | 941 | addiu $t8, $t8, -1 |
paul@33 | 942 | bnez $t8, exc_loop_delay |
paul@33 | 943 | nop |
paul@33 | 944 | la $v0, PORTA |
paul@33 | 945 | li $v1, (3 << 2) /* PORTA<3:2> = RA3, RA2 */ |
paul@33 | 946 | sw $v1, CLR($v0) |
paul@33 | 947 | exc_loop_wait_again: |
paul@33 | 948 | li $t8, 2500000 |
paul@33 | 949 | exc_loop_delay_again: |
paul@33 | 950 | addiu $t8, $t8, -1 |
paul@33 | 951 | bnez $t8, exc_loop_delay_again |
paul@33 | 952 | nop |
paul@33 | 953 | exc_errorepc_next: |
paul@33 | 954 | srl $t9, $t9, 1 |
paul@33 | 955 | bnez $t9, exc_loop |
paul@33 | 956 | nop |
paul@33 | 957 | j exc_handler |
paul@33 | 958 | nop |
paul@33 | 959 | |
paul@33 | 960 | |
paul@33 | 961 | |
paul@9 | 962 | /* Event routines. */ |
paul@9 | 963 | |
paul@9 | 964 | /* The vertical back porch. */ |
paul@9 | 965 | |
paul@9 | 966 | vbp_active: |
paul@9 | 967 | /* Test for visible region. */ |
paul@9 | 968 | |
paul@9 | 969 | sltiu $v0, $s0, VISIBLE_START |
paul@9 | 970 | bnez $v0, _vbp_active_ret |
paul@9 | 971 | nop |
paul@9 | 972 | |
paul@9 | 973 | /* Start the visible region. */ |
paul@9 | 974 | |
paul@9 | 975 | la $s1, visible_active |
paul@9 | 976 | |
paul@17 | 977 | /* Reset the line address. */ |
paul@17 | 978 | |
paul@17 | 979 | move $s2, $s3 |
paul@17 | 980 | |
paul@43 | 981 | /* Update the source address. */ |
paul@43 | 982 | |
paul@58 | 983 | la $v0, DCH1SSA |
paul@43 | 984 | sw $s2, 0($v0) |
paul@43 | 985 | |
paul@58 | 986 | /* Enable the start channel for timer event transfer initiation. */ |
paul@20 | 987 | |
paul@20 | 988 | la $v0, DCH0ECON |
paul@48 | 989 | li $v1, (1 << 4) /* DCH0ECON<4> = SIRQEN = 1 */ |
paul@20 | 990 | sw $v1, SET($v0) |
paul@20 | 991 | |
paul@9 | 992 | _vbp_active_ret: |
paul@9 | 993 | jr $ra |
paul@9 | 994 | nop |
paul@9 | 995 | |
paul@9 | 996 | |
paul@9 | 997 | |
paul@9 | 998 | /* The visible region. */ |
paul@9 | 999 | |
paul@9 | 1000 | visible_active: |
paul@9 | 1001 | /* Test for front porch. */ |
paul@9 | 1002 | |
paul@9 | 1003 | sltiu $v0, $s0, VFP_START |
paul@9 | 1004 | bnez $v0, _visible_active_ret |
paul@9 | 1005 | nop |
paul@9 | 1006 | |
paul@9 | 1007 | /* Start the front porch region. */ |
paul@9 | 1008 | |
paul@9 | 1009 | la $s1, vfp_active |
paul@9 | 1010 | |
paul@9 | 1011 | _visible_active_ret: |
paul@9 | 1012 | jr $ra |
paul@9 | 1013 | nop |
paul@9 | 1014 | |
paul@9 | 1015 | |
paul@9 | 1016 | |
paul@45 | 1017 | /* DMA update routine. */ |
paul@45 | 1018 | |
paul@45 | 1019 | visible_update_address: |
paul@45 | 1020 | |
paul@46 | 1021 | /* Test for the last visible line. */ |
paul@46 | 1022 | |
paul@46 | 1023 | la $v0, vfp_active |
paul@46 | 1024 | bne $s1, $v0, _visible_update_address |
paul@46 | 1025 | nop |
paul@46 | 1026 | |
paul@58 | 1027 | /* Disable the start channel. */ |
paul@46 | 1028 | |
paul@46 | 1029 | la $v0, DCH0ECON |
paul@48 | 1030 | li $v1, (1 << 4) /* DCH0ECON<4> = SIRQEN = 0 */ |
paul@46 | 1031 | sw $v1, CLR($v0) |
paul@46 | 1032 | |
paul@46 | 1033 | j _visible_update_ret |
paul@46 | 1034 | nop |
paul@46 | 1035 | |
paul@46 | 1036 | _visible_update_address: |
paul@46 | 1037 | |
paul@45 | 1038 | /* |
paul@45 | 1039 | Update the line data address if the line counter (referring to the |
paul@45 | 1040 | next line) is even. |
paul@45 | 1041 | */ |
paul@45 | 1042 | |
paul@45 | 1043 | andi $t8, $s0, 1 |
paul@45 | 1044 | bnez $t8, _visible_update_ret |
paul@45 | 1045 | nop |
paul@45 | 1046 | |
paul@45 | 1047 | /* Reference the next line and update the DMA source address. */ |
paul@45 | 1048 | |
paul@45 | 1049 | addiu $s2, $s2, LINE_LENGTH |
paul@45 | 1050 | |
paul@45 | 1051 | /* Test for wraparound. */ |
paul@45 | 1052 | |
paul@45 | 1053 | li $t8, (SCREEN_BASE + SCREEN_SIZE) |
paul@45 | 1054 | sltu $t8, $s2, $t8 |
paul@45 | 1055 | bnez $t8, _visible_dma_update |
paul@45 | 1056 | nop |
paul@45 | 1057 | |
paul@45 | 1058 | /* Reset the source address. */ |
paul@45 | 1059 | |
paul@45 | 1060 | li $s2, SCREEN_BASE |
paul@45 | 1061 | |
paul@45 | 1062 | _visible_dma_update: |
paul@45 | 1063 | |
paul@45 | 1064 | /* Update the source address. */ |
paul@45 | 1065 | |
paul@58 | 1066 | la $v0, DCH1SSA |
paul@45 | 1067 | sw $s2, 0($v0) |
paul@45 | 1068 | |
paul@45 | 1069 | _visible_update_ret: |
paul@45 | 1070 | j irq_exit |
paul@45 | 1071 | nop |
paul@45 | 1072 | |
paul@45 | 1073 | |
paul@45 | 1074 | |
paul@9 | 1075 | /* Within the vertical front porch. */ |
paul@9 | 1076 | |
paul@9 | 1077 | vfp_active: |
paul@9 | 1078 | /* Test for vsync. */ |
paul@9 | 1079 | |
paul@9 | 1080 | sltiu $v0, $s0, VSYNC_START |
paul@9 | 1081 | bnez $v0, _vfp_active_ret |
paul@9 | 1082 | nop |
paul@9 | 1083 | |
paul@9 | 1084 | /* Start the vsync. */ |
paul@9 | 1085 | |
paul@9 | 1086 | la $s1, vsync_active |
paul@9 | 1087 | |
paul@9 | 1088 | /* Bring vsync low when the next line starts. */ |
paul@9 | 1089 | |
paul@9 | 1090 | la $v0, OC2CON |
paul@9 | 1091 | li $v1, 0b010 | (1 << 15) /* OC2CON<2:0> = OCM<2:0> = 010 (single compare, output driven low) */ |
paul@9 | 1092 | sw $v1, 0($v0) |
paul@9 | 1093 | |
paul@9 | 1094 | _vfp_active_ret: |
paul@9 | 1095 | jr $ra |
paul@9 | 1096 | nop |
paul@9 | 1097 | |
paul@9 | 1098 | |
paul@9 | 1099 | |
paul@9 | 1100 | /* The vsync period. */ |
paul@9 | 1101 | |
paul@9 | 1102 | vsync_active: |
paul@9 | 1103 | /* Test for front porch. */ |
paul@9 | 1104 | |
paul@9 | 1105 | sltiu $v0, $s0, VSYNC_END |
paul@9 | 1106 | bnez $v0, _vsync_active_ret |
paul@9 | 1107 | nop |
paul@9 | 1108 | |
paul@9 | 1109 | /* Start the back porch. */ |
paul@9 | 1110 | |
paul@9 | 1111 | move $s0, $zero |
paul@9 | 1112 | la $s1, vbp_active |
paul@9 | 1113 | |
paul@9 | 1114 | /* Bring vsync high when the next line starts. */ |
paul@9 | 1115 | |
paul@9 | 1116 | la $v0, OC2CON |
paul@9 | 1117 | li $v1, 0b001 | (1 << 15) /* OC2CON<2:0> = OCM<2:0> = 001 (single compare, output driven high) */ |
paul@9 | 1118 | sw $v1, 0($v0) |
paul@9 | 1119 | |
paul@9 | 1120 | _vsync_active_ret: |
paul@9 | 1121 | jr $ra |
paul@9 | 1122 | nop |