2017-11-07 | Paul Boddie | file changeset files shortlog | Employ a basic CPU priority and keep the timer interrupt enabled (but not at CPU level), guarding priority changes by disabling and re-enabling the interrupt. The timer interrupt should probably be enabled during the active display period for the DMA channels to operate, even though circumstances appear to allow the channels to function in this configuration with the timer interrupt disabled. |
paul@41 | 1 | .globl message0 |
paul@41 | 2 | .globl message1 |
paul@41 | 3 | |
paul@41 | 4 | .section .flash, "a" |
paul@41 | 5 | |
paul@41 | 6 | message0: |
paul@41 | 7 | .string "Hello" |
paul@41 | 8 | |
paul@41 | 9 | message1: |
paul@41 | 10 | .string "Hello again" |