69:aa1ac5755f03
71:0c6e88eb049f
53:9b3b13a62733
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2017-11-07 |
Paul Boddie |
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Employ a basic CPU priority and keep the timer interrupt enabled (but not at CPU
level), guarding priority changes by disabling and re-enabling the interrupt.
The timer interrupt should probably be enabled during the active display period
for the DMA channels to operate, even though circumstances appear to allow the
channels to function in this configuration with the timer interrupt disabled. |
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mips.h vga.S
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68:ec19e9f803b5
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2017-11-06 |
Paul Boddie |
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Enable Timer3 interrupts in order to create timer events. |
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pic32.h vga.S
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67:22ebe789d830
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2017-11-06 |
Paul Boddie |
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Double the peripheral clock frequency for further timer usage. |
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vga.S vga.h
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66:64546519a57d
67:22ebe789d830 70:129ef681b3fc
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2017-11-06 |
Paul Boddie |
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Removed superfluous interrupt handling. |
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vga.S
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65:51c387b05002
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2017-11-06 |
Paul Boddie |
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Disabled the reset channel interrupt which appears superfluous for chaining as
well as needing to be handled at the CPU level. |
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vga.S
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64:0f2d331ec834
59:5d02b5c6d920
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2017-11-06 |
Paul Boddie |
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Test usage of Timer3 to initiate the reset channel cell transfer. |
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vga.S
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63:85305c169370
52:096262322f96
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2017-11-06 |
Paul Boddie |
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Test usage of Timer3 to initiate the reset channel cell transfer. |
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vga.S
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62:f1590f2ea5cb
53:9b3b13a62733
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2017-11-06 |
Paul Boddie |
changeset
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Test usage of Timer3 to initiate the reset channel cell transfer. |
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vga.S
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61:045ed8ec2160
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2017-11-04 |
Paul Boddie |
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A tentative sketch of how OC3 might drive line DMA transfers and the clock pulse
of a flip-flop. This does not work, perhaps because the OC3 events might not be
causing the DMA transfers. However, if OC3 interrupts are enabled they will most
likely cause interruptions that are too frequent and yet cannot be serviced
frequently enough for the DMA transfers to occur at the appropriate rate. |
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README.txt pic32.h vga.S vga.h
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60:ae02a1821af3
61:045ed8ec2160 73:83ebe9cd0314
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2017-11-04 |
Paul Boddie |
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Make DMA channel 1 the line channel. Things will only now work if the Timer2
interrupt is not disabled, for some reason. |
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vga.S
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