1.1 --- a/vga.S Fri Nov 17 17:22:46 2017 +0100
1.2 +++ b/vga.S Sat Nov 18 17:53:12 2017 +0100
1.3 @@ -115,7 +115,7 @@
1.4 li $t1, (1 << 3) /* PORTA<3> = RA3 */
1.5 sw $t1, CLR($t0)
1.6
1.7 - jal init_oc_pins
1.8 + jal init_io_pins
1.9 nop
1.10
1.11 /* Initialise the status register. */
1.12 @@ -146,6 +146,11 @@
1.13 jal init_oc
1.14 nop
1.15
1.16 + /* Initialise UART for debugging. */
1.17 +
1.18 + jal init_uart
1.19 + nop
1.20 +
1.21 /* Initialise the display state. */
1.22
1.23 li $s0, 0 /* line counter */
1.24 @@ -186,6 +191,10 @@
1.25 li $t1, (1 << 3) /* PORTA<3> = RA3 */
1.26 sw $t1, INV($t0)
1.27
1.28 + la $v0, U1TXREG
1.29 + li $v1, '.'
1.30 + sw $v1, 0($v0)
1.31 +
1.32 bnez $a1, loop /* until counter == 0 */
1.33 nop
1.34
1.35 @@ -374,7 +383,7 @@
1.36 jr $ra
1.37 nop
1.38
1.39 -init_oc_pins:
1.40 +init_io_pins:
1.41 /* Unlock the configuration register bits. */
1.42
1.43 la $v0, SYSKEY
1.44 @@ -401,6 +410,12 @@
1.45 li $v1, 0b0101 /* RPA1R<3:0> = 0101 (OC2) */
1.46 sw $v1, 0($v0)
1.47
1.48 + /* Map U1TX to RPB15. */
1.49 +
1.50 + la $v0, RPB15R
1.51 + li $v1, 0b0001 /* RPB15R<3:0> = 0001 (U1TX) */
1.52 + sw $v1, 0($v0)
1.53 +
1.54 la $v0, CFGCON
1.55 sw $t8, 0($v0)
1.56
1.57 @@ -612,6 +627,34 @@
1.58
1.59
1.60
1.61 +/* UART initialisation. */
1.62 +
1.63 +init_uart:
1.64 + /* Initialise UART. */
1.65 +
1.66 + la $v0, U1BRG
1.67 + li $v1, 12 /* U1BRG<15:0> = BRG = (FPB / (16 * baudrate)) - 1 = (24000000 / (16 * 115200)) - 1 = 12 */
1.68 + sw $v1, 0($v0)
1.69 +
1.70 + la $v0, U1MODE
1.71 + li $v1, (1 << 15) /* U1MODE<15> = ON = 0 */
1.72 + sw $v1, CLR($v0)
1.73 +
1.74 + /* Start UART. */
1.75 +
1.76 + la $v0, U1STA
1.77 + li $v1, (1 << 10) /* U1STA<10> = UTXEN = 1 */
1.78 + sw $v1, SET($v0)
1.79 +
1.80 + la $v0, U1MODE
1.81 + li $v1, (1 << 15) /* U1MODE<15> = ON = 1 */
1.82 + sw $v1, SET($v0)
1.83 +
1.84 + jr $ra
1.85 + nop
1.86 +
1.87 +
1.88 +
1.89 /* Utilities. */
1.90
1.91 handle_error_level:
1.92 @@ -796,44 +839,38 @@
1.93
1.94
1.95
1.96 +/* Exception handler. */
1.97 +
1.98 exc_handler:
1.99 - li $t9, 0x80000000
1.100 - mfc0 $t6, CP0_ERROREPC
1.101 + mfc0 $t7, CP0_ERROREPC
1.102 nop
1.103 +
1.104 +exc_write_word:
1.105 + li $t8, 32
1.106 + la $v0, U1TXREG
1.107 exc_loop:
1.108 - and $t7, $t9, $t6
1.109 - beqz $t7, exc_errorepc_zero
1.110 - nop
1.111 -exc_errorepc_one:
1.112 - la $v0, PORTA
1.113 - li $v1, (1 << 2) /* PORTA<2> = RA2 */
1.114 - sw $v1, SET($v0)
1.115 - j exc_loop_wait
1.116 + addiu $t8, $t8, -4
1.117 + srlv $v1, $t7, $t8 /* $v1 = $t7 >> $t8 */
1.118 + andi $v1, $v1, 0xF
1.119 + addiu $t9, $v1, -10 /* $t9 >= 10? */
1.120 + bgez $t9, exc_alpha
1.121 nop
1.122 -exc_errorepc_zero:
1.123 - la $v0, PORTA
1.124 - li $v1, (1 << 3) /* PORTA<3> = RA3 */
1.125 - sw $v1, SET($v0)
1.126 -exc_loop_wait:
1.127 - li $t8, 5000000
1.128 -exc_loop_delay:
1.129 - addiu $t8, $t8, -1
1.130 - bnez $t8, exc_loop_delay
1.131 +exc_digit:
1.132 + addiu $v1, $v1, 48 /* convert to digit: '0' */
1.133 + j exc_write
1.134 nop
1.135 - la $v0, PORTA
1.136 - li $v1, (3 << 2) /* PORTA<3:2> = RA3, RA2 */
1.137 - sw $v1, CLR($v0)
1.138 -exc_loop_wait_again:
1.139 - li $t8, 2500000
1.140 -exc_loop_delay_again:
1.141 - addiu $t8, $t8, -1
1.142 - bnez $t8, exc_loop_delay_again
1.143 +exc_alpha:
1.144 + addiu $v1, $v1, 55 /* convert to alpha: 'A' - 10 */
1.145 +exc_write:
1.146 + sw $v1, 0($v0)
1.147 + bnez $t8, exc_loop
1.148 nop
1.149 -exc_errorepc_next:
1.150 - srl $t9, $t9, 1
1.151 - bnez $t9, exc_loop
1.152 - nop
1.153 - j exc_handler
1.154 +exc_loop_end:
1.155 + li $v1, '\n'
1.156 + sw $v1, 0($v0)
1.157 +
1.158 +exc_handler_end:
1.159 + j exc_handler_end
1.160 nop
1.161
1.162