1.1 --- a/vga.S Sat Nov 04 21:47:48 2017 +0100
1.2 +++ b/vga.S Tue Nov 07 14:04:29 2017 +0100
1.3 @@ -284,8 +284,6 @@
1.4 la $v0, IPC2
1.5 li $v1, 0b11111
1.6 sw $v1, CLR($v0) /* T2IP, T2IS = 0 */
1.7 -
1.8 - la $v0, IPC2
1.9 li $v1, 0b11111
1.10 sw $v1, SET($v0) /* T2IP = 7; T2IS = 3 */
1.11
1.12 @@ -662,6 +660,7 @@
1.13 mfc0 $t3, CP0_STATUS
1.14 li $t4, ~STATUS_IRQ /* Clear interrupt priority bits. */
1.15 and $t3, $t3, $t4
1.16 + ori $t3, $t3, (3 << STATUS_IRQ_SHIFT)
1.17 li $t4, ~STATUS_BEV /* CP0_STATUS &= ~STATUS_BEV (use non-bootloader vectors) */
1.18 and $t3, $t3, $t4
1.19 ori $t3, $t3, STATUS_IE
1.20 @@ -937,6 +936,25 @@
1.21 li $v1, (1 << 4) /* DCH0ECON<4> = SIRQEN = 1 */
1.22 sw $v1, SET($v0)
1.23
1.24 + /*
1.25 + Suspend delivery of the timer interrupt during the visible period.
1.26 + The condition still occurs, however.
1.27 + */
1.28 +
1.29 + la $v0, IEC0
1.30 + li $v1, (1 << 9)
1.31 + sw $v1, CLR($v0) /* T2IE = 0 */
1.32 +
1.33 + la $v0, IPC2
1.34 + li $v1, 0b11111
1.35 + sw $v1, CLR($v0) /* T2IP, T2IS = 0 */
1.36 + li $v1, 0b00111
1.37 + sw $v1, SET($v0) /* T2IP = 1; T2IS = 3 */
1.38 +
1.39 + la $v0, IEC0
1.40 + li $v1, (1 << 9)
1.41 + sw $v1, SET($v0) /* T2IE = 0 */
1.42 +
1.43 _vbp_active_ret:
1.44 jr $ra
1.45 nop
1.46 @@ -956,6 +974,22 @@
1.47
1.48 la $s1, vfp_active
1.49
1.50 + /* Restore delivery of the timer interrupt after the visible period. */
1.51 +
1.52 + la $v0, IEC0
1.53 + li $v1, (1 << 9)
1.54 + sw $v1, CLR($v0) /* T2IE = 0 */
1.55 +
1.56 + la $v0, IPC2
1.57 + li $v1, 0b11111
1.58 + sw $v1, CLR($v0) /* T2IP, T2IS = 0 */
1.59 + li $v1, 0b11111
1.60 + sw $v1, SET($v0) /* T2IP = 7; T2IS = 3 */
1.61 +
1.62 + la $v0, IEC0
1.63 + li $v1, (1 << 9)
1.64 + sw $v1, SET($v0) /* T2IE = 1 */
1.65 +
1.66 _visible_active_ret:
1.67 jr $ra
1.68 nop