VGAPIC32

mips.h

17:4980cefab1ae
2017-05-16 Paul Boddie Introduced a screen start address register.
     1 #ifndef __MIPS_H__     2 #define __MIPS_H__     3      4 #define KSEG0_BASE	0x80000000     5 #define KSEG1_BASE	0xA0000000     6      7 #define CP0_INDEX	$0     8 #define CP0_ENTRYLO0	$2     9 #define CP0_ENTRYLO1	$3    10 #define CP0_CONTEXT	$4    11 #define CP0_PAGEMASK	$5    12 #define CP0_WIRED	$6    13 #define CP0_COUNT	$9    14 #define CP0_ENTRYHI	$10    15 #define CP0_COMPARE	$11    16 #define CP0_STATUS	$12    17 #define CP0_INTCTL	$12, 1    18 #define CP0_CAUSE	$13    19 #define CP0_EPC		$14    20 #define CP0_EBASE	$15, 1    21 #define CP0_CONFIG	$16    22 #define CP0_WATCHLO	$18    23 #define CP0_DEBUG	$23    24 #define CP0_TAGLO	$28    25 #define CP0_TAGHI	$29    26 #define CP0_ERROREPC	$30, 0    27     28 #define STATUS_CP0	0x10000000    29 #define STATUS_BEV	0x00400000    30 #define STATUS_IRQ	0x0000fc00    31 #define STATUS_UM	0x00000010    32 #define STATUS_ERL	0x00000004    33 #define STATUS_EXL	0x00000002    34 #define STATUS_IE	0x00000001    35     36 #define CAUSE_IV	0x00800000    37     38 #define EBASE_MASK	0x3ffff000    39     40 #define INTCTL_MASK	0x000003e0    41     42 #define DEBUG_DM	0x40000000    43     44 #define TLB_CACHED	0x00000018    45 #define TLB_UNCACHED	0x00000010    46 #define TLB_DIRTY	0x00000004    47 #define TLB_VALID	0x00000002    48 #define TLB_GLOBAL	0x00000001    49     50 #define TLB_READ	(TLB_CACHED | TLB_VALID)    51 #define TLB_WRITE	(TLB_CACHED | TLB_DIRTY | TLB_VALID)    52 #define TLB_ALL_READ	(TLB_CACHED | TLB_VALID | TLB_GLOBAL)    53 #define TLB_ALL_WRITE	(TLB_CACHED | TLB_DIRTY | TLB_VALID | TLB_GLOBAL)    54     55 #define CONFIG_K0	0x00000007    56 #define CONFIG_K0_UNCACHED		2    57 #define CONFIG_K0_CACHABLE_NONCOHERENT	3    58     59 #endif /* __MIPS_H__ */