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Disable and re-enable the line channel when setting the source address, even |
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Put character string, font and image data into separate files. |
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Added a tool to generate font definitions from GNU Unifont definitions. |
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Transition between the picture and the pattern. |
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Added register and display state saving and retrieval in the interrupt handler. |
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Write to KSEG0 instead of KSEG1. |
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Moved the framebuffer copying routine into a separate function. |
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Moved display definitions and framebuffer pattern generation to separate files. |
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Initialise system state before starting interrupts, preventing exceptions caused |
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Put the general exception handler in the proper location. |
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Added a link to an article about the project. |
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Added diagrams showing VGA signal, DMA transfer, and output circuit details. |
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Fixed sync pin assignment details. |
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Updated the circuit information. |
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Added a test pattern generating routine. |
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Fixed the number of visible display lines. |
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Updated the image to feature dithering and more realistic colours. |
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Use a suitable image for the I0RRGGBB representation. |
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Added copyright and licensing information. |
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Switched to using a I0RRGGBB colour representation. |
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Added a tool for simple image conversion to the appropriate pixel data format. |
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Test a 48MHz system clock, 24MHz peripheral clock, and 800 x 600 @ 60Hz output |
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Added missing operations to enable and disable the line channel. |
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Updated the documentation to indicate that RB6 is not available and that only |
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Added example image data and a sync instruction that seems to help the CPU |
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Introduced a screen start address register. |
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Fill the display by using a 30MHz clock and adjusted timings. |
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Switched to using PORTB instead of PMDIN for pixel data output. |
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Update the cache status in the config register. |
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Added initial documentation. |
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Fixed bitfield information in comment. |
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Tidied up the comments somewhat. |
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Simplified the horizontal line details; introduced bus arbitration mode 2 usage. |
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Introduced interrupt and exception initialisation fixes plus a revised state |
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Update the DMA source address without disabling the channel. |
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Added support for updating the line data address after every other transfer. |
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Added line address variable (to be used) and adjusted IRQ label names. |
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Introduced output compare usage with Timer2 to generate the hsync pulse for each |
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Switch to Timer2 usage from Timer1. |
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Tidied and incorporated some aspects of working PMP and DMA tests. |
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Added some definitions for memory areas and DMA. |
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Introduced the framework implementing different vertical signal periods. |
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An attempt to produce VGA output signals with a PIC32 device. |
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