# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1494798090 -7200
# Node ID 4a66779421fc8701b43f2482b941ade12b045959
# Parent  e6fa4e9b4e4f86e6d2356a9fa943024b1020e164
Simplified the horizontal line details; introduced bus arbitration mode 2 usage.

diff -r e6fa4e9b4e4f -r 4a66779421fc vga.S
--- a/vga.S	Sun May 14 13:29:13 2017 +0200
+++ b/vga.S	Sun May 14 23:41:30 2017 +0200
@@ -23,10 +23,8 @@
 #define LINE_LENGTH	160	/* pixels */
 
 #define HFREQ_LIMIT	1254	/* 40MHz cycles */
-#define LINE_LIMIT	960	/* 40MHz cycles (3 per byte/pixel) */
-#define HSYNC_LIMIT	96	/* 40MHz cycles (3 per byte/pixel) */
-
-#define HSYNC_START	LINE_LIMIT
+#define HSYNC_START	800	/* 40MHz cycles */
+#define HSYNC_LIMIT	96	/* 40MHz cycles */
 #define HSYNC_END	(HSYNC_START + HSYNC_LIMIT)
 
 #define VISIBLE_START	15	/* horizontal lines, back porch end */
@@ -79,8 +77,13 @@
 	*/
 
 	la $v0, BMXCON
-	li $v1, (1 << 6)	/* BMXCON<6> = BMXWSDRM = 0 */
-	sw $v1, CLR($v0)
+	lw $v1, 0($v0)
+	li $t8, ~(1 << 6)	/* BMXCON<6> = BMXWSDRM = 0 */
+	and $v1, $v1, $t8
+	li $t8, ~0b111		/* BMXCON<2:0> = BMXARB<2:0> = 0 */
+	ori $t8, $t8, 0b010	/* BMXCON<2:0> = BMXARB<2:0> = 2 */
+	and $v1, $v1, $t8
+	sw $v1, 0($v0)
 
 	/* Enable caching. */